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MOSFET, showing gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the body by an insulating layer (pink).

MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor), also known as the MOS transistor (metal–oxide–silicon transistor) or IGFET (Insulated-Gate Field-Effect Transistor), is a type of insulated-gate field-effect transistor that is fabricated by the controlled oxidation of a semiconductor (typically silicon) and utilizes an insulator (such as SiO₂) between the gate and the body. Today, the MOSFET is the most common type of transistor for both digital and analog circuits. The voltage of the gate terminal determines the electrical conductivity of the device; this ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals.

The MOSFET was invented by Mohamed M. Atalla and Dawon Kahng at Bell Labs in 1959, and first presented in 1960. It is the basic building block of modern electronics, and the most frequently manufactured device in history, with an estimated total of 13 sextillion (10²²) MOSFETs manufactured between 1960 and 2018.^[1] It is the dominant semiconductor device in digital and analog integrated circuits (ICs),^[2] and the most common power device.^[3] It is a compact transistor that has been miniaturised and mass-produced for a wide range of applications, revolutionizing the electronics industry and the world economy, and being central to the digital revolution, silicon age and information age. MOSFET scaling and miniaturization has been driving the rapid exponential growth of electronic semiconductor technology since the 1960s, and enables high-density ICs such as memory chips and microprocessors.

Overview[edit]

Individually packaged discrete MOSFETs

A key advantage of a MOSFET is that it requires almost no input current to control the load current, when compared with bipolar junction transistors (BJTs). In an enhancement mode MOSFET, voltage applied to the gate terminal can increase the conductivity from the "normally off" state. In a depletion mode MOSFET, voltage applied at the gate can reduce the conductivity from the "normally on" state.^[4] MOSFETs are also capable of high scalability, with increasing miniaturization, and can be easily scaled down to smaller dimensions. They also have faster switching speed (ideal for digital signals), much smaller size, consume significantly less power, and allow much higher density (ideal for large-scale integration), compared to BJTs. MOSFETs are also cheaper and have relatively simple processing steps, resulting in high manufacturing yield.

MOSFETs can either be manufactured as part of MOS integrated circuit chips or as discrete MOSFET devices (such as a power MOSFET), and can take the form of single-gate or multi-gate transistors. Since MOSFETs can be made with either p-type or n-type semiconductors (PMOS or NMOS logic, respectively), complementary pairs of MOSFETs can be used to make switching circuits with very low power consumption: CMOS (Complementary MOS) logic.

The name "metal–oxide–semiconductor" (MOS) typically refers to a metal gate, oxide insulation, and semiconductor (typically silicon).^[5] However, the "metal" in the name MOSFET is sometimes a misnomer, because the gate material can also be a layer of polysilicon (polycrystalline silicon). Because originally the gate was made from metal, the name metal-oxide semiconductor (MOS) stuck, as today the gates are typically made of polycrystalline sillicon, although in recent years, advancements in technology reintroduced metallic gates in order to solve various performance issues. Along with oxide, different dielectric materials can also be used with the aim of obtaining strong channels with smaller applied voltages. The MOS capacitor is also part of the MOSFET structure.

Process[edit]

Further information: doping, n-type semiconductor, and p-type semiconductor

The basic starting material for most integrated circuits based on MOSFET technology is typically Silicon (Si); though other processes such as silicon-germanium (Si_1−xGe_x) also exist. Silicon is a very brittle metalloid. It has the same structure as a diamond in elemental form (the actual structure is a 3D tetrahedral, just like carbon). It's a Group IV element - each silicon forming single covalent bonds with four adjacent silicon atoms. Because all of its valence electrons are involved in chemical bonds, pure silicon is quite a poor conductor of electricity. It's possible to raise the conductivity of silicon by introducing impurities, known as dopants, into the silicon lattice through a processes known as doping. Similar results can also be achieved by adding group V elements (which have 5 bonding electrons vs 4 for Si) such as phosphorus or arsenic. By inserting those group V elements into the silicon lattice it can still bond to the 4 original silicon atoms neighbors. The 5th valence electron is loosely bound to that group V element. The thermal vibrations is enough make that electron free to move - leaving positive ions and a free electron. It is this free electron that can carry current thereby increasing the conductivity of the lattice. The process forms a new semiconductor called an n-type semiconductor. The processes can be done with a group III element as well. This creates a situation where each atom is now short by an electron. The missing electron (or hole) propagates about the lattice. The hole acts as a positive carrier gaining the name p-type semiconductor.

A diode is the junction between p-type semiconductors and n-type semiconductors. When the voltage on the p-type semiconductors, known as anode, is raised above the n-type semiconductors, known as a cathode, the diode is said to be forward biased. When that happens, current flows. When the anode voltage is equal to or less than the cathode voltage, the diode is reverse biased - at which point very little current flows. Varying the voltage between the gate and body modulates the conductivity of this layer effectively controlling the current flow between drain and source.

MOS sandwich-like structure is created by superimposing several layers of conducting and insulating together. The actual process involves oxidation of the silicon, doping of the silicon using dopants, and etching of metal wires and contacts. Transistors are built on a pure and flawless single crystals of silicon. Each transistor consists of a body - the silicon wafer. The body is often grounded, often considered the reference node. Each transistor has a stack of the conducting gate that sits on top of an isolating glass (SiO2), and the substrate (also known as the body).

n-type semiconductor.

An nMOS transistor is built with a p-type body with two regions of n-type semiconductor adjacent to the gate called the source and the drain. For all practical purposes they are physically equivalent and can be used interchangeably. A pMOS transistor is built with an n-type body with two regions of p-type semiconductors adjacent to the gate.

Controlling Gate[edit]

Both pMOS and nMOS have a controlling gate. The controlling gate, as the name implies, controls the flow of electrons between the source and drain.

nMOS gate behavior[edit]

Main article: nMOS transistor

In the nMOS transistor, since the body is grounded, the p-n junctions of the source and drain to body are reverse-biased. If the voltage at the gate is raised, an electric field starts to build up - attracting free electrons to the underside of the Si-SiO2 interface. When the voltage is high enough, the electrons end up filling all the holes and a thin region under the gate called the channel gets inverted to act as an n-type semiconductor - creating a conducting path from the source to the drain, allowing current to flow. When the transistor is at that state, we say the transistor is ON. If the gate is grounded, little to no current flows through the reverse-biased junction. When that happens, we say the transistor is OFF.

pMOS gate behavior[edit]

Main article: pMOS transistor

p-type semiconductor.

In the pMOS transistor, the behavior and setup is the complement of the nMOS transistor. The body is held at positive voltage. When the gate is also positive - the source and drain are reverse-biased. When that happens, no current flows and we say the transistor is OFF.

When the voltage at the gate is lowered, positive charges are attracted to the underside of the Si-SiO2 interface. When the voltage gets sufficiently low the channel gets inverted - creating a conducting path from the source to the drain, allowing current to flow. Because the behavior of a pMOS transistor is the opposite of that of an nMOS transistor, the symbol for pMOS transistor is identical to that of nMOS with an additional bubble on the gate. That bubble is known as an inversion bubble.

When dealing with digital logic there are generally only have two distinct values - ON and OFF, 1 and 0, or HIGH and LOW. The positive voltage of the transistor is called VDD (or POWER or PWR). VDD represents the logic 1 value in digital circuits. In TTL logic, the VDD voltage levels were usually around 5 volts. Today's transistors cannot really withstand such high voltages - they are typically in the 1.5V to 3.3V range. The low voltage is often called GROUND (or GND or VSS). VSS represents the logic 0. It is also normally set to 0 volts.

Modes of operation[edit]

The operation of a MOSFET can be separated into three different modes, depending on the voltages at the terminals. In the following discussion, a simplified algebraic model is used.^[6] Modern MOSFET characteristics are more complex than the algebraic model presented here.^[7]

For an enhancement-mode, n-channel MOSFET, the three operational modes are:

Cutoff, subthreshold, and weak-inversion mode (n-channel MOSFET)

When V_GS < V_th:

where is gate-to-source bias and is the threshold voltage of the device.

According to the basic threshold model, the transistor is turned off, and there is no conduction between drain and source. A more accurate model considers the effect of thermal energy on the Fermi–Dirac distribution of electron energies which allow some of the more energetic electrons at the source to enter the channel and flow to the drain. This results in a subthreshold current that is an exponential function of gate–source voltage. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch, there is a weak-inversion current, sometimes called subthreshold leakage.

In weak inversion where the source is tied to bulk, the current varies exponentially with as given approximately by:^[8]^[9]

where = current at , the thermal voltage and the slope factor n is given by:

with = capacitance of the depletion layer and = capacitance of the oxide layer. This equation is generally used, but is only an adequate approximation for the source tied to the bulk. For the source not tied to the bulk, the subthreshold equation for drain current in saturation is^[10]^[11]

where the is the channel divider that is given by:

with = capacitance of the depletion layer and = capacitance of the oxide layer. In a long-channel device, there is no drain voltage dependence of the current once , but as channel length is reduced drain-induced barrier lowering introduces drain voltage dependence that depends in a complex way upon the device geometry (for example, the channel doping, the junction doping and so on). Frequently, threshold voltage V_th for this mode is defined as the gate voltage at which a selected value of current I_D0 occurs, for example, I_D0 = 1 μA, which may not be the same V_th-value used in the equations for the following modes.

Some micropower analog circuits are designed to take advantage of subthreshold conduction.^[12]^[13]^[14] By working in the weak-inversion region, the MOSFETs in these circuits deliver the highest possible transconductance-to-current ratio, namely: , almost that of a bipolar transistor.^[15]

The subthreshold I–V curve depends exponentially upon threshold voltage, introducing a strong dependence on any manufacturing variation that affects threshold voltage; for example: variations in oxide thickness, junction depth, or body doping that change the degree of drain-induced barrier lowering. The resulting sensitivity to fabricational variations complicates optimization for leakage and performance.^[16]^[17]

Triode mode or linear region, also known as the ohmic mode^[18]^[19] (n-channel MOSFET)

When V_GS > V_th and V_DS < V_GS − V_th:

The transistor is turned on, and a channel has been created which allows current between the drain and the source. The MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. The current from drain to source is modeled as:

where is the charge-carrier effective mobility, is the gate width, is the gate length and is the gate oxide capacitance per unit area. The transition from the exponential subthreshold region to the triode region is not as sharp as the equations suggest.

Saturation or active mode^[20]^[21] (n-channel MOSFET)

When V_GS > V_th and V_DS ≥ (V_GS – V_th):

The switch is turned on, and a channel has been created, which allows current between the drain and source. Since the drain voltage is higher than the source voltage, the electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. The onset of this region is also known as pinch-off to indicate the lack of channel region near the drain. Although the channel does not extend the full length of the device, the electric field between the drain and the channel is very high, and conduction continues. The drain current is now weakly dependent upon drain voltage and controlled primarily by the gate–source voltage, and modeled approximately as:

The additional factor involving λ, the channel-length modulation parameter, models current dependence on drain voltage due to the channel length modulation, effectively similar to the Early effect seen in bipolar devices. According to this equation, a key design parameter, the MOSFET transconductance is:

where the combination V_ov = V_GS − V_th is called the overdrive voltage,^[22] and where V_DSsat = V_GS − V_th accounts for a small discontinuity in which would otherwise appear at the transition between the triode and saturation regions.

Another key design parameter is the MOSFET output resistance given by:

.

r_out is the inverse of g_DS where . I_D is the expression in saturation region.

If λ is taken as zero, the resulting infinite output resistance can simplify circuit analysis, however this may lead to unrealistic circuit predictions, particularly in analog circuits.

As the channel length becomes very short, these equations become quite inaccurate. New physical effects arise. For example, carrier transport in the active mode may become limited by velocity saturation. When velocity saturation dominates, the saturation drain current is more nearly linear than quadratic in V_GS. At even shorter lengths, carriers transport with near zero scattering, known as quasi-ballistic transport. In the ballistic regime, the carriers travel at an injection velocity that may exceed the saturation velocity and approaches the Fermi velocity at high inversion charge density. In addition, drain-induced barrier lowering increases off-state (cutoff) current and requires an increase in threshold voltage to compensate, which in turn reduces the saturation current.

Symbols[edit]

There is no one standard that is commonly accepted across all organizations. Typically individual design groups adopt their own notations. Generally speaking, however, most follow the designs shown below which consists of a lone for the channel with the source and drain leaving it at right angles and then bending back at right angles outwards. Each device has a gate (G), drain (D), and a source (S), A distinction is sometimes made for enhancement mode where the channel is broken down into three smaller lines; it is sometimes drawn as a dotted line instead as well. Depletion mode devices have a solid line instead, this is due to the channel existing prior to power being applied.

Sometimes a fourth terminal for the body (B) is show. In discrete MOSFETs, the body lead is connected internally to the source. When that's the case, the body is also omitted from the symbol. When the bulk is shown, it is sometimes sometimes angled to meet up with the source. In ICs with a common bulk, the bulk is typically not shown and instead an inverting bubble is used to represent a PMOS.

Channel	Depletion MOSFET		Enhancement MOSFT
Channel	W/ bulk	W/O bulk	W/ bulk	W/O bulk
N-type
N-type
P-type
P-type

Early history[edit]

Background[edit]

Main article: field-effect transistor

The basic principle of the field-effect transistor (FET) was first proposed by Austrian physicist Julius Edgar Lilienfeld in 1926, when he filed the first patent for an insulated-gate field-effect transistor.^[23] Over the course of next two years he described various FET structures. In his configuration, aluminum formed the metal and aluminum oxide the oxide, while copper sulfide was used as a semiconductor. However, he was unable to build a practical working device.^[24] The FET concept was later also theorized by German engineer Oskar Heil in the 1930s and American physicist William Shockley in the 1940s.^[25] There was no working practical FET built at the time, and none of these early FET proposals involved thermally oxidized silicon.^[24]

Semiconductor companies initially focused on bipolar junction transistors (BJTs) in the early years of the semiconductor industry. However, the junction transistor was a relatively bulky device that was difficult to manufacture on a mass-production basis, which limited it to a number of specialised applications. FETs were theorized as potential alternatives to junction transistors, but researchers were unable to build practical FETs, largely due to the troublesome surface state barrier that prevented the external electric field from penetrating into the material.^[26] In the 1950s, researchers had largely given up on the FET concept, and instead focused on BJT technology.^[27]

Invention[edit]

Mohamed M. Atalla invented the MOSFET (MOS field-effect transistor) in 1959

Mohamed M. Atalla at Bell Labs was dealing with the problem of surface states in the late 1950s. He attempted to passivate the surface of silicon through the formation of oxide layer over it. He thought that growing a very thin high quality thermally grown SiO₂ on top of a clean silicon wafer would neutralize surface states enough to make a practical working field-effect transistor. He wrote his findings in his BTL memos in 1957, before presenting his work at an Electrochemical Society meeting in 1958.^[28]^[29]^[30]^[31]^[25] This was an important development that enabled MOS technology and silicon integrated circuit (IC) chips.^[32]

The MOSFET was invented when Mohamed Atalla and Dawon Kahng^[29]^[28] successfully fabricated the first working MOSFET device in November 1959.^[33] The device is covered by two patents, each filed separately by Atalla and Kahng in March 1960.^[34]^[35]^[36]^[37] They published their results in June 1960,^[38] at the Solid-State Device Conference held at Carnegie Mellon University.^[39] The same year, Atalla proposed the use of MOSFETs to build MOS integrated circuit (MOS IC) chips, noting the MOSFET's ease of fabrication.^[26]

Commercialization[edit]

The advantage of the MOSFET was that it was relatively compact and easy to mass-produce compared to the competing planar junction transistor,^[40] but the MOSFET represented a radically new technology, the adoption of which would have required spurning the progress that Bell had made with the bipolar junction transistor (BJT). The MOSFET was also initially slower and less reliable than the BJT.^[41]

In the early 1960s, MOS technology research programs were established by Fairchild Semiconductor, RCA Laboratories, General Microelectronics (led by former Fairchild engineer Frank Wanlass) and IBM.^[42] In 1962, Steve R. Hofstein and Fred P. Heiman at RCA built the first MOS integrated circuit chip. The following year, they collected all previous works on FETs and gave a theory of operation of the MOSFET.^[43] CMOS was developed by Chih-Tang Sah and Frank Wanlass at Fairchild in 1963.^[44] The first CMOS integrated circuit was later built in 1968 by Albert Medwin.^[45]

The first formal public announcement of the MOSFET's existence as a potential technology was made in 1963. It was then first commercialized by General Microelectronics in May 1964, followed Fairchild in October 1964. GMe's first MOS contract was with NASA, which used MOSFETs for spacecraft and satellites in the Interplanetary Monitoring Platform (IMP) program and Explorers Program.^[42] The early MOSFETs commercialized by General Microelectronics and Fairchild were p-channel (PMOS) devices for logic and switching applications.^[25] By the mid-1960s, RCA were using MOSFETs in their consumer products, including FM radio, television and amplifiers.^[46] In 1967, Bell Labs researchers Robert Kerwin, Donald Klein and John Sarace developed the self-aligned gate (silicon-gate) MOS transistor, which Fairchild researchers Federico Faggin and Tom Klein adapted for integrated circuits in 1968.^[47]

MOS revolution[edit]

Main article: MOS revolution

The development of the MOSFET led to a revolution in electronics technology, called the MOS revolution^[48] or MOSFET revolution,^[49] fuelling the technological and economic growth of the early semiconductor industry.

The impact of the MOSFET became commercially significant from the late 1960s onwards.^[50] This led to a revolution in the electronics industry, which has since impacted daily life in almost every way.^[51] The invention of the MOSFET has been cited as the birth of modern electronics^[52] and was central to the microcomputer revolution.^[53]

Importance[edit]

The MOSFET forms the basis of modern electronics,^[54] and is the basic element in most modern electronic equipment.^[55] It is the most common transistor in electronics,^[28] and the most widely used semiconductor device in the world.^[56] It has been described as the "workhorse of the electronics industry"^[57] and "the base technology" of the late 20th to early 21st centuries.^[27] MOSFET scaling and miniaturization (see List of semiconductor scale examples) have been the primary factors behind the rapid exponential growth of electronic semiconductor technology since the 1960s,^[58] as the rapid miniaturization of MOSFETs has been largely responsible for the increasing transistor density, increasing performance and decreasing power consumption of integrated circuit chips and electronic devices since the 1960s.^[59]

MOSFETs are capable of high scalability (Moore's law and Dennard scaling),^[60] with increasing miniaturization,^[61] and can be easily scaled down to smaller dimensions.^[62] They consume significantly less power, and allow much higher density, than bipolar transistors.^[63] MOSFETs can be much smaller than BJTs,^[64] about one-twentieth of the size by the early 1990s.^[64] MOSFETs also have faster switching speed,^[3] with rapid on–off electronic switching that makes them ideal for generating pulse trains,^[65] the basis for digital signals.^[66]^[67] In contrast to BJTs, which more slowly generate analog signals resembling sine waves,^[65] MOSFETs are also cheaper^[68] and have relatively simple processing steps, resulting in higher manufacturing yield.^[62] MOSFETs thus enable large-scale integration (LSI), and are ideal for digital circuits,^[69] as well as linear analog circuits.^[65]

The MOSFET has been variously described as the most important transistor,^[2] the most important device in the electronics industry,^[70] arguably the most important device in the computing industry,^[71] one of the most important developments in semiconductor technology,^[72] and possibly the most important invention in electronics.^[73] The MOSFET has been the fundamental building block of modern digital electronics,^[27] during the digital revolution,^[74] information revolution, information age,^[75] and silicon age.^[76]^[77] MOSFETs have been the driving force behind the computer revolution, and the technologies enabled by it.^[78]^[79]^[80] The rapid progress of the electronics industry during the late 20th to early 21st centuries was achieved by rapid MOSFET scaling (Dennard scaling and Moore's law), down to the level of nanoelectronics in the early 21st century.^[81] The MOSFET revolutionized the world during the information age, with its high density enabling a computer to exist on a few small IC chips rather than filling a room,^[82] and later making possible digital communications technology such as smartphones.^[78]

The MOSFET is the most widely manufactured device in history.^[83]^[84] The MOSFET generates annual sales of $295 billion as of 2015.^[85] Between 1960 and 2018, an estimated total of 13 sextillion MOS transistors have been manufactured, accounting for at least 99.9% of all transistors.^[83] Digital integrated circuits such as microprocessors and memory devices contain thousands to billions of integrated MOSFETs on each device, providing the basic switching functions required to implement logic gates and data storage. There are also memory devices which contain at least a trillion MOS transistors, such as a 256 GB microSD memory card, larger than the number of stars in the Milky Way galaxy.^[57] As of 2010, the operating principles of modern MOSFETs have remained largely the same as the original MOSFET first demonstrated by Mohamed Atalla and Dawon Kahng in 1960.^[86]^[87]

The US Patent and Trademark Office calls the MOSFET a "groundbreaking invention that transformed life and culture around the world"^[78] and the Computer History Museum credits it with "irrevocably changing the human experience."^[27] The MOSFET was also the basis for Nobel Prize winning breakthroughs such as the quantum Hall effect^[88] and the charge-coupled device (CCD),^[89] though there was never any Nobel Prize given for the MOSFET itself.^[90] In a 2018 note on Jack Kilby's Nobel Prize for Physics for his part in the invention of the integrated circuit, the Royal Swedish Academy of Sciences specifically mentioned the MOSFET and the microprocessor as other important inventions in the evolution of microelectronics.^[91] The MOSFET is also included on the list of IEEE milestones in electronics,^[92] and its inventors Mohamed Atalla and Dawon Kahng entered the National Inventors Hall of Fame in 2009.^[28]^[29]

Types of MOSFET[edit]

PMOS and NMOS logic[edit]

Main articles: PMOS logic and NMOS logic

See also: Depletion-load NMOS logic

P-channel MOS (PMOS) logic uses p-channel MOSFETs to implement logic gates and other digital circuits. N-channel MOS (NMOS) logic uses n-channel MOSFETs to implement logic gates and other digital circuits.

For devices of equal current driving capability, n-channel MOSFETs can be made smaller than p-channel MOSFETs, due to p-channel charge carriers (holes) having lower mobility than do n-channel charge carriers (electrons), and producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler. These were the driving principles in the design of NMOS logic which uses n-channel MOSFETs exclusively. However, unlike CMOS logic (neglecting leakage current), NMOS logic consumes power even when no switching is taking place.

Mohamed Atalla and Dawon Kahng originally demonstrated both pMOS and nMOS devices with 20 µm and then 10 µm gate lengths in 1960.^[30]^[93] Their original MOSFET devices also had a gate oxide thickness of 100 nm.^[94] However, the nMOS devices were impractical, and only the pMOS type were practical working devices.^[30] A more practical NMOS process was developed several years later. NMOS was initially faster than CMOS, thus NMOS was more widely used for computers in the 1970s.^[95] With advances in technology, CMOS logic displaced NMOS logic in the mid-1980s to become the preferred process for digital chips.

Complementary MOS (CMOS)[edit]

Main article: CMOS

The MOSFET is used in digital complementary metal–oxide–semiconductor (CMOS) logic,^[96] which uses p- and n-channel MOSFETs as building blocks. Overheating is a major concern in integrated circuits since ever more transistors are packed into ever smaller chips. CMOS logic reduces power consumption because no current flows (ideally), and thus no power is consumed, except when the inputs to logic gates are being switched. CMOS accomplishes this current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct and a low voltage on the gates causes the reverse. During the switching time as the voltage goes from one state to another, both MOSFETs will conduct briefly. This arrangement greatly reduces power consumption and heat generation.

CMOS was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963.^[44] CMOS had lower power consumption, but was initially slower than NMOS, which was more widely used for computers in the 1970s. In 1978, Hitachi introduced the twin-well CMOS process, which allowed CMOS to match the performance of NMOS with less power consumption. The twin-well CMOS process eventually overtook NMOS as the most common semiconductor manufacturing process for computers in the 1980s.^[95] By the 1970s–1980s, CMOS logic consumed over 7 times less power than NMOS logic,^[95] and about 100,000 times less power than bipolar transistor-transistor logic (TTL).^[97]

Depletion-mode[edit]

See also: Depletion and enhancement modes and Depletion-load NMOS logic

There are depletion-mode MOSFET devices, which are less commonly used than the standard enhancement-mode devices already described. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to source. To control the channel, a negative voltage is applied to the gate (for an n-channel device), depleting the channel, which reduces the current flow through the device. In essence, the depletion-mode device is equivalent to a normally closed (on) switch, while the enhancement-mode device is equivalent to a normally open (off) switch.^[98]

Due to their low noise figure in the RF region, and better gain, these devices are often preferred to bipolars in RF front-ends such as in TV sets.

Depletion-mode MOSFET families include BF960 by Siemens and Telefunken, and the BF980 in the 1980s by Philips (later to become NXP Semiconductors), whose derivatives are still used in AGC and RF mixer front-ends.

Metal–insulator–semiconductor FET (MISFET)[edit]

Metal–insulator–semiconductor field-effect-transistor,^[99]^[100]^[101] or MISFET, is a more general term than MOSFET and a synonym to insulated-gate field-effect transistor (IGFET). All MOSFETs are MISFETs, but not all MISFETs are MOSFETs.

The gate dielectric insulator in a MISFET is silicon dioxide in a MOSFET, but other materials can also be employed. The gate dielectric lies directly below the gate electrode and above the channel of the MISFET. The term metal is historically used for the gate material, even though now it is usually highly doped polysilicon or some other non-metal.

Insulator types may be:

Silicon dioxide, in MOSFETs
Organic insulators (e.g., undoped trans-polyacetylene; cyanoethyl pullulan, CEP^[102]), for organic-based FETs.^[101]

Floating-gate MOSFET (FGMOS)[edit]

Main article: Floating-gate MOSFET

The floating-gate MOSFET (FGMOS) is a type of MOSFET where the gate is electrically isolated, creating a floating node in DC and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. The first report of a floating-gate MOSFET (FGMOS) was made by Dawon Kahng (co-inventor of the original MOSFET) and Simon Min Sze in 1967.^[103]

The FGMOS is commonly used as a floating-gate memory cell, the digital storage element in EPROM, EEPROM and flash memories. Other uses of the FGMOS include a neuronal computational element in neural networks, analog storage element, digital potentiometers and single-transistor DACs.

Power MOSFET[edit]

Main article: Power MOSFET

See also: FET amplifier and Power electronics

Two power MOSFETs in D2PAK surface-mount packages. Operating as switches, each of these components can sustain a blocking voltage of 120 V in the off state, and can conduct a continuous current of 30 A in the on state, dissipating up to about 100 W and controlling a load of over 2000 W. A matchstick is pictured for scale.

Power MOSFETs have a different structure.^[104] As with most power devices, the structure is vertical and not planar. Using a vertical structure, it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the N-epitaxial layer (see cross section), while the current rating is a function of the channel width (the wider the channel, the higher the current). In a planar structure, the current and breakdown voltage ratings are both a function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the "silicon estate". With the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness (actually the N-epitaxial layer thickness) is proportional to the breakdown voltage.^[105]

Power MOSFETs with lateral structure are mainly used in high-end audio amplifiers and high-power PA systems. Their advantage is a better behaviour in the saturated region (corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Vertical MOSFETs are designed for switching applications.^[106]

The power MOSFET, which is commonly used in power electronics, was developed in the early 1970s.^[107] The power MOSFET enables low gate drive power, fast switching speed, and advanced paralleling capability.^[3]

Double-diffused MOS (DMOS)[edit]

Main articles: Power MOSFET and LDMOS

There are VDMOS (vertical double-diffused metal oxide semiconductor) and LDMOS (lateral double-diffused metal oxide semiconductor). Most power MOSFETs are made using this technology.

MOS capacitor[edit]

The MOS capacitor is part of the MOSFET structure, where the MOS capacitor is flanked by two p–n junctions.^[108] The MOS capacitor is widely used as a storage capacitor in memory chips, and as the basic building block of the charge-coupled device (CCD) in image sensor technology.^[109] In DRAM (dynamic random-access memory), each memory cell typically consists of a MOSFET and MOS capacitor.^[110]

Thin-film transistor (TFT)[edit]

Main article: Thin-film transistor

The thin-film transistor (TFT) is a type of MOSFET distinct from the standard bulk MOSFET.^[111] The first TFT was invented by Paul K. Weimer at RCA in 1962, building on the earlier work of Atalla and Kahng on MOSFETs.^[112]

The idea of a TFT-based liquid-crystal display (LCD) was conceived by Bernard Lechner of RCA Laboratories in 1968.^[113] Lechner, F. J. Marlowe, E. O. Nester and J. Tults demonstrated the concept in 1968 with an 18x2 matrix dynamic scattering LCD that used standard discrete MOSFETs, as TFT performance was not adequate at the time.^[114]

Bipolar–MOS transistors[edit]

Main articles: BiCMOS and Insulated-gate bipolar transistor

BiCMOS is an integrated circuit that combines BJT and CMOS transistors on a single chip.^[115]

The insulated-gate bipolar transistor (IGBT) is a power transistor with characteristics of both a MOSFET and bipolar junction transistor (BJT).^[116]

MOS sensors[edit]

A number of MOSFET sensors have been developed, for measuring physical, chemical, biological and environmental parameters.^[117] The earliest MOSFET sensors include the open-gate FET (OGFET) introduced by Johannessen in 1970,^[117] the ion-sensitive field-effect transistor (ISFET) invented by Piet Bergveld in 1970,^[118] the adsorption FET (ADFET) patented by P.F. Cox in 1974, and a hydrogen-sensitive MOSFET demonstrated by I. Lundstrom, M.S. Shivaraman, C.S. Svenson and L. Lundkvist in 1975.^[117] The ISFET is a special type of MOSFET with a gate at a certain distance,^[117] and where the metal gate is replaced by an ion-sensitive membrane, electrolyte solution and reference electrode.^[119]

By the mid-1980s, numerous other MOSFET sensors had been developed, including the gas sensor FET (GASFET), surface accessible FET (SAFET), charge flow transistor (CFT), pressure sensor FET (PRESSFET), chemical field-effect transistor (ChemFET), reference ISFET (REFET), biosensor FET (BioFET), enzyme-modified FET (ENFET) and immunologically modified FET (IMFET).^[117] By the early 2000s, BioFET types such as the DNA field-effect transistor (DNAFET), gene-modified FET (GenFET) and cell-potential BioFET (CPFET) had been developed.^[119]

The two main types of image sensors used in digital imaging technology are the charge-coupled device (CCD) and the active-pixel sensor (CMOS sensor). Both CCD and CMOS sensors are based on MOS technology, with the CCD based on MOS capacitors and the CMOS sensor based on MOS transistors.^[89]

Multi-gate MOSFET (MuGFET)[edit]

Main article: Multigate device

See also: FinFET

A FinFET (fin field-effect transistor), a type of multi-gate MOSFET.

The dual-gate MOSFET (DGMOS) has a tetrode configuration, where both gates control the current in the device. It is commonly used for small-signal devices in radio frequency applications where biasing the drain-side gate at constant potential reduces the gain loss caused by Miller effect, replacing two separate transistors in cascode configuration. Other common uses in RF circuits include gain control and mixing (frequency conversion). The tetrode description, though accurate, does not replicate the vacuum-tube tetrode. Vacuum-tube tetrodes, using a screen grid, exhibit much lower grid-plate capacitance and much higher output impedance and voltage gains than triode vacuum tubes. These improvements are commonly an order of magnitude (10 times) or considerably more. Tetrode transistors (whether bipolar junction or field-effect) do not exhibit improvements of such a great degree.

The FinFET is a double-gate silicon-on-insulator device, one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering. The fin refers to the narrow channel between source and drain. A thin insulating oxide layer on either side of the fin separates it from the gate. SOI FinFETs with a thick oxide on top of the fin are called double-gate and those with a thin oxide on top as well as on the sides are called triple-gate FinFETs.^[120]^[121]

A double-gate MOSFET transistor was first demonstrated in 1984 by Electrotechnical Laboratory researchers Toshihiro Sekigawa and Yutaka Hayashi.^[122]^[123] A GAAFET (gate-all-around MOSFET), a type of multi-gate non-planar 3D transistor, was first demonstrated in 1988 by a Toshiba research team including Fujio Masuoka, H. Takato and K. Sunouchi.^[124]^[125] The FinFET (fin field-effect transistor), a type of 3D non-planar double-gate MOSFET, originated from the research of Digh Hisamoto and his team at Hitachi Central Research Laboratory in 1989.^[126]^[127] The development of nanowire multi-gate MOSFETs have since become fundamental to nanoelectronics.^[128]

Quantum field-effect transistor (QFET)[edit]

Main article: QFET

A quantum field-effect transistor (QFET) or quantum well field-effect transistor (QWFET) is a type of MOSFET^[129]^[130]^[131] that takes advantage of quantum tunneling to greatly increase the speed of transistor operation.^[132]

Radiation-hardened-by-design (RHBD)[edit]

Semiconductor sub-micrometer and nanometer electronic circuits are the primary concern for operating within the normal tolerance in harsh radiation environments like outer space. One of the design approaches for making a radiation-hardened-by-design (RHBD) device is enclosed-layout-transistor (ELT). Normally, the gate of the MOSFET surrounds the drain, which is placed in the center of the ELT. The source of the MOSFET surrounds the gate. Another RHBD MOSFET is called H-Gate. Both of these transistors have very low leakage current with respect to radiation. However, they are large in size and take more space on silicon than a standard MOSFET. In older STI (shallow trench isolation) designs, radiation strikes near the silicon oxide region cause the channel inversion at the corners of the standard MOSFET due to accumulation of radiation induced trapped charges. If the charges are large enough, the accumulated charges affect STI surface edges along the channel near the channel interface (gate) of the standard MOSFET. Thus the device channel inversion occurs along the channel edges and the device creates an off-state leakage path, causing the device to turn on. So the reliability of circuits degrades severely. The ELT offers many advantages. These advantages include improvement of reliability by reducing unwanted surface inversion at the gate edges that occurs in the standard MOSFET. Since the gate edges are enclosed in ELT, there is no gate oxide edge (STI at gate interface), and thus the transistor off-state leakage is reduced considerably. Low-power microelectronic circuits including computers, communication devices and monitoring systems in the space shuttle and satellites are very different to what is used on earth. They require radiation (high-speed atomic particles like proton and neutron, solar flare magnetic energy dissipation in Earth's space, energetic cosmic rays like X-ray, gamma ray etc.) tolerant circuits. These special electronics are designed by applying different techniques using RHBD MOSFETs to ensure safer journeys and space-walks for astronauts.

Applications[edit]

Main article: MOS revolution

The MOSFET generally forms the basis of modern electronics,^[54] as the dominant transistor in digital circuits as well as analog integrated circuits.^[2] It is the basis for numerous modern technologies,^[133] and is commonly used for a wide range of applications.^[59] According to Jean-Pierre Colinge, numerous modern technologies would not exist without the MOSFET, such as the modern computer industry, digital telecommunication systems, video games, pocket calculators, and digital wristwatches, for example.^[133]

Discrete MOSFET devices are widely used in applications such as switch mode power supplies, variable-frequency drives and other power electronics applications where each device may be switching thousands of watts. Radio-frequency amplifiers up to the UHF spectrum use MOSFET transistors as analog signal and power amplifiers. Radio systems also use MOSFETs as oscillators, or mixers to convert frequencies. MOSFET devices are also applied in audio-frequency power amplifiers for public address systems, sound reinforcement and home and automobile sound systems.

MOSFETs in integrated circuits are the primary elements of computer processors, semiconductor memory, image sensors, and most other types of integrated circuits.

MOS integrated circuit (MOS IC)[edit]

See also: Integrated circuit, Invention of the integrated circuit, and Three-dimensional integrated circuit

The MOSFET is the most widely used type of transistor and the most critical device component in integrated circuit (IC) chips.^[134] The monolithic integrated circuit chip was enabled by the surface passivation process, which electrically stabilized silicon surfaces via thermal oxidation, making it possible to fabricate monolithic integrated circuit chips using silicon. The surface passivation process was developed by Mohamed M. Atalla at Bell Labs in 1957. This was the basis for the planar process, developed by Jean Hoerni at Fairchild Semiconductor in early 1959, which was critical to the invention of the monolithic integrated circuit chip by Robert Noyce later in 1959.^[135]^[136]^[32] The same year,^[25] Atalla used his surface passivation process to invent the MOSFET with Dawon Kahng at Bell Labs.^[29]^[28] This was followed by the development of clean rooms to reduce contamination to levels never before thought necessary, and coincided with the development of photolithography^[137] which, along with surface passivation and the planar process, allowed circuits to be made in few steps.

Mohamed Atalla first proposed the concept of the MOS integrated circuit (MOS IC) chip in 1960, noting that the MOSFET's ease of fabrication made it useful for integrated circuits.^[26] In contrast to bipolar transistors which required a number of steps for the p–n junction isolation of transistors on a chip, MOSFETs required no such steps but could be easily isolated from each other.^[41] Its advantage for integrated circuits was re-iterated by Dawon Kahng in 1961.^[33] The Si–SiO₂ system possessed the technical attractions of low cost of production (on a per circuit basis) and ease of integration. These two factors, along with its rapidly scaling miniaturization and low energy consumption, led to the MOSFET becoming the most widely used type of transistor in IC chips.

The earliest experimental MOS IC to be demonstrated was a 16-transistor chip built by Fred Heiman and Steven Hofstein at RCA in 1962.^[68] General Microelectronics later introduced the first commercial MOS integrated circuits in 1964, consisting of 120 p-channel transistors.^[138] It was a 20-bit shift register, developed by Robert Norman^[68] and Frank Wanlass.^[139] In 1968, Fairchild Semiconductor researchers Federico Faggin and Tom Klein developed the first silicon-gate MOS IC.^[47]

MOS large-scale integration (MOS LSI)[edit]

See also: Large-scale integration and Very large-scale integration

With its high scalability,^[60] and much lower power consumption and higher density than bipolar junction transistors,^[63] the MOSFET made it possible to build high-density IC chips.^[5] By 1964, MOS chips had reached higher transistor density and lower manufacturing costs than bipolar chips. MOS chips further increased in complexity at a rate predicted by Moore's law, leading to large-scale integration (LSI) with hundreds of MOSFETs on a chip by the late 1960s.^[140] MOS technology enabled the integration of more than 10,000 transistors on a single LSI chip by the early 1970s,^[141] before later enabling very large-scale integration (VLSI).^[62]^[142]

Microprocessors[edit]

See also: Microcontroller and Microprocessor chronology

The MOSFET was responsible for the invention of the microprocessor.^[143] The origins of both the microprocessor and the microcontroller can be traced back to the invention and development of MOS technology. The application of MOS LSI chips to computing was the basis for the first microprocessors, as engineers began recognizing that a complete computer processor could be contained on a single MOS LSI chip.^[140]

The earliest microprocessors were all MOS chips, built with MOS LSI circuits. The first multi-chip microprocessors, the Four-Phase Systems AL1 in 1969 and the Garrett AiResearch MP944 in 1970, were developed with multiple MOS LSI chips. The first commercial single-chip microprocessor, the Intel 4004, was developed by Federico Faggin, using his silicon-gate MOS IC technology, with Intel engineers Marcian Hoff and Stan Mazor, and Busicom engineer Masatoshi Shima.^[144] With the arrival of CMOS microprocessors in 1975, the term "MOS microprocessors" began to refer to chips fabricated entirely from PMOS logic or fabricated entirely from NMOS logic, contrasted with "CMOS microprocessors" and "bipolar bit-slice processors".^[145]

CMOS circuits[edit]

Main article: CMOS

Digital[edit]

The growth of digital technologies like the microprocessor has provided the motivation to advance MOSFET technology faster than any other type of silicon-based transistor.^[146] A big advantage of MOSFETs for digital switching is that the oxide layer between the gate and the channel prevents DC current from flowing through the gate, further reducing power consumption and giving a very large input impedance. The insulating oxide between the gate and channel effectively isolates a MOSFET in one logic stage from earlier and later stages, which allows a single output to drive a much larger number of inputs (the fan-out capacity) than BJT-based logic (such as TTL). This isolation also helps designers ignore loading effects between logic stages, to an extent dependent on the operating frequency: as frequencies increase, the input impedance of the MOSFETs decreases.

Analog[edit]

Further information: CMOS amplifier, RF CMOS, and Mixed-signal integrated circuit

The MOSFET's advantages in digital circuits do not translate into supremacy in all analog circuits. The two types of circuit draw upon different features of transistor behavior. Digital circuits switch, spending most of their time either fully on or fully off. The transition from one to the other is only of concern with regards to speed and charge required. Analog circuits depend on operation in the transition region where small changes to V_gs can modulate the output (drain) current. The JFET and bipolar junction transistor (BJT) are preferred for accurate matching (of adjacent devices in integrated circuits), higher transconductance and certain temperature characteristics which simplify keeping performance predictable as circuit temperature varies.

Nevertheless, MOSFETs are widely used in many types of analog circuits because of their own advantages (zero gate current, high and adjustable output impedance and improved robustness vs. BJTs which can be permanently degraded by even lightly breaking down the emitter-base). The characteristics and performance of many analog circuits can be scaled up or down by changing the sizes (length and width) of the MOSFETs used. By comparison, in bipolar transistors the size of the device does not significantly affect its performance. MOSFETs' ideal characteristics regarding gate current (zero) and drain-source offset voltage (zero) also make them nearly ideal switch elements, and also make switched capacitor analog circuits practical. In their linear region, MOSFETs can be used as precision resistors, which can have a much higher controlled resistance than BJTs. In high power circuits, MOSFETs sometimes have the advantage of not suffering from thermal runaway as BJTs do. Also, MOSFETs can be configured to perform as capacitors and gyrator circuits which allow op-amps made from them to appear as inductors, thereby allowing all of the normal analog devices on a chip (except for diodes, which can be made smaller than a MOSFET anyway) to be built entirely out of MOSFETs. This means that complete analog circuits can be made on a silicon chip in a much smaller space and with simpler fabrication techniques. MOSFETS are ideally suited to switch inductive loads because of tolerance to inductive kickback.

Some ICs combine analog and digital MOSFET circuitry on a single mixed-signal integrated circuit, making the needed board space even smaller. This creates a need to isolate the analog circuits from the digital circuits on a chip level, leading to the use of isolation rings and silicon on insulator (SOI). Since MOSFETs require more space to handle a given amount of power than a BJT, fabrication processes can incorporate BJTs and MOSFETs into a single device. Mixed-transistor devices are called bi-FETs (bipolar FETs) if they contain just one BJT-FET and BiCMOS (bipolar-CMOS) if they contain complementary BJT-FETs. Such devices have the advantages of both insulated gates and higher current density.

In the late 1980s, Asad Abidi pioneered RF CMOS technology, which uses MOS VLSI circuits, while working at UCLA. This changed the way in which RF circuits were designed, away from discrete bipolar transistors and towards CMOS integrated circuits. As of 2008, the radio transceivers in all wireless networking devices and modern mobile phones are mass-produced as RF CMOS devices. RF CMOS is also used in nearly all modern Bluetooth and wireless LAN (WLAN) devices.^[147]

MOS memory[edit]

Main article: MOS memory

Further information: Computer memory and Memory cell (computing)

The advent of the MOSFET enabled the practical use of MOS transistors as memory cell storage elements, a function previously served by magnetic cores in computer memory.^[148] The first modern computer memory was introduced in 1965, when John Schmidt at Fairchild Semiconductor designed the first MOS semiconductor memory, a 64-bit MOS SRAM (static random-access memory).^[149] SRAM became an alternative to magnetic-core memory, but required six MOS transistors for each bit of data.^[150]

MOS technology is the basis for DRAM (dynamic random-access memory). In 1966, Dr. Robert H. Dennard at the IBM Thomas J. Watson Research Center was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.^[150] In 1967, Dennard filed a patent under IBM for a single-transistor DRAM (dynamic random-access memory) memory cell, based on MOS technology.^[151] MOS memory enabled higher performance, was cheaper, and consumed less power, than magnetic-core memory, leading to MOS memory overtaking magnetic core memory as the dominant computer memory technology by the early 1970s.^[152]

Frank Wanlass, while studying MOSFET structures in 1963, noted the movement of charge through oxide onto a gate. While he did not pursue it, this idea would later become the basis for EPROM (erasable programmable read-only memory) technology.^[153] In 1967, Dawon Kahng and Simon Min Sze proposed that floating-gate memory cells, consisting of floating-gate MOSFETs (FGMOS), could be used to produce reprogrammable ROM (read-only memory).^[154] Floating-gate memory cells later became the basis for non-volatile memory (NVM) technologies including EPROM, EEPROM (electrically erasable programmable ROM) and flash memory.^[155]

Consumer electronics[edit]

MOSFETs are widely used in consumer electronics. One of the earliest influential consumer electronic products enabled by MOS LSI circuits was the electronic pocket calculator,^[141] as MOS LSI technology enabled large amounts of computational capability in small packages.^[156] In 1965, the Victor 3900 desktop calculator was the first MOS calculator, with 29 MOS chips.^[157] In 1967, the Texas Instruments Cal-Tech was the first prototype electronic handheld calculator, with three MOS LSI chips, and it was later released as the Canon Pocketronic in 1970.^[158] The Sharp QT-8D desktop calculator was the first mass-produced LSI MOS calculator in 1969,^[159] and the Sharp EL-8 which used four MOS LSI chips was the first commercial electronic handheld calculator in 1970.^[158] The first true electronic pocket calculator was the Busicom LE-120A HANDY LE, which used a single MOS LSI calculator-on-a-chip from Mostek, and was released in 1971.^[158] By 1972, MOS LSI circuits were commercialized for numerous other applications.^[160]

MOSFETs are fundamental to information and communications technology (ICT),^[78]^[91] including modern computers,^[161]^[133]^[142] modern computing,^[162] telecommunications, the communications infrastructure,^[161]^[163] the Internet,^[161]^[84]^[164] digital telephony,^[165] wireless telecommunications,^[166]^[167] and mobile networks.^[167] According to Colinge, the modern computer industry and digital telecommunication systems would not exist without the MOSFET.^[133] Advances in MOS technology has been the most important contributing factor in the rapid rise of network bandwidth in telecommunication networks, with bandwidth doubling every 18 months, from bits per second to terabits per second (Edholm's law).^[168]

MOS sensors[edit]

See also: Sensor, Image sensor, Charge-coupled device, and Active-pixel sensor

MOS sensors, also known as MOSFET sensors, are widely used to measure physical, chemical, biological and environmental parameters.^[117] The ion-sensitive field-effect transistor (ISFET), for example, is widely used in biomedical applications.^[119] MOS chemiresistors and MOSFETs have also been extensively shown to have promising applications is gas sensing either as single sensor devices or as components in chemical sensor arrays.^[169]

MOSFETs are also widely used in microelectromechanical systems (MEMS), as silicon MOSFETs could interact and communicate with the surroundings and process things such as chemicals, motions and light.^[170] An early example of a MEMS device is the resonant-gate transistor, an adaptation of the MOSFET, developed by Harvey C. Nathanson in 1965.^[171]

MOS technology is the basis for modern image sensors, including the charge-coupled device (CCD) and the CMOS active-pixel sensor (CMOS sensor), used in digital imaging and digital cameras.^[89] Willard Boyle and George E. Smith developed the CCD in 1969. While researching the MOS process, they realized that an electric charge was the analogy of the magnetic bubble and that it could be stored on a tiny MOS capacitor. As it was fairly straightforward to fabricate a series of MOS capacitors in a row, they connected a suitable voltage to them so that the charge could be stepped along from one to the next.^[89] The CCD is a semiconductor circuit that was later used in the first digital video cameras for television broadcasting.^[172]

The MOS active-pixel sensor (APS) was developed by Tsutomu Nakamura at Olympus in 1985.^[173] The CMOS active-pixel sensor was later developed by Eric Fossum and his team at NASA's Jet Propulsion Laboratory in the early 1990s.^[174]

MOS image sensors are widely used in optical mouse technology. The first optical mouse, invented by Richard F. Lyon at Xerox in 1980, used a 5 µm NMOS sensor chip.^[175]^[176] Since the first commercial optical mouse, the IntelliMouse introduced in 1999, most optical mouse devices use CMOS sensors.^[177]

Power MOSFETs[edit]

See also: Power MOSFET, LDMOS#Applications, VMOS, FET amplifier, IGBT, MOS-controlled thyristor, Power electronics, and Power semiconductor device

The power MOSFET is the most widely used power device in the world.^[3] Advantages over bipolar junction transistors in power electronics include MOSFETs not requiring a continuous flow of drive current to remain in the ON state, offering higher switching speeds, lower switching power losses, lower on-resistances, and reduced susceptibility to thermal runaway.^[178] The power MOSFET had an impact on power supplies, enabling higher operating frequencies, size and weight reduction, and increased volume production.^[179]

Switching power supplies are the most common applications for power MOSFETs.^[65] They are also widely used for MOS RF power amplifiers, which enabled the transition of mobile networks from analog to digital in the 1990s. This led to the wide proliferation of wireless mobile networks, which revolutionised telecommunication systems.^[166] The LDMOS in particular is the most widely used power amplifier in mobile networks, such as 2G, 3G,^[166] 4G, and 5G.^[167] Over 50 billion discrete power MOSFETs are shipped annually, as of 2018. They are widely used for automotive, industrial and communications systems in particular.^[180] Power MOSFETs are commonly used in automotive electronics, particularly as switching devices in electronic control units,^[181] and as power converters in modern electric vehicles.^[182] The insulated-gate bipolar transistor (IGBT), a hybrid MOS-bipolar transistor, is also used for a wide variety of applications.^[183]

Scaling[edit]

See also: Dennard scaling, Moore's law, Transistor count, and Edholm's law

Trend of Intel CPU transistor gate length

Over the past decades, the MOSFET (as used for digital logic) has continually been scaled down in size; typical MOSFET channel lengths were once several micrometres, but modern integrated circuits are incorporating MOSFETs with channel lengths of tens of nanometers. Robert Dennard's work on scaling theory was pivotal in recognising that this ongoing reduction was possible. The semiconductor industry maintains a "roadmap", the ITRS,^[184] which sets the pace for MOSFET development. Historically, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process, the need to use very low voltages, and with poorer electrical performance necessitating circuit redesign and innovation (small MOSFETs exhibit higher leakage currents and lower output resistance). As of 2019, the smallest MOSFETs in production are 5 nm FinFET semiconductor nodes, manufactured by Samsung Electronics and TSMC.^[185]^[186]

Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area. Since fabrication costs for a semiconductor wafer are relatively fixed, the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the price per chip. In fact, over the past 30 years the number of transistors per chip has been doubled every 2–3 years once a new technology node is introduced. For example, the number of MOSFETs in a microprocessor fabricated in a 45 nm technology can well be twice as many as in a 65 nm chip. This doubling of transistor density was first observed by Gordon Moore in 1965 and is commonly referred to as Moore's law.^[187] It is also expected that smaller transistors switch faster. For example, one approach to size reduction is a scaling of the MOSFET that requires all device dimensions to reduce proportionally. The main device dimensions are the channel length, channel width, and oxide thickness. When they are scaled down by equal factors, the transistor channel resistance does not change, while gate capacitance is cut by that factor. Hence, the RC delay of the transistor scales with a similar factor. While this has been traditionally the case for the older technologies, for the state-of-the-art MOSFETs reduction of the transistor dimensions does not necessarily translate to higher chip speed because the delay due to interconnections is more significant.

Producing MOSFETs with channel lengths much smaller than a micrometre is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. Though processes such as atomic layer deposition (ALD) have improved fabrication for small components, the small size of the MOSFET (less than a few tens of nanometers) has created operational problems:

Higher subthreshold conduction: As MOSFET geometries shrink, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the on case and low current in the off case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips.^[188]^[189]
Increased gate-oxide leakage: The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the quantum mechanical phenomenon of electron tunneling occurs between the gate and channel, leading to increased power consumption. Silicon dioxide has traditionally been used as the gate insulator. Silicon dioxide however has a modest dielectric constant. Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance (capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness). All else equal, a higher dielectric thickness reduces the quantum tunneling current through the dielectric between the gate and the channel. Insulators that have a larger dielectric constant than silicon dioxide (referred to as high-κ dielectrics), such as group IVb metal silicates e.g. hafnium and zirconium silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards. On the other hand, the barrier height of the new gate insulator is an important consideration; the difference in conduction band energy between the semiconductor and the dielectric (and the corresponding difference in valence band energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 eV. For many alternative dielectrics the value is significantly lower, tending to increase the tunneling current, somewhat negating the advantage of higher dielectric constant. The maximum gate–source voltage is determined by the strength of the electric field able to be sustained by the gate dielectric before significant leakage occurs. As the insulating dielectric is made thinner, the electric field strength within it goes up for a fixed voltage. This necessitates using lower voltages with the thinner dielectric.
Increased junction leakage: To make devices smaller, junction design has become more complex, leading to higher doping levels, shallower junctions, "halo" doping and so forth,^[190]^[191] all to decrease drain-induced barrier lowering (see the section on junction design). To keep these complex junctions in place, the annealing steps formerly used to remove damage and electrically active defects must be curtailed^[192] increasing junction leakage. Heavier doping is also associated with thinner depletion layers and more recombination centers that result in increased leakage current, even without lattice damage.
Drain-induced barrier lowering (DIBL) and V_T roll off: Because of the short-channel effect, channel formation is not entirely done by the gate, but now the drain and source also affect the channel formation. As the channel length decreases, the depletion regions of the source and drain come closer together and make the threshold voltage (V_T) a function of the length of the channel. This is called V_T roll-off. V_T also becomes function of drain to source voltage V_DS. As we increase the V_DS, the depletion regions increase in size, and a considerable amount of charge is depleted by the V_DS. The gate voltage required to form the channel is then lowered, and thus, the V_T decreases with an increase in V_DS. This effect is called drain induced barrier lowering (DIBL).
Lower output resistance: For analog operation, good gain requires a high MOSFET output impedance, which is to say, the MOSFET current should vary only slightly with the applied drain-to-source voltage. As devices are made smaller, the influence of the drain competes more successfully with that of the gate due to the growing proximity of these two electrodes, increasing the sensitivity of the MOSFET current to the drain voltage. To counteract the resulting decrease in output resistance, circuits are made more complex, either by requiring more devices, for example the cascode and cascade amplifiers, or by feedback circuitry using operational amplifiers, for example a circuit like that in the adjacent figure.
Lower transconductance: The transconductance of the MOSFET decides its gain and is proportional to hole or electron mobility (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance.
Interconnect capacitance: Traditionally, switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, interconnect capacitance (the capacitance of the metal-layer connections between different parts of the chip) is becoming a large percentage of capacitance.^[193]^[194] Signals have to travel through the interconnect, which leads to increased delay and lower performance.
Heat production: The ever-increasing density of MOSFETs on an integrated circuit creates problems of substantial localized heat generation that can impair circuit operation. Circuits operate more slowly at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling devices and methods are now required for many integrated circuits including microprocessors. Power MOSFETs are at risk of thermal runaway. As their on-state resistance rises with temperature, if the load is approximately a constant-current load then the power loss rises correspondingly, generating further heat. When the heatsink is not able to keep the temperature low enough, the junction temperature may rise quickly and uncontrollably, resulting in destruction of the device.
Process variations: With MOSFETs becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions: length, width, junction depths, oxide thickness etc., and become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain, more statistical. The random nature of manufacture means we do not know which particular example MOSFETs actually will end up in a particular instance of the circuit. This uncertainty forces a less optimal design because the design must work for a great variety of possible component MOSFETs. See process variation, design for manufacturability, reliability engineering, and statistical process control.^[195]
Modeling challenges: Modern ICs are computer-simulated with the goal of obtaining working circuits from the very first manufactured lot. As devices are miniaturized, the complexity of the processing makes it difficult to predict exactly what the final devices look like, and modeling of physical processes becomes more challenging as well. In addition, microscopic variations in structure due simply to the probabilistic nature of atomic processes require statistical (not just deterministic) predictions. These factors combine to make adequate simulation and "right the first time" manufacture difficult.

A related scaling rule is Edholm's law. In 2004, Phil Edholm observed that the bandwidth of telecommunication networks (including the Internet) is doubling every 18 months.^[196] Over the course of several decades, the bandwidths of communication networks has risen from bits per second to terabits per second. The rapid rise in telecommunication bandwidth is largely due to the same MOSFET scaling that enables Moore's law, as telecommunication networks are built from MOSFETs.^[168]

Timeline[edit]

Main article: List of semiconductor scale examples

See also: Semiconductor device fabrication and Transistor density

PMOS and NMOS[edit]

PMOS and NMOS demonstrations
Date	Channel length	Oxide thickness^[197]	MOSFET logic	Researcher(s)	Organization	Ref
1960-06	20,000 nm	100 nm	PMOS	Mohamed M. Atalla, Dawon Kahng	Bell Telephone Laboratories	^[198]^[199]
	20,000 nm	100 nm	NMOS	Mohamed M. Atalla, Dawon Kahng	Bell Telephone Laboratories	^[198]^[199]
	10,000 nm	100 nm	PMOS	Mohamed M. Atalla, Dawon Kahng	Bell Telephone Laboratories	^[200]
	10,000 nm	100 nm	NMOS	Mohamed M. Atalla, Dawon Kahng	Bell Telephone Laboratories	^[200]
1965-05	8,000 nm	150 nm	NMOS	Chih-Tang Sah, Otto Leistiko, A.S. Grove	Fairchild Semiconductor	^[201]
1965-05	5,000 nm	170 nm	PMOS	Chih-Tang Sah, Otto Leistiko, A.S. Grove	Fairchild Semiconductor	^[201]
1972-12	1,000 nm	?	PMOS	Hwa-Nien Yu, Robert H. Dennard, Fritz H. Gaensslen	IBM T.J. Watson Research Center	^[202]^[203]^[204]
1973	7,500 nm	?	NMOS	Sohichi Suzuki	NEC	^[205]^[206]
1973	6,000 nm	?	PMOS	?	Toshiba	^[207]^[208]
1974-10	1,000 nm	35 nm	NMOS	Hwa-Nien Yu, Robert H. Dennard, Fritz H. Gaensslen	IBM T.J. Watson Research Center	^[209]
1974-10	500 nm	35 nm	NMOS	Hwa-Nien Yu, Robert H. Dennard, Fritz H. Gaensslen	IBM T.J. Watson Research Center	^[209]
1975-09	1,500 nm	20 nm	NMOS	Ryoichi Hori, Hiroo Masuda, Osamu Minato	Hitachi	^[203]^[210]
1976-03	3,000 nm	?	NMOS	?	Intel	^[211]
1979-04	1,000 nm	25 nm	NMOS	William R. Hunter, L. M. Ephrath, Alice Cramer	IBM T.J. Watson Research Center	^[212]
1984-12	100 nm	5 nm	NMOS	Toshio Kobayashi, Seiji Horiguchi, K. Kiuchi	Nippon Telegraph and Telephone	^[213]
1985-12	150 nm	2.5 nm	NMOS	Toshio Kobayashi, Seiji Horiguchi, M. Miyake, M. Oda	Nippon Telegraph and Telephone	^[214]
1985-12	75 nm	?	NMOS	Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis	MIT	^[215]
1986-01	60 nm	?	NMOS	Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis	MIT	^[216]
1986-12	60 nm	?	?	Ghavam G. Shahidi, Dimitri A. Antoniadis, Henry I. Smith	MIT	^[217]^[218]^[216]
1987-05	400 nm	10 nm	NMOS	Bijan Davari, Chung-Yu Ting, Kie Y. Ahn, S. Basavaiah	IBM T.J. Watson Research Center	^[219]
1987-06	200 nm	3.5 nm	PMOS	Toshio Kobayashi, M. Miyake, K. Deguchi	Nippon Telegraph and Telephone	^[220]
1993-12	40 nm	?	NMOS	Mizuki Ono, Masanobu Saito, Takashi Yoshitomi	Toshiba	^[221]
1996-09	16 nm	?	PMOS	Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba	NEC	^[222]
1998-06	50 nm	1.3 nm	NMOS	Khaled Z. Ahmed, Effiong E. Ibok, Miryeong Song	Advanced Micro Devices (AMD)	^[223]^[224]
2002-12	6 nm	?	PMOS	Bruce Doris, Omer Dokumaci, Meikei Ieong	IBM	^[225]^[226]^[227]
2003-12	3 nm	?	PMOS	Hitoshi Wakabayashi, Shigeharu Yamagami	NEC	^[228]^[226]
2003-12	3 nm	?	NMOS	Hitoshi Wakabayashi, Shigeharu Yamagami	NEC	^[228]^[226]

CMOS (single-gate)[edit]

CMOS demonstrations (single-gate)
Date	Channel length	Oxide thickness^[197]	Researcher(s)	Organization	Ref
1963-02	?	?	Chih-Tang Sah, Frank Wanlass	Fairchild Semiconductor	^[44]^[229]
1968	20,000 nm	100 nm	?	RCA Laboratories	^[230]
1970	10,000 nm	100 nm	?	RCA Laboratories	^[230]
1976-12	2,000 nm	?	A. Aitken, R.G. Poulsen, A.T.P. MacArthur, J.J. White	Mitel Semiconductor	^[231]
1978-02	3,000 nm	?	Toshiaki Masuhara, Osamu Minato, Toshio Sasaki, Yoshio Sakai	Hitachi Central Research Laboratory	^[232]^[233]^[234]
1983-02	1,200 nm	25 nm	R.J.C. Chwang, M. Choi, D. Creek, S. Stern, P.H. Pelley	Intel	^[235]^[236]
1983-02	900 nm	15 nm	Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima	Nippon Telegraph and Telephone (NTT)	^[235]^[237]
1983-12	1,000 nm	22.5 nm	G.J. Hu, Yuan Taur, Robert H. Dennard, Chung-Yu Ting	IBM T.J. Watson Research Center	^[238]
1987-02	800 nm	17 nm	T. Sumi, Tsuneo Taniguchi, Mikio Kishimoto, Hiroshige Hirano	Matsushita	^[235]^[239]
1987-02	700 nm	12 nm	Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima	Nippon Telegraph and Telephone (NTT)	^[235]^[240]
1987-09	500 nm	12.5 nm	Hussein I. Hanafi, Robert H. Dennard, Yuan Taur, Nadim F. Haddad	IBM T.J. Watson Research Center	^[241]
1987-12	250 nm	?	Naoki Kasai, Nobuhiro Endo, Hiroshi Kitajima	NEC	^[242]
1988-02	400 nm	10 nm	M. Inoue, H. Kotani, T. Yamada, Hiroyuki Yamauchi	Matsushita	^[235]^[243]
1990-12	100 nm	?	Ghavam G. Shahidi, Bijan Davari, Yuan Taur, James D. Warnock	IBM T.J. Watson Research Center	^[244]
1993	350 nm	?	?	Sony	^[245]
1996	150 nm	?	?	Mitsubishi Electric	^[245]
1998	180 nm	?	?	TSMC	^[246]
2003-12	5 nm	?	Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki Ikezawa	NEC	^[228]^[247]

Multi-gate MOSFET (MuGFET)[edit]

Multi-gate MOSFET demonstrations
Date	Channel length	MuGFET type	Researcher(s)	Organization	Ref
1987	2,000 nm	DGMOS	Toshihiro Sekigawa	Electrotechnical Laboratory (ETL)	^[248]
1988-12	250 nm	DGMOS	Bijan Davari, Wen-Hsing Chang, Matthew R. Wordeman, C.S. Oh	IBM T.J. Watson Research Center	^[249]^[250]
	180 nm	DGMOS	Bijan Davari, Wen-Hsing Chang, Matthew R. Wordeman, C.S. Oh	IBM T.J. Watson Research Center	^[249]^[250]
	?	GAAFET	Fujio Masuoka, Hiroshi Takato, Kazumasa Sunouchi, N. Okabe	Toshiba	^[251]^[252]^[253]
1989-12	200 nm	FinFET	Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, Eiji Takeda	Hitachi Central Research Laboratory	^[254]^[255]^[256]
1998-12	17 nm	FinFET	Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor	University of California (Berkeley)	^[128]^[257]
2001	15 nm	FinFET	Chenming Hu, Yang‐Kyu Choi, Nick Lindert, Tsu-Jae King Liu	University of California (Berkeley)	^[128]^[258]
2002-12	10 nm	FinFET	Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor	University of California (Berkeley)	^[128]^[259]
2006-06	3 nm	GAAFET	Hyunjin Lee, Yang-kyu Choi, Lee-Eun Yu, Seong-Wan Ryu	KAIST	^[260]^[261]

Other types of MOSFET[edit]

Other MOSFET demonstrations
Date	Channel length (nm)	Oxide thickness (nm)^[197]	MOSFET type	Researcher(s)	Organization	Ref
1962-10	?	?	TFT	Paul K. Weimer	RCA Laboratories	^[262]^[134]
1965	?	?	GaAs	H. Becke, R. Hall, J. White	RCA Laboratories	^[263]
1966-10	100,000	100	TFT	T.P. Brody, H.E. Kunig	Westinghouse Electric	^[264]^[265]
1967-08	?	?	FGMOS	Dawon Kahng, Simon Min Sze	Bell Telephone Laboratories	^[266]
1967-10	?	?	MNOS	H.A. Richard Wegener, A.J. Lincoln, H.C. Pao	Sperry Corporation	^[267]
1968-07	?	?	BiMOS	Hung-Chang Lin, Ramachandra R. Iyer	Westinghouse Electric	^[268]^[269]
1968-10	?	?	BiCMOS	Hung-Chang Lin, Ramachandra R. Iyer, C.T. Ho	Westinghouse Electric	^[270]^[269]
1969	?	?	VMOS	?	Hitachi	^[271]^[272]
1969-09	?	?	DMOS	Y. Tarui, Y. Hayashi, Toshihiro Sekigawa	Electrotechnical Laboratory (ETL)	^[273]^[274]
1970-10	?	?	ISFET	Piet Bergveld	University of Twente	^[275]^[276]
1970-10	1000	?	DMOS	Y. Tarui, Y. Hayashi, Toshihiro Sekigawa	Electrotechnical Laboratory (ETL)	^[277]
1977	?	?	VDMOS	John Louis Moll	HP Labs	^[271]
1977	?	?	LDMOS	?	Hitachi	^[278]
1979-07	?	?	IGBT	Bantval Jayant Baliga, Margaret Lazeri	General Electric	^[279]
1984-12	2000	?	BiCMOS	H. Higuchi, Goro Kitsukawa, Takahide Ikeda, Y. Nishio	Hitachi	^[280]
1985-05	300	?	?	K. Deguchi, Kazuhiko Komatsu, M. Miyake, H. Namatsu	Nippon Telegraph and Telephone	^[281]
1985-02	1000	?	BiCMOS	H. Momose, Hideki Shibata, S. Saitoh, Jun-ichi Miyamoto	Toshiba	^[282]
1986-11	90	8.3	?	Han-Sheng Lee, L.C. Puzio	General Motors	^[283]
1987-09	?	10	?	Hussein I. Hanafi, Ting, Chung-Yu, Ahn, Kie Y.	IBM T.J. Watson Research Center	^[284]
1987-12	800	?	BiCMOS	Robert H. Havemann, R. E. Eklund, Hiep V. Tran	Texas Instruments	^[285]
1997-06	30	?	EJ-MOSFET	Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba	NEC	^[286]
1998	32	?	?	?	NEC	^[226]
1999	8	?	?	?	NEC	^[226]
2000-04	8	?	EJ-MOSFET	Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba	NEC	^[287]

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External links[edit]

How Semiconductors and Transistors Work (MOSFETs) WeCanFigureThisOut.org
Understanding power MOSFET data sheet parameters – Nexperia PDF Application Note AN11158
An introduction to depletion-mode MOSFETs
Power MOSFETs
Criteria for Successful Selection of IGBT and MOSFET Modules
MOSFET Process Step by Step A Flash slide showing the fabricating process of a MOSFET in detail
MOSFET Calculator
Advanced MOSFET issues
MOSFET applet
(1998) Application Manual IGBT and MOSFET Power Modules, 1st, ISLE Verlag. ISBN 978-3-932633-24-9.
(2011) PDF-Version, 2nd, Nuremberg: Semikron. ISBN 978-3-938843-66-6.
MIT Open Courseware 6.002 – Spring 2007
MIT Open Courseware 6.012 – Fall 2009
Georgia Tech BJT and FET Slides
CircuitDesign: MOS Diffusion Parasitics
Course on Physics of Nanoscale Transistors
Notes on Ballistic MOSFETs

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@@ Line 1: / Line 1: @@
-{{title|MOSFET - Metal-Oxide-Semiconductor Field-Effect-Transistor}}[[File:Electronic component mosfets.jpg|thumb|[[discrete logic chips|Individually packaged]] MOSFETs]]
+{{title|MOSFET - Metal-Oxide-Semiconductor Field-Effect-Transistor}}
+{{semi devices}}
+[[File:MOSFET Structure.png|thumb|MOSFET, showing [[metal gate|gate]] (G), body (B), source (S) and drain (D) terminals. The gate is separated from the body by an [[gate oxide|insulating layer]] (pink).]]
 '''MOSFET''' ('''Metal-Oxide-Semiconductor Field-Effect-Transistor'''), also known as the '''MOS transistor''' ('''metal–oxide–silicon transistor''') or '''IGFET''' ('''Insulated-Gate Field-Effect Transistor'''), is a type of insulated-gate [[field-effect transistor]] that is fabricated by the [[thermal oxidation|controlled oxidation]] of a [[semiconductor]] (typically [[silicon]]) and utilizes an insulator (such as [[wikipedia:Silicon dioxide|SiO<sub>2</sub>]]) between the gate and the body. Today, the MOSFET is the most common type of [[transistor]] for both digital and analog circuits. The voltage of the [[gate oxide|gate terminal]] determines the [[electrical conductivity]] of the device; this ability to change conductivity with the amount of applied voltage can be used for [[amplifier|amplifying]] or switching [[signal (electrical engineering)|electronic signals]].
 The MOSFET was invented by [[Mohamed M. Atalla]] and [[Dawon Kahng]] at [[Bell Labs]] in 1959, and first presented in 1960. It is the basic building block of modern electronics, and the [[List of best-selling electronic devices|most frequently manufactured device]] in history, with an estimated total of 13 sextillion (10<sup>22</sup>) MOSFETs manufactured between 1960 and 2018.<ref>{{cite book|title=13 Sextillion & Counting: The Long & Winding Road to the Most Frequently Manufactured Human Artifact in History|url=https://computerhistory.org/blog/13-sextillion-counting-the-long-winding-road-to-the-most-frequently-manufactured-human-artifact-in-history/|last=Laws|first=David|date=April 2, 2018|publisher=Computer History Museum|access-date=May 5, 2020}}</ref> It is the dominant [[semiconductor device]] in [[Digital electronics|digital]] and [[Analogue electronics|analog]] [[integrated circuits]] (ICs),<ref name="Ashley" /> and the most common [[power device]].<ref name="aosmd" /> It is a compact [[transistor]] that has been miniaturised and mass-produced for a [[List of MOSFET applications|wide range of applications]], revolutionizing the [[electronics industry]] and the world economy, and being central to the [[digital revolution]], [[silicon age]] and [[information age]]. MOSFET scaling and miniaturization has been driving the rapid exponential growth of electronic semiconductor technology since the 1960s, and enables [[Very Large Scale Integration|high-density ICs]] such as [[memory chip]]s and [[microprocessors]].
+== Overview ==
+[[File:Electronic component mosfets.jpg|thumb|[[discrete logic chips|Individually packaged]] discrete MOSFETs]]
 A key advantage of a MOSFET is that it requires almost no input current to control the load current, when compared with [[bipolar junction transistors]] (BJTs). In an ''[[enhancement mode]]'' MOSFET, voltage applied to the gate terminal can increase the conductivity from the "normally off" state. In a ''[[depletion mode]]'' MOSFET, voltage applied at the gate can reduce the conductivity from the "normally on" state.<ref name="depletion">{{cite book |title=Electronic Circuits |chapter=§8.2 The depletion mode MOSFET |chapter-url=https://books.google.com/books?id=ggpVToC2obIC&pg=SA8-PA2|page=812 |first1=U. A. |last1=Bakshi |first2=A. P.|last2=Godse |isbn=978-81-8431-284-3 |year=2007 |publisher=Technical Publications}}</ref> MOSFETs are also capable of high scalability, with increasing [[miniaturization]], and can be easily scaled down to smaller dimensions. They also have faster switching speed (ideal for [[digital signal]]s), much smaller size, consume significantly less power, and allow much higher density (ideal for [[large-scale integration]]), compared to BJTs. MOSFETs are also cheaper and have relatively simple processing steps, resulting in high [[manufacturing yield]].
@@ Line 10: / Line 16: @@
 The name "metal–oxide–semiconductor" (MOS) typically refers to a [[metal gate]], [[gate oxide|oxide insulation]], and semiconductor (typically silicon).<ref name="computerhistory-transistor" /> However, the "metal" in the name MOSFET is sometimes a misnomer, because the gate material can also be a layer of [[polysilicon]] (polycrystalline silicon). Because originally the [[controlling gate|gate]] was made from metal, the name metal-oxide semiconductor (MOS) stuck, as today the gates are typically made of polycrystalline sillicon, although in recent years, advancements in technology reintroduced metallic gates in order to solve various performance issues. Along with [[oxide]], different [[dielectric]] materials can also be used with the aim of obtaining strong channels with smaller applied voltages. The MOS capacitor is also part of the MOSFET structure.
-== Overview ==
 ===Process===
 {{further|doping|n-type semiconductor|p-type semiconductor}}
@@ Line 39: / Line 44: @@
 When dealing with [[digital logic]] there are generally only have two distinct values - ON and OFF, 1 and 0, or HIGH and LOW. The positive voltage of the transistor is called VDD (or POWER or PWR). VDD represents the logic 1 value in digital circuits. In TTL logic, the VDD voltage levels were usually around 5 volts. Today's transistors cannot really withstand such high voltages - they are typically in the 1.5V to 3.3V range. The low voltage is often called GROUND (or GND or VSS). VSS represents the logic 0. It is also normally set to 0 volts.
-== Modes of operation ==
+=== Modes of operation ===
-{{empty section}}
+The operation of a MOSFET can be separated into three different modes, depending on the voltages at the terminals. In the following discussion, a simplified algebraic model is used.<ref name=Hodges>{{cite article|first1=H.|last1= Shichman  |first2=D. A.|last2=Hodges  |name-list-style=amp |title=Modeling and simulation of insulated-gate field-effect transistor switching circuits |journal=IEEE Journal of Solid-State Circuits |volume=SC-3 |issue=3 |pages=285–89 |year=1968 |doi=10.1109/JSSC.1968.1049902 |bibcode= 1968IJSSC...3..285S }}</ref> Modern MOSFET characteristics are more complex than the algebraic model presented here.<ref name=Hu>For example, see {{cite book
+ |title=MOSFET modeling & BSIM3 user's guide
+ |url=https://books.google.com/books?id=R5DP56qUql4C
+ |isbn=978-0-7923-8575-2 |year=1999 |publisher=Springer
+ |first1=Yuhua|last1=Cheng
+ |first2=Chenming|last2=Hu
+}}. The most recent version of the [[BSIM]] model is described in {{cite article
+ |title=BSIM-CMG 106.1.0beta Multi-Gate MOSFET Compact Model
+ |first1=Sriramkumar|last1=V.
+ |first2=Navid|last2=Paydavosi
+ |first3=Darsen|last3=Lu
+ |first4=Chung-Hsun|last4=Lin
+ |first5=Mohan|last5=Dunga
+ |first6=Shijing|last6=Yao
+ |first7=Tanvir|last7=Morshed
+ |first8=Ali|last8=Niknejad
+ |first9=Chenming|last9=Hu
+ |name-list-style=amp
+ |url=http://www-device.eecs.berkeley.edu/bsim/Files/BSIMCMG/BSIMCMG106.0.0/BSIMCMG106.0.0_TechnicalManual_20120313.pdf
+ |year=2012
+ |publisher=Department of EE and CS, UC Berkeley
+ |access-date=2012-04-01
+ |url-status=dead
+ |archive-url=https://web.archive.org/web/20140727084407/http://www-device.eecs.berkeley.edu/bsim/Files/BSIMCMG/BSIMCMG106.0.0/BSIMCMG106.0.0_TechnicalManual_20120313.pdf
+ |archive-date=2014-07-27
+}}</ref>
+For an ''enhancement-mode, n-channel MOSFET'', the three operational modes are:
+; Cutoff, subthreshold, and weak-inversion mode (n-channel MOSFET)
+When ''V''<sub>GS</sub> &lt; ''V''<sub>th</sub>:
+where <math>V_\text{GS}</math> is gate-to-source bias and <math>V_\text{th}</math> is the [[threshold voltage]] of the device.
+According to the basic threshold model, the transistor is turned off, and there is no conduction between drain and source. A more accurate model considers the effect of thermal energy on the [[Fermi–Dirac distribution]] of electron energies which allow some of the more energetic electrons at the source to enter the channel and flow to the drain. This results in a subthreshold current that is an exponential function of gate–source voltage. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch, there is a weak-inversion current, sometimes called subthreshold leakage.
+In weak inversion where the source is tied to bulk, the current varies exponentially with <math>V_\text{GS}</math> as given approximately by:<ref name=Gray-Meyer>
+{{ cite book
+ | first1 = P. R. | last1=Gray
+ | first2=P. J. | last2=Hurst
+ | first3=S. H. | last3=Lewis
+ | first4=R. G. | last4=Meyer
+ | name-list-style=amp
+ | title=Analysis and Design of Analog Integrated Circuits
+ | year = 2001
+ | pages=66–67
+ | edition=Fourth
+ | publisher = Wiley
+ | location=New York
+ | isbn=978-0471321682
+ | url = http://worldcat.org/isbn/0471321680
+}}</ref><ref name=vanRoermund>
+{{ cite book
+ | first1 = P. R. | last1=van der Meer
+ | first2=A. | last2=van Staveren
+ | first3=A. H. M. | last3=van Roermund
+ | title = Low-Power Deep Sub-Micron CMOS Logic: Subthreshold Current Reduction
+ | year = 2004
+ | page=78
+ | publisher=Springer
+ | location=Dordrecht
+ | isbn = 978-1-4020-2848-9
+ | url=https://books.google.com/books?id=nyken8ivkb8C&pg=PA78
+}}</ref>
+: <math>I_\text{D} \approx I_\text{D0} e^\frac{V_\text{GS} - V_\text{th}}{nV_\text{T}}, </math>
+where <math>I_\text{D0}</math> = current at <math>V_\text{GS} = V_\text{th}</math>, the thermal voltage <math>V_\text{T} = kT/q</math> and the slope factor ''n'' is given by:
+: <math>n = 1 + \frac{C_\text{dep}}{C_\text{ox}}, \, </math>
+with <math>C_\text{dep}</math> = capacitance of the depletion layer and <math>C_\text{ox}</math> = capacitance of the oxide layer. This equation is generally used, but is only an adequate approximation for the source tied to the bulk. For the source not tied to the bulk, the subthreshold equation for drain current in saturation is<ref>{{cite article|last=Degnan|first=Brian|title=Wikipedia fails subvt|url=https://sites.google.com/site/degnan68k/semiconductors/wikipedia-fails-subvt}}</ref><ref>{{cite book|last=Mead|first=Carver|title=Analog VLSI and Neural Systems|year=1989|publisher=Addison-Wesley|location=Reading, MA|isbn=9780201059922|page=[https://archive.org/details/analogvlsineural00mead/page/370 370]|url-access=registration|url=https://archive.org/details/analogvlsineural00mead/page/370}}</ref>
+: <math>I_\text{D} \approx I_\text{D0} e^\frac{\kappa \left(V_\text{G} - V_\text{th}\right) - V_\text{S}}{V_\text{T}}, </math>
+where the <math>\kappa</math> is the channel divider that is given by:
+: <math>\kappa = \frac{C_\text{ox}}{{C_\text{ox} + C_\text{D}}}, </math>
+with <math>C_\text{D}</math> = capacitance of the depletion layer and <math>C_\text{ox}</math> = capacitance of the oxide layer. In a long-channel device, there is no drain voltage dependence of the current once <math>V_\text{DS} \gg V_\text{T}</math>, but as channel length is reduced [[drain-induced barrier lowering]] introduces drain voltage dependence that depends in a complex way upon the device geometry (for example, the channel doping, the junction doping and so on). Frequently, threshold voltage ''V''<sub>th</sub> for this mode is defined as the gate voltage at which a selected value of current ''I''<sub>D0</sub> occurs, for example, ''I''<sub>D0</sub> = 1&nbsp;μA, which may not be the same ''V''<sub>th</sub>-value used in the equations for the following modes.
+Some micropower analog circuits are designed to take advantage of subthreshold conduction.<ref name=Smith-Hamilton>{{ cite book | first1 = Leslie S.|last1=Smith |first2=Alister|last2=Hamilton | title=Neuromorphic Systems: Engineering Silicon from Neurobiology | year = 1998 | pages=52–56 | publisher=World Scientific | isbn = 978-981-02-3377-8 | url=https://books.google.com/books?id=kWSXEHyQL9sC&pg=PA55 }}</ref><ref name=Kumar>{{ cite book | first = Satish|last=Kumar | title = Neural Networks: A Classroom Approach | year = 2004 | page=688 | publisher=Tata McGraw-Hill | isbn = 978-0-07-048292-0 | url=https://books.google.com/books?id=GJQh-2p6TvgC&pg=PA688 }}</ref><ref name=Conference>{{ cite book | first1 = Manfred|last1=Glesner |first2=Peter|last2=Zipf |first3=Michel|last3=Renovell | title=Field-programmable Logic and Applications: 12th International Conference | year = 2002 | page= 425 | location=Dordrecht | publisher = Springer | isbn=978-3-540-44108-3 | url = https://books.google.com/books?id=fneXs6IY2-oC&pg=PA425}}</ref> By working in the weak-inversion region, the MOSFETs in these circuits deliver the highest possible transconductance-to-current ratio, namely: <math>g_m/I_\text{D} = 1/\left(nV_\text{T}\right)</math>, almost that of a bipolar transistor.<ref>{{ cite book | title = Circuits and systems tutorials | chapter = The Fundamentals of Analog Micropower Design | editor1-first = Chris|editor1-last=Toumazou |editor2-first=Nicholas C.|editor2-last=Battersby |editor3-first=Sonia|editor3-last=Porta | first= Eric A.|last=Vittoz | publisher = John Wiley and Sons | year = 1996 | isbn = 978-0-7803-1170-1 | pages = 365–72 | chapter-url = https://books.google.com/books?id=WTInL9njOKAC&pg=PA367 }}</ref>
+The subthreshold ''[[I–V curve]]'' depends exponentially upon threshold voltage, introducing a strong dependence on any manufacturing variation that affects threshold voltage; for example: variations in oxide thickness, junction depth, or body doping that change the degree of drain-induced barrier lowering. The resulting sensitivity to fabricational variations complicates optimization for leakage and performance.<ref name=Shukla>{{ cite book | first1 =Sandeep K.|last1=Shukla |first2=R. Iris|last2=Bahar | title=Nano, Quantum and Molecular Computing | year = 2004 | page=10 and Fig. 1.4, p. 11 | publisher = Springer | isbn=978-1-4020-8067-8 | url = https://books.google.com/books?id=lLvo1iMGhJgC&pg=PA10}}</ref><ref name=Srivasta>{{ cite book | first1 =Ashish|last1=Srivastava |first2=Dennis|last2=Sylvester |first3=David|last3=Blaauw | title=Statistical Analysis and Optimization For VLSI: Timing and Power | year = 2005 | page=135 | publisher=Springer | isbn = 978-0-387-25738-9 | url = https://books.google.com/books?id=WqsQTyOu5jwC&pg=PA9 }}</ref>
+; Triode mode or linear region, also known as the ohmic mode<ref name=Schneider>{{ cite book | first1 =C. |last1=Galup-Montoro  |first2=Schneider|last2=M.C. |name-list-style=amp | title=MOSFET modeling for circuit analysis and design | year = 2007 | page=83 | publisher=World Scientific | location = London/Singapore | isbn=978-981-256-810-6 | url = http://worldcat.org/isbn/981-256-810-7}}</ref><ref name=Malik>{{ cite book | first = Norbert R.|last= Malik | title = Electronic circuits: analysis, simulation, and design | year = 1995 | pages=315–16 | publisher=Prentice Hall | location = Englewood Cliffs, NJ | isbn=978-0-02-374910-0 | url = http://worldcat.org/isbn/0-02-374910-5 }}</ref> (n-channel MOSFET)
+When ''V''<sub>GS</sub> &gt; ''V''<sub>th</sub> and ''V''<sub>DS</sub> &lt; ''V''<sub>GS</sub>&nbsp;− ''V''<sub>th</sub>:
+The transistor is turned on, and a channel has been created which allows current between the drain and the source. The MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. The current from drain to source is modeled as:
+:<math>I_\text{D} = \mu_n C_\text{ox}\frac{W}{L} \left[ \left(V_\text{GS} - V_{\rm th}\right)V_\text{DS} - \frac{{V_\text{DS}}^2}{2} \right] (1 + \lambda V_{DS})</math>
+where <math>\mu_n</math> is the charge-carrier effective mobility, <math>W</math> is the gate width, <math>L</math> is the gate length and <math>C_\text{ox}</math> is the [[gate oxide]] capacitance per unit area. The transition from the exponential subthreshold region to the triode region is not as sharp as the equations suggest.
+; Saturation or active mode<ref name=Gray-Meyer2>{{ cite book |first1=P. R.|last1=Gray |first2=P. J.|last2= Hurst |first3=S. H.|last3= Lewis |first4=R. G.|last4= Meyer | title = §1.5.2 p. 45 | isbn=978-0-471-32168-2 | url = http://worldcat.org/isbn/0-471-32168-0|year=2001 }}</ref><ref name=Sedra>{{ cite book | first1 =A. S.|last1=Sedra  |first2=K. C.|last2=Smith |name-list-style=amp | title=Microelectronic circuits | year = 2004 | edition=Fifth | page=552 | publisher = Oxford | location=New York | isbn=978-0-19-514251-8 | url = http://worldcat.org/isbn/0-19-514251-9 }}</ref> (n-channel MOSFET)
+When ''V<sub>GS</sub> &gt; V''<sub>th</sub> and ''V<sub>DS</sub>'' ≥ (V''<sub>GS</sub>&nbsp;– V''<sub>th</sub>):
+The switch is turned on, and a channel has been created, which allows current between the drain and source. Since the drain voltage is higher than the source voltage, the electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. The onset of this region is also known as [[channel length modulation|pinch-off]] to indicate the lack of channel region near the drain. Although the channel does not extend the full length of the device, the electric field between the drain and the channel is very high, and conduction continues. The drain current is now weakly dependent upon drain voltage and controlled primarily by the gate–source voltage, and modeled approximately as:
+: <math>I_\text{D} = \frac{\mu_n C_\text{ox}}{2}\frac{W}{L}\left[V_\text{GS} - V_\text{th}\right]^2 \left[1 + \lambda (V_\text{DS} - V_\text{DSsat})\right].</math>
+The additional factor involving λ, the channel-length modulation parameter, models current dependence on drain voltage due to the [[channel length modulation]], effectively similar to the [[Early effect]] seen in bipolar devices. According to this equation, a key design parameter, the MOSFET transconductance is:
+: <math>g_m = \frac{\partial I_D}{\partial V_\text{GS}} = \frac{2I_\text{D}}{V_\text{GS} - V_\text{th}} = \frac{2I_\text{D}}{V_\text{ov}} , </math>
+where the combination ''V''<sub>ov</sub> = ''V''<sub>GS</sub>&nbsp;− ''V''<sub>th</sub> is called the [[overdrive voltage]],<ref name=Sedra2>{{cite book | first1 =A. S.|last1=Sedra  |first2=K.C.|last2=Smith  |name-list-style=amp | title=p. 250, Eq. 4.14 | isbn = 978-0-19-514251-8 | url=http://worldcat.org/isbn/0-19-514251-9|year=2004  }}</ref> and where ''V''<sub>DSsat</sub> = ''V''<sub>GS</sub>&nbsp;− ''V''<sub>th</sub> accounts for a small discontinuity in <math>I_\text{D}</math> which would otherwise appear at the transition between the triode and saturation regions.
+Another key design parameter is the MOSFET output resistance <math>r_{out} = \frac{\partial V_\text{DS}}{\partial I_\text{DS}}</math> given by:
+:<math>r_\text{out} \approx \frac{1}{\lambda I_\text{D}}</math>.
+''r''<sub>out</sub> is the inverse of ''g''<sub>DS</sub> where <math>g_\text{DS} = \frac{\partial I_\text{DS}}{\partial V_\text{DS}}</math>. ''I''<sub>D</sub> is the expression in saturation region.
+If λ is taken as zero, the resulting infinite output resistance can simplify circuit analysis, however this may lead to unrealistic circuit predictions, particularly in analog circuits.
+As the channel length becomes very short, these equations become quite inaccurate. New physical effects arise. For example, carrier transport in the active mode may become limited by [[velocity saturation]]. When velocity saturation dominates, the saturation drain current is more nearly linear than quadratic in ''V''<sub>GS</sub>. At even shorter lengths, carriers transport with near zero scattering, known as quasi-[[ballistic transport]]. In the ballistic regime, the carriers travel at an injection velocity that may exceed the saturation velocity and approaches the [[Fermi velocity]] at high inversion charge density. In addition, drain-induced barrier lowering increases off-state (cutoff) current and requires an increase in threshold voltage to compensate, which in turn reduces the saturation current.
 == Symbols ==
@@ Line 65: / Line 188: @@
 === Background ===
-{{Main|Field-effect transistor}}
+{{Main|field-effect transistor}}
 The basic principle of the [[field-effect transistor]] (FET) was first proposed by Austrian physicist [[Julius Edgar Lilienfeld]] in 1926, when he filed the first [[patent]] for an insulated-gate field-effect transistor.<ref name=p1>Lilienfeld, Julius Edgar (1926-10-08) "Method and apparatus for controlling electric currents" (US patent 1745175A)</ref> Over the course of next two years he described various FET structures. In his configuration, aluminum formed the metal and aluminum oxide the oxide, while [[copper sulfide]] was used as a [[semiconductor]]. However, he was unable to build a practical working device.<ref name="Deal">{{cite book |last1=Deal |first1=Bruce E. |chapter=Highlights Of Silicon Thermal Oxidation Technology |title=Silicon materials science and technology |date=1998 |publisher=[[The Electrochemical Society]] |isbn=978-1566771931 |page=183 |chapter-url=https://books.google.com/books?id=cr8FPGkiRS0C&pg=PA183}}</ref> The FET concept was later also theorized by German engineer [[Oskar Heil]] in the 1930s and American physicist [[William Shockley]] in the 1940s.<ref name="computerhistory"/> There was no working practical FET built at the time, and none of these early FET proposals involved [[thermal oxidation|thermally oxidized]] silicon.<ref name="Deal"/>
@@ Line 72: / Line 195: @@
 === Invention ===
+[[File:Atalla1963.png|thumb|[[Mohamed M. Atalla]] invented the [[MOSFET]] (MOS field-effect transistor) in 1959]]
 [[Mohamed M. Atalla]] at [[Bell Labs]] was dealing with the problem of surface states in the late 1950s. He attempted to [[Surface passivation|passivate the surface]] of [[silicon]] through the [[Thermal oxidation|formation of oxide layer]] over it. He thought that growing a very thin high quality thermally grown SiO<sub>2</sub> on top of a clean silicon wafer would neutralize surface states enough to make a practical working field-effect transistor. He wrote his findings in his BTL memos in 1957, before presenting his work at an [[Electrochemical Society]] meeting in 1958.<ref name="kahng">{{cite article |title=Dawon Kahng |url=https://www.invent.org/inductees/dawon-kahng |website=[[National Inventors Hall of Fame]] |access-date=27 June 2019}}</ref><ref name="atalla">{{cite article|title=Martin (John) M. Atalla|publisher=[[National Inventors Hall of Fame]]|year=2009|url=https://www.invent.org/inductees/martin-john-m-atalla|access-date=21 June 2013}}</ref><ref name="Lojek">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer Science & Business Media |isbn=978-3540342588 |pages=321–23}}</ref><ref name="Huff34">{{cite book |last1=Huff |first1=Howard |title=High Dielectric Constant Materials: VLSI MOSFET Applications |date=2005 |publisher=Springer Science & Business Media |isbn=978-3540210818 |page=34 |url=https://books.google.com/books?id=kaSmXepnqCMC&pg=PA34}}</ref><ref name="computerhistory">{{cite article|url=https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/|title=1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated|journal=The Silicon Engine: A Timeline of Semiconductors in Computers|publisher=[[Computer History Museum]] |access-date=August 31, 2019}}</ref> This was an important development that enabled MOS technology and silicon [[integrated circuit]] (IC) chips.<ref name="Sah"/>
@@ Line 102: / Line 226: @@
 The [[US Patent and Trademark Office]] calls the MOSFET a "groundbreaking invention that transformed life and culture around the world"<ref name="uspto"/> and the [[Computer History Museum]] credits it with "irrevocably changing the human experience."<ref name="triumph"/> The MOSFET was also the basis for [[Nobel Prize]] winning breakthroughs such as the [[quantum Hall effect]]<ref name="Lindley">{{cite article |last1=Lindley |first1=David |title=Focus: Landmarks&nbsp;– Accidental Discovery Leads to Calibration Standard |journal=[[Physics (magazine)|Physics]] |date=15 May 2015 |volume=8 |doi=10.1103/Physics.8.46 }}</ref> and the [[charge-coupled device]] (CCD),<ref name="Williams"/> though there was never any Nobel Prize given for the MOSFET itself.<ref>{{cite book |last1=Woodall |first1=Jerry M. |author1-link=Jerry Woodall |title=Fundamentals of III-V Semiconductor MOSFETs |date=2010 |publisher=Springer Science & Business Media |isbn=978-1441915474 |page=2 |url=https://books.google.com/books?id=sk2SrZH3xEcC&pg=PA2}}</ref> In a 2018 note on [[Jack Kilby]]'s [[Nobel Prize for Physics]] for his part in the invention of the integrated circuit, the [[Royal Swedish Academy of Sciences]] specifically mentioned the MOSFET and the microprocessor as other important inventions in the evolution of [[microelectronics]].<ref name="Nobel">{{cite article |title=Advanced information on the Nobel Prize in Physics 2000 |url=https://www.nobelprize.org/uploads/2018/06/advanced-physicsprize2000.pdf |website=[[Nobel Prize]] |date=June 2018 |access-date=17 August 2019}}</ref> The MOSFET is also included on the [[list of IEEE milestones]] in electronics,<ref>{{cite article |title=Milestones:List of IEEE Milestones |url=http://ethw.org/Milestones:List_of_IEEE_Milestones |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=25 July 2019}}</ref> and its inventors Mohamed Atalla and Dawon Kahng entered the [[National Inventors Hall of Fame]] in 2009.<ref name="kahng"/><ref name="atalla"/>
+== Types of MOSFET ==
+=== PMOS and NMOS logic ===
+{{Main|PMOS logic|NMOS logic}}
+{{see also|Depletion-load NMOS logic}}
+[[PMOS logic|P-channel MOS (PMOS) logic]] uses [[p-channel]] MOSFETs to implement [[logic gate]]s and other [[digital circuit]]s. [[NMOS logic|N-channel MOS (NMOS) logic]] uses [[n-channel]] MOSFETs to implement logic gates and other digital circuits.
+For devices of equal current driving capability, n-channel MOSFETs can be made smaller than p-channel MOSFETs, due to p-channel charge carriers ([[electron hole|holes]]) having lower [[electron mobility|mobility]] than do n-channel charge carriers ([[electrons]]), and producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler. These were the driving principles in the design of [[NMOS logic]] which uses n-channel MOSFETs exclusively. However, unlike CMOS logic (neglecting [[leakage current]]), NMOS logic consumes power even when no switching is taking place.
+[[Mohamed Atalla]] and [[Dawon Kahng]] originally demonstrated both pMOS and nMOS devices with [[20 µm process|20&nbsp;µm]] and then [[10 µm process|10&nbsp;µm]] gate lengths in 1960.<ref name="Lojek"/><ref>{{cite book |last1=Voinigescu |first1=Sorin |title=High-Frequency Integrated Circuits |date=2013 |publisher=Cambridge University Press|isbn=978-0521873024 |page=164 |url=https://books.google.com/books?id=71dHe1yb9jgC&pg=PA164}}</ref> Their original MOSFET devices also had a [[gate oxide]] thickness of [[100&nbsp;nm]].<ref>{{cite book |last1=Sze |first1=Simon M. |author1-link=Simon Sze |title=Semiconductor Devices: Physics and Technology |date=2002 |publisher=Wiley|isbn=0-471-33372-7 |page=4 |edition=2nd |url=http://www.fulviofrisone.com/attachments/article/453/Semiconductor.Devices_Physics.Technology_Sze.2ndEd_Wiley_2002.pdf}}</ref> However, the nMOS devices were impractical, and only the pMOS type were practical working devices.<ref name="Lojek"/> A more practical NMOS process was developed several years later. NMOS was initially faster than [[CMOS]], thus NMOS was more widely used for computers in the 1970s.<ref name="shmj727E">{{cite article |title=1978: Double-well fast CMOS SRAM (Hitachi) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |website=Semiconductor History Museum of Japan |access-date=5 July 2019 |archive-url=https://web.archive.org/web/20190705234921/http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |archive-date=5 July 2019 |url-status=dead }}</ref> With advances in technology, CMOS logic displaced NMOS logic in the mid-1980s to become the preferred process for digital chips.
+=== Complementary MOS (CMOS) ===
+{{Main|CMOS}}
+The MOSFET is used in digital [[complementary metal–oxide–semiconductor]] ([[CMOS]]) logic,<ref>{{cite article|url=http://www.computerhistory.org/semiconductor/timeline/1963-CMOS.html |title=Computer History Museum&nbsp;– The Silicon Engine &#124; 1963&nbsp;– Complementary MOS Circuit Configuration is Invented |publisher=Computerhistory.org |access-date=2012-06-02}}</ref> which uses p- and n-channel MOSFETs as building blocks. Overheating is a major concern in [[integrated circuit]]s since ever more transistors are packed into ever smaller chips. CMOS logic reduces power consumption because no current flows (ideally), and thus no [[Power (physics)|power]] is consumed, except when the inputs to [[logic gate]]s are being switched. CMOS accomplishes this current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct and a low voltage on the gates causes the reverse. During the switching time as the voltage goes from one state to another, both MOSFETs will conduct briefly. This arrangement greatly reduces power consumption and heat generation.
+CMOS was developed by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963.<ref name="computerhistory1963">{{cite article |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> CMOS had lower power consumption, but was initially slower than NMOS, which was more widely used for computers in the 1970s. In 1978, [[Hitachi]] introduced the twin-well CMOS process, which allowed CMOS to match the performance of NMOS with less power consumption. The twin-well CMOS process eventually overtook NMOS as the most common [[semiconductor manufacturing process]] for computers in the 1980s.<ref name="shmj727E" /> By the 1970s&ndash;1980s, CMOS logic consumed over {{#expr:110/15 round 0}}&nbsp;times less power than NMOS logic,<ref name="shmj727E" /> and about 100,000 times less power than bipolar [[transistor-transistor logic]] (TTL).<ref>{{cite book |last1=Higgins |first1=Richard J. |title=Electronics with digital and analog integrated circuits |date=1983 |publisher=Prentice-Hall |isbn=978-0132507042 |page=[https://archive.org/details/electronicswithd0000higg/page/101 101] |url=https://archive.org/details/electronicswithd0000higg |url-access=registration |quote=The dominant difference is power: CMOS gates can consume about 100,000 times less power than their TTL equivalents!}}</ref>
+=== Depletion-mode ===
+{{see also|Depletion and enhancement modes|Depletion-load NMOS logic}}
+There are ''depletion-mode'' MOSFET devices, which are less commonly used than the standard ''enhancement-mode'' devices already described. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to source. To control the channel, a negative voltage is applied to the gate (for an n-channel device), depleting the channel, which reduces the current flow through the device. In essence, the depletion-mode device is equivalent to a [[normally closed]] (on) switch, while the enhancement-mode device is equivalent to a [[normally open]] (off) switch.<ref>
+{{cite article
+ | title= Depletion Mode
+ | encyclopedia= Techweb
+ | date= 29 January 2010
+ | publisher= Techweb
+ | url=http://www.techweb.com/encyclopedia/imageFriendly.jhtml;?term=depletion+mode|access-date=27 November 2010
+}}</ref>
+Due to their low [[noise figure]] in the [[radio frequency|RF]] region, and better [[gain (electronics)#Power gain|gain]], these devices are often preferred to [[bipolar junction transistors|bipolars]] in [[RF front end|RF front-ends]] such as in [[television|TV]] sets.
+Depletion-mode MOSFET families include BF960 by [[Siemens]] and [[Telefunken]], and the BF980 in the 1980s by [[Philips]] (later to become [[NXP Semiconductors]]), whose derivatives are still used in [[automatic gain control|AGC]] and RF [[frequency mixer|mixer]] front-ends.
+=== Metal–insulator–semiconductor FET (MISFET) ===
+Metal–insulator–semiconductor field-effect-transistor,<ref>{{cite article
+ | url = http://www.semi1source.com/glossary/default.asp?searchterm=MIS
+ | title = MIS
+ | work = Semiconductor Glossary
+ | access-date = 2017-05-14
+ | archive-date = 2017-01-22
+ | archive-url = https://web.archive.org/web/20170122153452/http://www.semi1source.com/glossary/default.asp?searchterm=MIS
+ | url-status = dead
+ }}</ref><ref>
+{{cite book
+ | title = Semiconducting polymers: chemistry, physics and engineering
+ | first1= Georges | last1 = Hadziioannou
+ | first2=George G. | last2=Malliaras
+ | publisher = Wiley-VCH
+ | year = 2007
+ | isbn = 978-3-527-31271-9
+ | url = https://books.google.com/books?id=D37RykvobWwC&q=misfet+metal-insulator-semiconductor-field-effect-transistor&pg=PA532
+}}</ref><ref name=Jones>
+{{cite book
+ | title = Organic Molecular Solids: Properties and Applications
+ | first = William | last=Jones
+ | publisher = CRC Press
+ | year = 1997
+ | isbn = 978-0-8493-9428-7
+ | url = https://books.google.com/books?id=8sb1kwH6EgIC&q=misfet+metal-insulator-semiconductor-field-effect-transistor&pg=PA350
+}}</ref> or ''MISFET'', is a more general term than ''MOSFET'' and a synonym to ''insulated-gate field-effect transistor'' (IGFET). All MOSFETs are MISFETs, but not all MISFETs are MOSFETs.
+The gate dielectric insulator in a MISFET is [[silicon dioxide]] in a MOSFET, but other materials can also be employed. The [[gate dielectric]] lies directly below the [[gate electrode]] and above the [[channel (semiconductor)|channel]] of the MISFET. The term ''metal'' is historically used for the gate material, even though now it is usually [[doping (semiconductor)|highly doped]] [[polysilicon]] or some other [[non-metal]].
+Insulator types may be:
+* Silicon dioxide, in MOSFETs
+* Organic insulators (e.g., undoped trans-[[polyacetylene]]; cyanoethyl [[pullulan]], CEP<ref>
+{{cite article
+ |title=High performance organic field-effect transistors using cyanoethyl pullulan (CEP) high-k polymer cross-linked with trimethylolpropane triglycidyl ether (TTE) at low temperatures
+ | journal=Journal of Materials Chemistry C
+|volume=1
+ |issue=25
+ |pages=3955
+ |doi=10.1039/C3TC30134F
+ |year=2013
+ |last1=Xu
+ |first1=Wentao
+ |last2=Guo
+ |first2=Chang
+ |last3=Rhee
+ |first3=Shi-Woo
+ | url=http://oasis.postech.ac.kr/handle/2014.oak/10995
+}}</ref>), for organic-based FETs.<ref name=Jones/>
+=== Floating-gate MOSFET (FGMOS) ===
+{{Main|Floating-gate MOSFET}}
+The [[floating-gate MOSFET]] (FGMOS) is a type of MOSFET where the gate is electrically isolated, creating a floating node in DC and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. The first report of a [[floating-gate MOSFET]] (FGMOS) was made by [[Dawon Kahng]] (co-inventor of the original MOSFET) and [[Simon Min Sze]] in 1967.<ref>D. Kahng and S. M. Sze, "A floating-gate and its application to memory devices", ''The Bell System Technical Journal'', vol. 46, no. 4, 1967, pp. 1288–95</ref>
+The FGMOS is commonly used as a floating-gate [[memory cell (computing)|memory cell]], the digital storage element in [[EPROM]], [[EEPROM]] and [[Flash memory|flash memories]]. Other uses of the FGMOS include a neuronal computational element in [[neural network]]s, analog storage element, [[digital potentiometer]]s and single-transistor [[Digital-to-analog converter|DACs]].
+=== Power MOSFET ===
+{{Main|Power MOSFET}}
+{{see also|FET amplifier|Power electronics}}
+[[file:D2PAK.JPG|thumb|upright=1.2|Two [[power MOSFET]]s in [[D2PAK]] [[surface-mount technology|surface-mount]] packages. Operating as switches, each of these components can sustain a blocking voltage of 120&nbsp;[[volts|V]] in the ''off'' state, and can conduct a con&shy;ti&shy;nuous current of 30&nbsp;[[amperes|A]] in the ''on'' state, dissipating up to about 100&nbsp;[[watt|W]] and controlling a load of over 2000&nbsp;W. A [[matchstick]] is pictured for scale.]]
+[[Power MOSFET]]s have a different structure.<ref>{{cite book|title=Power Semiconductor Devices|first=B. Jayant|last=Baliga|publisher=PWS publishing Company|location=Boston|isbn=978-0-534-94098-0|year=1996}}</ref> As with most power devices, the structure is vertical and not planar. Using a vertical structure, it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the N-[[epitaxy|epitaxial]] layer (see cross section), while the current rating is a function of the channel width (the wider the channel, the higher the current). In a planar structure, the current and breakdown voltage ratings are both a function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the "silicon estate". With the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness (actually the N-epitaxial layer thickness) is proportional to the breakdown voltage.<ref>{{cite article|url=http://www.element-14.com/community/docs/DOC-18273/l/power-mosfet-basics-understanding-mosfet-characteristics-associated-with-the-figure-of-merit|title=Power MOSFET Basics: Understanding MOSFET Characteristics Associated With The Figure of Merit|website=element14|access-date=27 November 2010|archive-url=https://web.archive.org/web/20150405142659/http://www.element-14.com/community/docs/DOC-18273/l/power-mosfet-basics-understanding-mosfet-characteristics-associated-with-the-figure-of-merit |archive-date=5 April 2015 }}</ref>
+Power MOSFETs with lateral structure are mainly used in high-end audio amplifiers and high-power PA systems. Their advantage is a better behaviour in the saturated region (corresponding to the linear region of a [[bipolar transistor]]) than the vertical MOSFETs. Vertical MOSFETs are designed for switching applications.<ref>{{cite article|url=http://www.element-14.com/community/docs/DOC-18275/l/power-mosfet-basics-understanding-gate-charge-and-using-it-to-assess-switching-performance|title=Power MOSFET Basics: Understanding Gate Charge and Using It To Assess Switching Performance|website=element14|access-date=27 November 2010|archive-url=https://web.archive.org/web/20140630044120/http://www.element-14.com/community/docs/DOC-18275/l/power-mosfet-basics-understanding-gate-charge-and-using-it-to-assess-switching-performance |archive-date=30 June 2014 }}</ref>
+The power MOSFET, which is commonly used in [[power electronics]], was developed in the early 1970s.<ref>{{cite book |last1=Irwin |first1=J. David |title=The Industrial Electronics Handbook |date=1997 |publisher=[[CRC Press]] |isbn=978-0849383434 |page=218 |url=https://books.google.com/books?id=s0k9kGs5bHYC&pg=PA218}}</ref> The power MOSFET enables low gate drive power, fast switching speed, and advanced paralleling capability.<ref name="aosmd">{{cite article |title=Power MOSFET Basics |url=http://www.aosmd.com/res/application_notes/mosfets/Power_MOSFET_Basics.pdf |website=Alpha & Omega Semiconductor |access-date=29 July 2019 |quote=Power MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) are the most commonly used power devices due to their low gate drive power, fast switching speed and superior paralleling capability.}}</ref>
+=== Double-diffused MOS (DMOS) ===
+{{Main|Power MOSFET|LDMOS}}
+There are ''[[Power MOSFET|VDMOS]]'' (vertical double-diffused metal oxide semiconductor) and ''[[LDMOS]]'' (lateral double-diffused metal oxide semiconductor). Most power MOSFETs are made using this technology.
+=== MOS capacitor ===
+The MOS capacitor is part of the MOSFET structure, where the MOS capacitor is flanked by two [[p–n junction]]s.<ref name="Hu2009">{{cite article |last1=Hu |first1=Chenming |author1-link=Chenming Hu |title=MOS Capacitor |url=https://people.eecs.berkeley.edu/~hu/Chenming-Hu_ch5.pdf |website=[[UC Berkeley]] |date=February 13, 2009 |access-date=6 October 2019 |url-status=dead |archive-url=https://web.archive.org/web/20160615164507/http://people.eecs.berkeley.edu/~hu/Chenming-Hu_ch5.pdf |archive-date=2016-06-15}}</ref> The MOS capacitor is widely used as a storage capacitor in [[memory chip]]s, and as the basic building block of the [[charge-coupled device]] (CCD) in [[image sensor]] technology.<ref name="Sze2012">{{cite book |last1=Sze |first1=Simon Min |author1-link=Simon Sze |last2=Lee |first2=Ming-Kwei |chapter=MOS Capacitor and MOSFET |title=Semiconductor Devices: Physics and Technology |date=May 2012 |publisher=John Wiley & Sons |isbn=978-0470537947 |chapter-url=https://www.oreilly.com/library/view/semiconductor-devices-physics/9780470537947/13_chap05.html |access-date=6 October 2019}}</ref> In [[Dynamic random-access memory|DRAM]] (dynamic [[random-access memory]]), each [[memory cell (computing)|memory cell]] typically consists of a MOSFET and MOS capacitor.<ref>{{cite book |last1=Sze |first1=Simon M. |author1-link=Simon Sze |title=Semiconductor Devices: Physics and Technology |date=2002 |publisher=Wiley |isbn=0-471-33372-7 |page=214 |edition=2nd |url=http://www.fulviofrisone.com/attachments/article/453/Semiconductor.Devices_Physics.Technology_Sze.2ndEd_Wiley_2002.pdf}}</ref>
+=== Thin-film transistor (TFT) ===
+{{Main|Thin-film transistor}}
+The [[thin-film transistor]] (TFT) is a type of MOSFET distinct from the standard bulk MOSFET.<ref name="Kimizuka">{{cite book |last1=Kimizuka |first1=Noboru |last2=Yamazaki |first2=Shunpei |title=Physics and Technology of Crystalline Oxide Semiconductor CAAC-IGZO: Fundamentals |date=2016 |publisher=John Wiley & Sons |isbn=978-1119247401 |page=217 |url=https://books.google.com/books?id=_iTRDAAAQBAJ&pg=PA217}}</ref> The first TFT was invented by [[Paul K. Weimer]] at [[RCA]] in 1962, building on the earlier work of Atalla and Kahng on MOSFETs.<ref>{{cite article |last1=Weimer |first1=Paul K. |author1-link=Paul K. Weimer |title=The TFT A New Thin-Film Transistor |journal=[[Proceedings of the IRE]] |date=1962 |volume=50 |issue=6 |pages=1462–69 |doi=10.1109/JRPROC.1962.288190 |s2cid=51650159 |issn=0096-8390}}</ref>
+The idea of a TFT-based [[liquid-crystal display]] (LCD) was conceived by Bernard Lechner of [[RCA Laboratories]] in 1968.<ref name="Kawamoto">{{cite article |last1=Kawamoto |first1=H. |title=The Inventors of TFT Active-Matrix LCD Receive the 2011 IEEE Nishizawa Medal |journal=Journal of Display Technology |date=2012 |volume=8 |issue=1 |pages=3–4 |doi=10.1109/JDT.2011.2177740 |issn=1551-319X|bibcode=2012JDisT...8....3K }}</ref> Lechner, F. J. Marlowe, E. O. Nester and J. Tults demonstrated the concept in 1968 with an 18x2 matrix [[dynamic scattering]] LCD that used standard discrete MOSFETs, as TFT performance was not adequate at the time.<ref>{{cite book |last1=Castellano |first1=Joseph A. |title=Liquid Gold: The Story of Liquid Crystal Displays and the Creation of an Industry |date=2005 |publisher=[[World Scientific]] |isbn=978-9812389565 |pages=176–77 |url=https://books.google.com/books?id=vrtpDQAAQBAJ&pg=PA176}}</ref>
+=== Bipolar–MOS transistors ===
+{{Main|BiCMOS|Insulated-gate bipolar transistor}}
+[[BiCMOS]] is an [[integrated circuit]] that combines BJT and [[CMOS]] transistors on a single chip.<ref>{{cite book |last1=Alvarez |first1=Antonio R. |chapter=Introduction To BiCMOS |title=BiCMOS Technology and Applications |date=1990 |publisher=[[Springer Science & Business Media]] |doi=10.1007/978-1-4757-2029-7_1 |isbn=978-0792393849 |pages=1-20 (2)}}</ref>
+The [[insulated-gate bipolar transistor]] (IGBT) is a [[power transistor]] with characteristics of both a MOSFET and [[bipolar junction transistor]] (BJT).<ref>{{cite article |title=IGBT Definition |url=https://www.pcmag.com/encyclopedia/term/59900/igbt |website=PC Magazine Encyclopedia |publisher=[[PC Magazine]] |access-date=17 August 2019}}</ref>
+=== MOS sensors ===
+A number of MOSFET [[sensors]] have been developed, for measuring [[physics|physical]], [[chemistry|chemical]], [[biological]] and [[environmental]] parameters.<ref name="Bergveld">{{cite article |last1=Bergveld |first1=Piet |author1-link=Piet Bergveld |title=The impact of MOSFET-based sensors |journal=Sensors and Actuators |date=October 1985 |volume=8 |issue=2 |pages=109–27 |doi=10.1016/0250-6874(85)87009-8 |url=https://core.ac.uk/download/pdf/11473091.pdf |issn=0250-6874|bibcode=1985SeAc....8..109B }}</ref> The earliest MOSFET sensors include the open-gate FET (OGFET) introduced by Johannessen in 1970,<ref name="Bergveld"/> the [[ion-sensitive field-effect transistor]] (ISFET) invented by [[Piet Bergveld]] in 1970,<ref>{{cite article|author=Chris Toumazou |author2=Pantelis Georgiou |url=https://www.researchgate.net/publication/260616066 |title=40 years of ISFET technology:From neuronal sensing to DNA sequencing |journal=[[Electronics Letters]] |date=December 2011 |access-date=13 May 2016}}</ref> the [[adsorption]] FET (ADFET) [[patented]] by P.F. Cox in 1974, and a [[hydrogen]]-sensitive MOSFET demonstrated by I. Lundstrom, M.S. Shivaraman, C.S. Svenson and L. Lundkvist in 1975.<ref name="Bergveld"/> The ISFET is a special type of MOSFET with a gate at a certain distance,<ref name="Bergveld"/> and where the [[metal gate]] is replaced by an [[ion]]-sensitive [[membrane]], [[electrolyte]] solution and [[reference electrode]].<ref name="Schoning">{{cite article |last1=Schöning |first1=Michael J. |last2=Poghossian |first2=Arshak |title=Recent advances in biologically sensitive field-effect transistors (BioFETs) |journal=Analyst |date=10 September 2002 |volume=127 |issue=9 |pages=1137–51 |doi=10.1039/B204444G |pmid=12375833 |url=http://juser.fz-juelich.de/record/16078/files/12968.pdf |issn=1364-5528|bibcode=2002Ana...127.1137S }}</ref>
+By the mid-1980s, numerous other MOSFET sensors had been developed, including the [[gas sensor]] FET (GASFET), surface accessible FET (SAFET), charge flow transistor (CFT), [[pressure sensor]] FET (PRESSFET), [[chemical field-effect transistor]] (ChemFET), [[ISFET|reference ISFET]] (REFET), [[Bio-FET|biosensor FET]] (BioFET), [[Bio-FET|enzyme-modified FET]] (ENFET) and immunologically modified FET (IMFET).<ref name="Bergveld"/> By the early 2000s, BioFET types such as the [[DNA field-effect transistor]] (DNAFET), [[Genetically modified|gene-modified]] FET (GenFET) and [[Membrane potential|cell-potential]] BioFET (CPFET) had been developed.<ref name="Schoning"/>
+The two main types of [[image sensor]]s used in [[digital imaging]] technology are the [[charge-coupled device]] (CCD) and the [[active-pixel sensor]] (CMOS sensor). Both CCD and CMOS sensors are based on MOS technology, with the CCD based on MOS capacitors and the CMOS sensor based on MOS transistors.<ref name="Williams">{{cite book |last1=Williams |first1=J. B. |title=The Electronics Revolution: Inventing the Future |date=2017 |publisher=Springer |isbn=978-3319490885 |pages=245, 249–50 |url=https://books.google.com/books?id=v4QlDwAAQBAJ&pg=PA245}}</ref>
+=== Multi-gate MOSFET (MuGFET) ===
+{{Main|Multigate device}}
+{{see also|FinFET}}
+[[file:FINFET MOSFET.png|thumb|upright=1.2|A [[FinFET]] (fin field-effect transistor), a type of [[multi-gate MOSFET]].]]
+The [[dual-gate MOSFET]] (DGMOS) has a [[tetrode]] configuration, where both gates control the current in the device. It is commonly used for small-signal devices in radio frequency applications where biasing the drain-side gate at constant potential reduces the gain loss caused by [[Miller effect]], replacing two separate transistors in [[cascode]] configuration. Other common uses in RF circuits include gain control and mixing (frequency conversion). The ''tetrode'' description, though accurate, does not replicate the vacuum-tube tetrode. Vacuum-tube tetrodes, using a screen grid, exhibit much lower grid-plate capacitance and much higher output impedance and voltage gains than triode [[vacuum tubes]]. These improvements are commonly an order of magnitude (10 times) or considerably more. Tetrode transistors (whether bipolar junction or field-effect) do not exhibit improvements of such a great degree.
+The [[FinFET]] is a double-gate [[silicon on insulator|silicon-on-insulator]] device, one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering. The ''fin'' refers to the narrow channel between source and drain. A thin insulating oxide layer on either side of the fin separates it from the gate. SOI FinFETs with a thick oxide on top of the fin are called ''double-gate'' and those with a thin oxide on top as well as on the sides are called ''triple-gate'' FinFETs.<ref name=SOI>{{cite book |title=Frontiers in electronics: future chips : proceedings of the 2002 Workshop on Frontiers in Electronics (WOFE-02), St Croix, Virgin Islands, US, 6–11 January 2002 |year=2002|publisher=World Scientific |chapter=Figure 12: Simplified cross section of FinFET double-gate MOSFET.  |isbn=978-981-238-222-1|first1=P. M.|last1= Zeitzoff |first2=J. A.|last2= Hutchby |first3=H. R.|last3= Huff |editor1-first=Yoon-Soo|editor1-last=Park |editor2-first=Michael|editor2-last=Shur |editor3-first=William|editor3-last=Tang |chapter-url=https://books.google.com/books?id=uC6h4-OEWsMC&pg=PA82 |page=82}}</ref><ref>{{cite book |title=Silicon-on-Insulator Technology and Devices |chapter=Comparison of SOI FinFETs and bulk FinFETs: Figure 2 |first1=J.-H.|last1= Lee |first2=J.-W.|last2= Lee |first3=H.-A.-R.|last3= Jung |first4=B.-K.|last4= Choi |chapter-url=https://books.google.com/books?id=OVbb42PwZysC&pg=PA102 |page=102 |publisher=The Electrochemical Society |year=2009 |isbn=978-1-56677-712-4}}</ref>
+A [[double-gate]] MOSFET transistor was first demonstrated in 1984 by [[Electrotechnical Laboratory]] researchers Toshihiro Sekigawa and Yutaka Hayashi.<ref>{{cite book |last1=Colinge |first1=J.P. |title=FinFETs and Other Multi-Gate Transistors |date=2008 |publisher=Springer Science & Business Media |isbn=978-0387717517 |page=11 |url=https://books.google.com/books?id=t1ojkCdTGEEC&pg=PA11}}</ref><ref>{{cite article |last1=Sekigawa |first1=Toshihiro |last2=Hayashi |first2=Yutaka |title=Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate |journal=Solid-State Electronics |date=1 August 1984 |volume=27 |issue=8 |pages=827–28 |doi=10.1016/0038-1101(84)90036-4 |issn=0038-1101|bibcode=1984SSEle..27..827S }}</ref> A [[GAAFET]] (gate-all-around MOSFET), a type of [[Multigate device|multi-gate]] non-planar [[3D transistor]], was first demonstrated in 1988 by a [[Toshiba]] research team including [[Fujio Masuoka]], H. Takato and K. Sunouchi.<ref>{{cite article |last1=Masuoka |first1=Fujio |author1-link=Fujio Masuoka |last2=Takato |first2=H. |last3=Sunouchi |first3=K. |last4=Okabe |first4=N. |last5=Nitayama |first5=A. |last6=Hieda |first6=K. |last7=Horiguchi |first7=F. |title=High performance CMOS surrounding-gate transistor (SGT) for ultra high density LSIs |journal=Technical Digest., International Electron Devices Meeting |date=December 1988 |pages=222–25 |doi=10.1109/IEDM.1988.32796|s2cid=114148274 }}</ref><ref>{{cite book |last1=Brozek |first1=Tomasz |title=Micro- and Nanoelectronics: Emerging Device Challenges and Solutions |date=2017 |publisher=CRC Press |isbn=978-1351831345 |page=117 |url=https://books.google.com/books?id=dAhEDwAAQBAJ&pg=PA117}}</ref> The [[FinFET]] (fin field-effect transistor), a type of 3D non-planar double-gate MOSFET, originated from the research of Digh Hisamoto and his team at [[Hitachi|Hitachi Central Research Laboratory]] in 1989.<ref>{{cite article |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |website=[[IEEE Andrew S. Grove Award]] |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=4 July 2019}}</ref><ref>{{cite article |title=The Breakthrough Advantage for FPGAs with Tri-Gate Technology |url=https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01201-fpga-tri-gate-technology.pdf |publisher=[[Intel]] |year=2014 |access-date=4 July 2019 |archive-date=17 October 2019 |archive-url=https://web.archive.org/web/20191017033141/https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01201-fpga-tri-gate-technology.pdf |url-status=dead }}</ref> The development of [[nanowire]] multi-gate MOSFETs have since become fundamental to [[nanoelectronics]].<ref name="Liu"/>
+===Quantum field-effect transistor (QFET)===
+{{Main|QFET}}
+A [[QFET|quantum field-effect transistor]] (QFET) or [[quantum well]] field-effect transistor (QWFET) is a type of MOSFET<ref>{{cite article |last1=Datta |first1=Kanak |last2=Khosru |first2=Quazi D. M. |title=III–V tri-gate quantum well MOSFET: Quantum ballistic simulation study for 10nm technology and beyond |journal=Solid-State Electronics |volume=118 |pages=66–77 |doi=10.1016/j.sse.2015.11.034 |issn=0038-1101|bibcode=2016SSEle.118...66D |arxiv=1802.09136 |year=2018 |s2cid=101934219 }}</ref><ref>{{cite book |last1=Kulkarni |first1=Jaydeep P. |last2=Roy |first2=Kaushik |chapter=Technology/Circuit Co-Design for III-V FETs |editor-last1=Oktyabrsky |editor-first1=Serge |editor-last2=Ye |editor-first2=Peide |title=Fundamentals of III-V Semiconductor MOSFETs |date=2010 |publisher=[[Springer Science & Business Media]] |isbn=978-1-4419-1547-4 |doi=10.1007/978-1-4419-1547-4_14|pages=423–42 |chapter-url=https://books.google.com/books?id=sk2SrZH3xEcC&pg=PA423}}</ref><ref>{{cite article |last1=Lin |first1=Jianqiang |title=InGaAs Quantum-Well MOSFETs for logic applications |date=2015 |publisher=[[Massachusetts Institute of Technology]] |hdl=1721.1/99777 |type=Thesis }}</ref> that takes advantage of [[quantum tunneling]] to greatly increase the speed of transistor operation.<ref>{{cite article | title = WHAT'S NEWS: A review of the latest happenings in electronics | newspaper =[[Radio-Electronics]] | publisher=Gernsback | volume=62 |issue=5 | date =May 1991 | url =https://archive.org/stream/radio_electronics_1991-05/Radio_Electronics_May_1991_djvu.txt }}</ref>
+=== Radiation-hardened-by-design (RHBD) ===
+Semiconductor sub-micrometer and nanometer electronic circuits are the primary concern for operating within the normal tolerance in harsh [[radiation]] environments like [[outer space]]. One of the design approaches for making a [[radiation hardening|radiation-hardened-by-design]] (RHBD) device is enclosed-layout-transistor (ELT). Normally, the gate of the MOSFET surrounds the drain, which is placed in the center of the ELT. The source of the MOSFET surrounds the gate. Another RHBD MOSFET is called H-Gate. Both of these transistors have very low leakage current with respect to radiation. However, they are large in size and take more space on silicon than a standard MOSFET. In older STI (shallow trench isolation) designs, radiation strikes near the silicon oxide region cause the channel inversion at the corners of the standard MOSFET due to accumulation of radiation induced trapped charges. If the charges are large enough, the accumulated charges affect STI surface edges along the channel near the channel interface (gate) of the standard MOSFET. Thus the device channel inversion occurs along the channel edges and the device creates an off-state leakage path, causing the device to turn on. So the reliability of circuits degrades severely. The ELT offers many advantages. These advantages include improvement of [[reliability (semiconductor)|reliability]] by reducing unwanted surface inversion at the gate edges that occurs in the standard MOSFET. Since the gate edges are enclosed in ELT, there is no gate oxide edge (STI at gate interface), and thus the transistor off-state leakage is reduced considerably. Low-power microelectronic circuits including computers, communication devices and monitoring systems in the space shuttle and satellites are very different to what is used on earth. They require radiation (high-speed atomic particles like [[proton]] and [[neutron]], [[solar flare]] magnetic energy dissipation in Earth's space, energetic [[cosmic rays]] like [[X-ray]], [[gamma ray]] etc.) tolerant circuits. These special electronics are designed by applying different techniques using RHBD MOSFETs to ensure safer journeys and space-walks for astronauts.
+== Applications ==
+{{Main|MOS revolution}}
+The MOSFET generally forms the basis of modern [[electronics]],<ref name="McCluskey"/> as the dominant transistor in [[digital circuits]] as well as [[analog integrated circuit]]s.<ref name="Ashley"/> It is the basis for numerous modern technologies,<ref name="Colinge2005"/> and is commonly used for a wide range of applications.<ref name="Sridharan"/> According to Jean-Pierre Colinge, numerous modern technologies would not exist without the MOSFET, such as the modern [[computer industry]], [[digital telecommunication]] systems, [[video games]], [[pocket calculators]], and [[digital wristwatch]]es, for example.<ref name="Colinge2005">{{cite book |last1=Colinge |first1=Jean-Pierre |last2=Colinge |first2=C. A. |title=Physics of Semiconductor Devices |date=2005 |publisher=Springer Science & Business Media |isbn=978-0387285238 |page=165 |url=https://books.google.com/books?id=-o5bAG5pR3AC&pg=PA165 |quote=Without the MOSFET there would be no computer industry, no digital telecommunication systems, no video games, no pocket calculators and no digital wristwatches.}}</ref>
+Discrete MOSFET devices are widely used in applications such as [[switch mode power supply|switch mode power supplies]], [[variable-frequency drive]]s and other [[power electronics]] applications where each device may be switching thousands of watts. Radio-frequency amplifiers up to the [[UHF]] spectrum use MOSFET transistors as analog signal and power amplifiers. Radio systems also use MOSFETs as oscillators, or [[frequency mixer|mixers]] to convert frequencies. MOSFET devices are also applied in audio-frequency power amplifiers for public address systems, [[sound reinforcement]] and home and automobile sound systems.
+MOSFETs in [[integrated circuits]] are the primary elements of [[computer processor]]s, [[semiconductor memory]], [[image sensors]], and most other types of integrated circuits.
+=== MOS integrated circuit (MOS IC) ===
+{{see also|Integrated circuit|Invention of the integrated circuit|Three-dimensional integrated circuit}}
+The MOSFET is the most widely used type of transistor and the most critical device component in [[integrated circuit]] (IC) chips.<ref name="Kuo"/> The [[monolithic integrated circuit]] chip was enabled by the [[surface passivation]] process, which electrically stabilized [[silicon]] surfaces via [[thermal oxidation]], making it possible to [[semiconductor device fabrication|fabricate]] monolithic integrated circuit chips using silicon. The surface passivation process was developed by [[Mohamed M. Atalla]] at [[Bell Labs]] in 1957. This was the basis for the [[planar process]], developed by [[Jean Hoerni]] at [[Fairchild Semiconductor]] in early 1959, which was critical to the invention of the monolithic integrated circuit chip by [[Robert Noyce]] later in 1959.<ref>{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer Science & Business Media|isbn=978-3540342588 |pages=120, 321–23}}</ref><ref name="Bassett46">{{cite book |last1=Bassett |first1=Ross Knox |title=To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology |date=2007 |publisher=Johns Hopkins University Press |isbn=978-0801886393 |page=46 |url=https://books.google.com/books?id=UUbB3d2UnaAC&pg=PA46}}</ref><ref name="Sah">{{cite article |last=Sah |first=Chih-Tang |author-link=Chih-Tang Sah |title=Evolution of the MOS transistor-from conception to VLSI |journal=[[Proceedings of the IEEE]] |date=October 1988 |volume=76 |issue=10 |pages=1280–1326 [1290] |doi=10.1109/5.16328 |url=http://www.dejazzer.com/ece723/resources/Evolution_of_the_MOS_transistor.pdf |issn=0018-9219 |quote=Those of us active in silicon material and device research during 1956{{ndash}}1960 considered this successful effort by the Bell Labs group led by Atalla to stabilize the silicon surface the most important and significant technology advance, which blazed the trail that led to silicon integrated circuit technology developments in the second phase and volume production in the third phase.|bibcode=1988IEEEP..76.1280S }}</ref> The same year,<ref name="computerhistory"/> Atalla used his surface passivation process to invent the MOSFET with [[Dawon Kahng]] at Bell Labs.<ref name="atalla"/><ref name="kahng"/> This was followed by the development of [[clean room]]s to reduce contamination to levels never before thought necessary, and coincided with the development of [[photolithography]]<ref>{{cite article | url = http://www.computerhistory.org/semiconductor/timeline/1955-Photolithography.html  | title = Computer History Museum&nbsp;– The Silicon Engine &#124; 1955&nbsp;– Photolithography Techniques Are Used to Make Silicon Devices | publisher = Computerhistory.org | access-date = 2012-06-02 }}</ref> which, along with surface passivation and the planar process, allowed circuits to be made in few steps.
+Mohamed Atalla first proposed the concept of the MOS integrated circuit (MOS IC) chip in 1960, noting that the MOSFET's ease of [[Semiconductor device fabrication|fabrication]] made it useful for integrated circuits.<ref name="Moskowitz"/> In contrast to [[bipolar transistors]] which required a number of steps for the [[p–n junction isolation]] of transistors on a chip, MOSFETs required no such steps but could be easily isolated from each other.<ref name="Bassett53"/> Its advantage for integrated circuits was re-iterated by Dawon Kahng in 1961.<ref name="Bassett22"/> The [[Silicon|Si]]–[[Silicon dioxide|SiO<sub>2</sub>]] system possessed the technical attractions of low cost of production (on a per circuit basis) and ease of integration. These two factors, along with its [[#Scaling|rapidly scaling]] miniaturization and low [[energy consumption]], led to the MOSFET becoming the most widely used type of transistor in IC chips.
+The earliest experimental MOS IC to be demonstrated was a 16-transistor chip built by Fred Heiman and Steven Hofstein at [[RCA]] in 1962.<ref name="computerhistory-digital">{{cite article |title=Tortoise of Transistors Wins the Race – CHM Revolution |url=https://www.computerhistory.org/revolution/digital-logic/12/279 |website=[[Computer History Museum]] |access-date=22 July 2019}}</ref> [[General Microelectronics]] later introduced the first commercial MOS integrated circuits in 1964, consisting of 120 [[p-channel]] transistors.<ref>{{cite article|url=http://www.computerhistory.org/semiconductor/timeline/1964-Commecial.html|title=1964 – First Commercial MOS IC Introduced|website=[[Computer History Museum]]}}</ref> It was a 20-bit [[shift register]], developed by Robert Norman<ref name="computerhistory-digital"/> and [[Frank Wanlass]].<ref>{{cite article |last1=Kilby |first1=J. S. |title=Miniaturized electronic circuits [US Patent No. 3,138, 743] |journal=IEEE Solid-State Circuits Society Newsletter |date=2007 |volume=12 |issue=2 |pages=44–54 |doi=10.1109/N-SSC.2007.4785580 |url=https://www.researchgate.net/publication/245509003 |issn=1098-4232}}</ref> In 1968, [[Fairchild Semiconductor]] researchers [[Federico Faggin]] and Tom Klein developed the first [[silicon-gate]] MOS IC.<ref name="computerhistory1968"/>
+==== MOS large-scale integration (MOS LSI) ====
+{{see also|Large-scale integration|Very large-scale integration}}
+With its [[#Scaling|high scalability]],<ref name="Motoyoshi">{{cite article |last1=Motoyoshi |first1=M. |title=Through-Silicon Via (TSV) |journal=Proceedings of the IEEE |date=2009 |volume=97 |issue=1 |pages=43–48 |doi=10.1109/JPROC.2008.2007462 |s2cid=29105721 |url=https://pdfs.semanticscholar.org/8a44/93b535463daa7d7317b08d8900a33b8cbaf4.pdf |archive-url=https://web.archive.org/web/20190719120523/https://pdfs.semanticscholar.org/8a44/93b535463daa7d7317b08d8900a33b8cbaf4.pdf |url-status=dead |archive-date=2019-07-19 |issn=0018-9219}}</ref> and much lower power consumption and higher density than bipolar junction transistors,<ref name="Moore">{{cite article |title=Transistors Keep Moore's Law Alive |url=https://www.eetimes.com/author.asp?section_id=36&doc_id=1334068 |access-date=18 July 2019 |work=[[EETimes]] |date=12 December 2018}}</ref> the MOSFET made it possible to build [[Large scale integration|high-density]] IC chips.<ref name="computerhistory-transistor">{{cite article |title=Who Invented the Transistor? |url=https://www.computerhistory.org/atchm/who-invented-the-transistor/ |website=[[Computer History Museum]] |date=4 December 2013 |access-date=20 July 2019}}</ref> By 1964, MOS chips had reached higher [[transistor density]] and lower manufacturing costs than [[bipolar junction transistor|bipolar]] chips. MOS chips further increased in complexity at a rate predicted by [[Moore's law]], leading to [[large-scale integration]] (LSI) with hundreds of MOSFETs on a chip by the late 1960s.<ref name="ieee">{{cite article |last1=Shirriff |first1=Ken |title=The Surprising Story of the First Microprocessors |journal=[[IEEE Spectrum]] |volume=53 |issue=9 |pages=48–54 |date=30 August 2016 |publisher=[[Institute of Electrical and Electronics Engineers]] |url=https://spectrum.ieee.org/tech-history/silicon-revolution/the-surprising-story-of-the-first-microprocessors |access-date=13 October 2019|doi=10.1109/MSPEC.2016.7551353 |s2cid=32003640 }}</ref> MOS technology enabled the integration of more than 10,000 transistors on a single LSI chip by the early 1970s,<ref name="Hittinger">{{cite article |last1=Hittinger |first1=William C. |title=Metal–Oxide–Semiconductor Technology |journal=Scientific American |date=1973 |volume=229 |issue=2 |pages=48–59 |issn=0036-8733|jstor=24923169 |doi=10.1038/scientificamerican0873-48 |bibcode=1973SciAm.229b..48H }}</ref> before later enabling [[very large-scale integration]] (VLSI).<ref name="Britannica"/><ref name="Grant1"/>
+==== Microprocessors ====
+{{see also|Microcontroller|Microprocessor chronology}}
+The MOSFET was responsible for the invention of the microprocessor.<ref>{{cite book |last1=Schwarz |first1=A. F. |title=Handbook of VLSI Chip Design and Expert Systems |date=2014 |publisher=[[Academic Press]] |isbn=978-1483258058 |page=16 |url=https://books.google.com/books?id=LqOjBQAAQBAJ&pg=PA16}}</ref> The origins of both the microprocessor and the [[microcontroller]] can be traced back to the invention and development of MOS technology. The application of MOS LSI chips to [[computing]] was the basis for the first microprocessors, as engineers began recognizing that a complete [[computer processor]] could be contained on a single MOS LSI chip.<ref name="ieee"/>
+The [[microprocessor chronology|earliest microprocessors]] were all MOS chips, built with MOS LSI circuits. The first multi-chip microprocessors, the [[Four-Phase Systems AL1]] in 1969 and the [[Garrett AiResearch]] [[MP944]] in 1970, were developed with multiple MOS LSI chips. The first commercial single-chip microprocessor, the [[Intel 4004]], was developed by [[Federico Faggin]], using his silicon-gate MOS IC technology, with [[Intel]] engineers [[Marcian Hoff]] and [[Stan Mazor]], and [[Busicom]] engineer [[Masatoshi Shima]].<ref>{{cite article |title=1971: Microprocessor Integrates CPU Function onto a Single Chip |website=The Silicon Engine |url=https://www.computerhistory.org/siliconengine/microprocessor-integrates-cpu-function-onto-a-single-chip/ |publisher=[[Computer History Museum]] |access-date=22 July 2019}}</ref> With the arrival of [[CMOS]] microprocessors in 1975, the term "MOS microprocessors" began to refer to chips fabricated entirely from [[PMOS logic]] or fabricated entirely from [[NMOS logic]], contrasted with "CMOS microprocessors" and "bipolar [[bit-slice]] processors".<ref name="cushman">{{cite article|first=Robert H.|last=Cushman|url=http://www.swtpc.com/mholley/Microprocessors/EDN_Sep_20_1975_6502.pdf|title=2-1/2-generation μP's-$10 parts that perform like low-end mini's|publisher=EDN|date=20 September 1975|access-date=8 August 2013|archive-url=https://web.archive.org/web/20160424050556/http://www.swtpc.com/mholley/Microprocessors/EDN_Sep_20_1975_6502.pdf|archive-date=24 April 2016|url-status=dead}}</ref>
+=== CMOS circuits ===
+{{Main|CMOS}}
+==== Digital ====
+The growth of digital technologies like the [[microprocessor]] has provided the motivation to advance MOSFET technology faster than any other type of silicon-based transistor.<ref>{{cite article|url=http://www.computerhistory.org/microprocessors/ |title=Computer History Museum&nbsp;– Exhibits&nbsp;– Microprocessors |publisher=Computerhistory.org |access-date=2012-06-02}}</ref> A big advantage of MOSFETs for digital switching is that the oxide layer between the gate and the channel prevents DC current from flowing through the gate, further reducing power consumption and giving a very large input impedance. The insulating oxide between the gate and channel effectively isolates a MOSFET in one logic stage from earlier and later stages, which allows a single output to drive a much larger number of inputs (the [[fan-out]] capacity) than BJT-based logic (such as [[transistor-transistor logic|TTL]]). This isolation also helps designers ignore loading effects between logic stages, to an extent dependent on the operating frequency: as frequencies increase, the input impedance of the MOSFETs decreases.
+==== Analog ====
+{{further|CMOS amplifier|RF CMOS|Mixed-signal integrated circuit}}
+The MOSFET's advantages in digital circuits do not translate into supremacy in all [[analog circuit]]s. The two types of circuit draw upon different features of transistor behavior. Digital circuits switch, spending most of their time either fully on or fully off. The transition from one to the other is only of concern with regards to speed and charge required. Analog circuits depend on operation in the transition region where small changes to ''V''<sub>gs</sub> can modulate the output (drain) current. The JFET and [[bipolar junction transistor]] (BJT) are preferred for accurate matching (of adjacent devices in integrated circuits), higher [[transconductance]] and certain temperature characteristics which simplify keeping performance predictable as circuit temperature varies.
+Nevertheless, MOSFETs are widely used in many types of analog circuits because of their own advantages (zero gate current, high and adjustable output impedance and improved robustness vs. BJTs which can be permanently degraded by even lightly breaking down the emitter-base). The characteristics and performance of many analog circuits can be scaled up or down by changing the sizes (length and width) of the MOSFETs used. By comparison, in bipolar transistors the size of the device does not significantly affect its performance. MOSFETs' ideal characteristics regarding gate current (zero) and drain-source offset voltage (zero) also make them nearly ideal switch elements, and also make [[switched capacitor]] analog circuits practical. In their linear region, MOSFETs can be used as precision resistors, which can have a much higher controlled resistance than BJTs. In high power circuits, MOSFETs sometimes have the advantage of not suffering from [[thermal runaway]] as BJTs do. Also, MOSFETs can be configured to perform as capacitors and [[gyrator|gyrator circuits]] which allow op-amps made from them to appear as inductors, thereby allowing all of the normal analog devices on a chip (except for diodes, which can be made smaller than a MOSFET anyway) to be built entirely out of MOSFETs. This means that complete analog circuits can be made on a silicon chip in a much smaller space and with simpler fabrication techniques. MOSFETS are ideally suited to switch inductive loads because of tolerance to inductive kickback.
+Some ICs combine analog and digital MOSFET circuitry on a single [[mixed-signal integrated circuit]], making the needed board space even smaller. This creates a need to isolate the analog circuits from the digital circuits on a chip level, leading to the use of isolation rings and [[silicon on insulator]] (SOI). Since MOSFETs require more space to handle a given amount of power than a BJT, fabrication processes can incorporate BJTs and MOSFETs into a single device. Mixed-transistor devices are called bi-FETs (bipolar FETs) if they contain just one BJT-FET and [[BiCMOS]] (bipolar-CMOS) if they contain complementary BJT-FETs. Such devices have the advantages of both insulated gates and higher current density.
+In the late 1980s, [[Asad Abidi]] pioneered [[RF CMOS]] technology, which uses MOS [[VLSI]] circuits, while working at [[UCLA]]. This changed the way in which [[RF circuit]]s were designed, away from discrete bipolar transistors and towards CMOS integrated circuits. As of 2008, the [[radio transceiver]]s in all [[wireless networking]] devices and modern [[mobile phones]] are mass-produced as RF CMOS devices. RF CMOS is also used in nearly all modern [[Bluetooth]] and [[wireless LAN]] (WLAN) devices.<ref name="O'Neill">{{cite article |last1=O'Neill |first1=A. |title=Asad Abidi Recognized for Work in RF-CMOS |journal=IEEE Solid-State Circuits Society Newsletter |date=2008 |volume=13 |issue=1 |pages=57–58 |doi=10.1109/N-SSC.2008.4785694 |issn=1098-4232}}</ref>
+=== MOS memory ===
+{{Main|MOS memory}}
+{{further|Computer memory|Memory cell (computing)}}
+The advent of the MOSFET enabled the practical use of MOS transistors as [[memory cell (computing)|memory cell]] storage elements, a function previously served by [[magnetic-core memory|magnetic cores]] in [[computer memory]].<ref name="ScienceDirect-Transistors">{{cite article |title=Transistors – an overview |url=https://www.sciencedirect.com/topics/computer-science/transistors |website=[[ScienceDirect]] |access-date=8 August 2019}}</ref> The first modern computer memory was introduced in 1965, when John Schmidt at [[Fairchild Semiconductor]] designed the first MOS [[semiconductor memory]], a [[64-bit]] MOS [[Static random-access memory|SRAM]] (static [[random-access memory]]).<ref name="Horizon">{{cite book|url=https://books.google.com/books?id=kG4rAQAAIAAJ&q=John+Schmidt|title=Solid State Design – Vol. 6|date=1965|publisher=Horizon House}}</ref> SRAM became an alternative to [[magnetic-core memory]], but required six MOS transistors for each [[bit]] of data.<ref name="ibm100">{{cite article |title=DRAM |url=https://www.ibm.com/ibm/history/ibm100/us/en/icons/dram/ |website=IBM100 |publisher=[[IBM]] |access-date=20 September 2019 |date=9 August 2017}}</ref>
+MOS technology is the basis for [[DRAM]] (dynamic [[random-access memory]]). In 1966, Dr. [[Robert H. Dennard]] at the [[IBM]] [[Thomas J. Watson Research Center]] was working on [[MOS memory]]. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.<ref name="ibm100"/> In 1967, Dennard filed a patent under IBM for a single-transistor DRAM (dynamic random-access memory) memory cell, based on MOS technology.<ref name="Dennard">{{cite article |title=Robert Dennard |url=https://www.britannica.com/biography/Robert-Dennard |website=[[Encyclopedia Britannica]] |access-date=8 July 2019}}</ref> MOS memory enabled higher performance, was cheaper, and consumed less power, than [[magnetic-core memory]], leading to MOS memory overtaking magnetic core memory as the dominant [[computer memory]] technology by the early 1970s.<ref name="computerhistory1970">{{cite article |title=1970: MOS Dynamic RAM Competes with Magnetic Core Memory on Price |url=https://www.computerhistory.org/siliconengine/mos-dynamic-ram-competes-with-magnetic-core-memory-on-price/ |website=[[Computer History Museum]] |access-date=29 July 2019}}</ref>
+[[Frank Wanlass]], while studying MOSFET structures in 1963, noted the movement of charge through [[Gate oxide|oxide]] onto a [[Metal gate|gate]]. While he did not pursue it, this idea would later become the basis for [[EPROM]] (erasable [[programmable read-only memory]]) technology.<ref>{{cite article |title=People |url=https://www.computerhistory.org/siliconengine/people/ |website=The Silicon Engine |publisher=[[Computer History Museum]] |access-date=17 August 2019}}</ref> In 1967, [[Dawon Kahng]] and [[Simon Min Sze]] proposed that [[floating-gate]] memory cells, consisting of [[floating-gate MOSFET]]s (FGMOS), could be used to produce [[EPROM|reprogrammable ROM]] ([[read-only memory]]).<ref name="computerhistory1971">{{cite article |title=1971: Reusable semiconductor ROM introduced |url=https://www.computerhistory.org/storageengine/reusable-semiconductor-rom-introduced/ |website=[[Computer History Museum]] |access-date=19 June 2019}}</ref> Floating-gate memory cells later became the basis for [[non-volatile memory]] (NVM) technologies including EPROM, [[EEPROM]] (electrically erasable programmable ROM) and [[flash memory]].<ref name="Bez">{{cite book |last1=Bez |first1=R. |last2=Pirovano |first2=A. |title=Advances in Non-Volatile Memory and Storage Technology |date=2019 |publisher=[[Woodhead Publishing]] |isbn=978-0081025857}}</ref>
+===Consumer electronics===
+MOSFETs are widely used in [[consumer electronics]]. One of the earliest influential consumer electronic products enabled by MOS LSI circuits was the electronic [[pocket calculator]],<ref name="Hittinger"/> as MOS LSI technology enabled large amounts of [[computational]] capability in small packages.<ref name="Cherry1973">{{cite article|last1=Cherry|first1=Robert William|date=June 1973|title=A calculator option for the Tektronix 4010 computer graphics terminal|url=https://calhoun.nps.edu/handle/10945/16514|journal=Compilation of Abstracts of Dissertations, Theses and Research Papers Submitted by Candidates for Degrees|publisher=[[Naval Postgraduate School]]|hdl=10945/16514|type=Thesis|hdl-access=free}}</ref> In 1965, the [[Victor Technology|Victor]] 3900 [[desktop calculator]] was the first MOS [[calculator]], with 29 MOS chips.<ref>{{cite article |title=Victor 3900 |url=http://www.vintagecalculators.com/html/victor_3900.html |website=Vintage Calculators Web Museum |access-date=15 May 2020}}</ref> In 1967, the [[Texas Instruments]] Cal-Tech was the first prototype electronic [[handheld calculator]], with three MOS LSI chips, and it was later released as the [[Canon Inc.|Canon]] Pocketronic in 1970.<ref name="hand-held">{{cite article |title=Hand-held Calculators |url=http://www.vintagecalculators.com/html/hand-held_calculators.html |website=Vintage Calculators Web Museum |access-date=22 July 2019}}</ref> The [[Sharp QT-8D]] desktop calculator was the first mass-produced LSI MOS calculator in 1969,<ref name="vintage">{{cite article |author=Nigel Tout |url=http://www.vintagecalculators.com/html/sharp_qt-8d.html |title=Sharp ''QT-8D "micro Compet"'' |work=Vintage Calculators Web Museum |access-date=September 29, 2010}}</ref> and the [[Sharp EL-8]] which used four MOS LSI chips was the first commercial electronic handheld calculator in 1970.<ref name="hand-held"/> The first true electronic pocket calculator was the [[Busicom]] LE-120A HANDY LE, which used a single MOS LSI [[System on a chip|calculator-on-a-chip]] from [[Mostek]], and was released in 1971.<ref name="hand-held"/> By 1972, MOS LSI circuits were commercialized for numerous other applications.<ref name="Design">{{cite article|date=1972|title=Design News|url=https://books.google.com/books?id=s5w-AQAAIAAJ|journal=[[Design News]]|publisher=Cahners Publishing Company|volume=27|issue=1–8|page=275|quote=Today, under contracts with some 20 major companies, we're working on nearly 30 product programs&nbsp;– applications of MOS/LSI technology for automobiles, trucks, appliances, business machines, musical instruments, computer peripherals, cash registers, calculators, data transmission and telecommunication equipment.}}</ref>
+MOSFETs are fundamental to [[information and communications technology]] (ICT),<ref name="uspto"/><ref name="Nobel"/> including modern [[computers]],<ref name="Omura53">{{cite book |last1=Omura |first1=Yasuhisa |last2=Mallik |first2=Abhijit |last3=Matsuo |first3=Naoto |title=MOS Devices for Low-Voltage and Low-Energy Applications |date=2017 |publisher=John Wiley & Sons |isbn=978-1119107354 |page=53 |url=https://books.google.com/books?id=yOjFDQAAQBAJ&pg=PA53}}</ref><ref name="Colinge2005"/><ref name="Grant1">{{cite book|url=https://books.google.com/books?id=ZiZTAAAAMAAJ|title=Power MOSFETS: theory and applications|last1=Grant|first1=Duncan Andrew|last2=Gowar|first2=John|date=1989|publisher=Wiley|isbn=978-0471828679|page=1|quote=The metal–oxide–semiconductor field-effect transistor (MOSFET) is the most commonly used active device in the very-large-scale integration of digital integrated circuits (VLSI). During the 1970s these components revolutionized electronic signal processing, control systems and computers.}}</ref> modern [[computing]],<ref>{{cite book|title=The Electronics Handbook|last1=Chen|first1=Tom|date=1996|publisher=[[CRC Press]]|isbn=978-0-8493-8345-8|editor-last1=Whitaker|editor-first1=Jerry C.|page=644|chapter=Integrated Circuits|chapter-url=https://books.google.com/books?id=DSHSqWQXm3oC&pg=PA644}}</ref> [[telecommunications]], the [[communications infrastructure]],<ref name="Omura53"/><ref name="Whiteley">{{cite book |last1=Whiteley |first1=Carol |last2=McLaughlin |first2=John Robert |title=Technology, Entrepreneurs, and Silicon Valley |date=2002 |publisher=Institute for the History of Technology |isbn=978-0964921719 |url=https://books.google.com/books?id=x9koAQAAIAAJ |quote=These active electronic components, or power semiconductor products, from Siliconix are used to switch and convert power in a wide range of systems, from portable information appliances to the communications infrastructure that enables the Internet. The company's power MOSFETs&nbsp;– tiny solid-state switches, or metal oxide semiconductor field-effect transistors&nbsp;– and power integrated circuits are widely used in cell phones and notebook computers to manage battery power efficiently}}</ref> the [[Internet]],<ref name="Omura53"/><ref name="Baker"/><ref name="Green">{{cite article |last1=Green |first1=M. M. |title=An overview on wireline communication systems for high-speed broadband communication |journal=Proceedings of Papers 5th European Conference on Circuits and Systems for Communications (ECCSC'10) |date=November 2010 |pages=1–8 |url=https://ieeexplore.ieee.org/document/5733843|isbn=978-1-61284-400-8}}</ref> [[digital telephony]],<ref name="Allstot">{{cite book|title=A Short History of Circuits and Systems: From Green, Mobile, Pervasive Networking to Big Data Computing|last1=Allstot|first1=David J.|date=2016|publisher=[[IEEE Circuits and Systems Society]]|isbn=978-8793609860|editor-last1=Maloberti|editor-first1=Franco|pages=105–10|chapter=Switched Capacitor Filters|editor-last2=Davies|editor-first2=Anthony C.|chapter-url=https://ieee-cas.org/sites/default/files/a_short_history_of_circuits_and_systems-_ebook-_web.pdf}}</ref> [[wireless]] telecommunications,<ref name="Baliga2005">{{cite book|url=https://books.google.com/books?id=StJpDQAAQBAJ|title=Silicon RF Power MOSFETS|last1=Baliga|first1=B. Jayant|date=2005|publisher=[[World Scientific]]|isbn=978-9812561213|author1-link=B. Jayant Baliga}}</ref><ref name="Asif">{{cite book |last1=Asif |first1=Saad |title=5G Mobile Communications: Concepts and Technologies |date=2018 |publisher=CRC Press |isbn=978-0429881343 |pages=128–34 |url=https://books.google.com/books?id=yg1mDwAAQBAJ&pg=PT128}}</ref> and [[mobile network]]s.<ref name="Asif"/> According to Colinge, the modern [[computer industry]] and [[digital telecommunication]] systems would not exist without the MOSFET.<ref name="Colinge2005"/> Advances in MOS technology has been the most important contributing factor in the rapid rise of [[network bandwidth]] in [[telecommunication network]]s, with bandwidth doubling every 18 months, from [[bits per second]] to [[terabit per second|terabits per second]] ([[Edholm's law]]).<ref name="Jindal">{{cite article |last1=Jindal |first1=R. P. |title=From millibits to terabits per second and beyond – Over 60 years of innovation |journal=2009 2nd International Workshop on Electron Devices and Semiconductor Technology |date=2009 |pages=1–6 |doi=10.1109/EDST.2009.5166093 |url=https://events.vtools.ieee.org/m/195547|isbn=978-1-4244-3831-0 |s2cid=25112828 }}</ref>
+=== MOS sensors ===
+{{see also|Sensor|Image sensor|Charge-coupled device|Active-pixel sensor}}
+MOS [[sensors]], also known as MOSFET sensors, are widely used to measure [[physics|physical]], [[chemistry|chemical]], [[biological]] and [[environmental]] parameters.<ref name="Bergveld"/> The [[ion-sensitive field-effect transistor]] (ISFET), for example, is widely used in [[biomedical]] applications.<ref name="Schoning"/> MOS [[Chemiresistor|chemiresistors]] and MOSFETs have also been extensively shown to have promising applications is gas sensing either as single sensor devices or as components in [[Chemical sensor array|chemical sensor arrays]].<ref>{{cite article|last1=Albert|first1=Keith J.|last2=Lewis|first2=Nathan S.|last3=Schauer|first3=Caroline L.|last4=Sotzing|first4=Gregory A.|last5=Stitzel|first5=Shannon E.|last6=Vaid|first6=Thomas P.|last7=Walt|first7=David R.|date=2000-07-01|title=Cross-Reactive Chemical Sensor Arrays|url=https://doi.org/10.1021/cr980102w|journal=Chemical Reviews|volume=100|issue=7|pages=2595–2626|doi=10.1021/cr980102w|pmid=11749297|issn=0009-2665}}</ref>
+MOSFETs are also widely used in [[microelectromechanical systems]] (MEMS), as silicon MOSFETs could interact and communicate with the surroundings and process things such as [[chemicals]], [[motions]] and [[light]].<ref name="Rai">{{cite book |last1=Rai-Choudhury |first1=P. |title=MEMS and MOEMS Technology and Applications |date=2000 |publisher=[[SPIE Press]] |isbn=978-0819437167 |pages=ix, 3–4 |url=https://books.google.com/books?id=v6KOTaI2DhAC&pg=PR9}}</ref> An early example of a MEMS device is the resonant-gate transistor, an adaptation of the MOSFET, developed by [[Harvey C. Nathanson]] in 1965.<ref>{{cite article|vauthors=Nathanson HC, Wickstrom RA|date=1965|title=A Resonant-Gate Silicon Surface Transistor with High-Q Band-Pass Properties|journal=[[Applied Physics Letters|Appl. Phys. Lett.]]|volume=7|issue=4|pages=84–86|doi=10.1063/1.1754323|bibcode=1965ApPhL...7...84N}}</ref>
+MOS technology is the basis for modern [[image sensor]]s, including the [[charge-coupled device]] (CCD) and the CMOS [[active-pixel sensor]] (CMOS sensor), used in [[digital imaging]] and [[digital camera]]s.<ref name="Williams"/> [[Willard Boyle]] and [[George E. Smith]] developed the CCD in 1969. While researching the MOS process, they realized that an electric charge was the analogy of the magnetic bubble and that it could be stored on a tiny MOS capacitor. As it was fairly straightforward to fabricate a series of MOS capacitors in a row, they connected a suitable voltage to them so that the charge could be stepped along from one to the next.<ref name="Williams"/> The CCD is a semiconductor circuit that was later used in the first [[digital video camera]]s for [[television broadcasting]].<ref>{{cite article|last1=Boyle|first1=William S|last2=Smith|first2=George E.|date=1970|title=Charge Coupled Semiconductor Devices|journal=Bell Syst. Tech. J.|volume=49|issue=4|pages=587–93|doi=10.1002/j.1538-7305.1970.tb01790.x}}</ref>
+The MOS [[active-pixel sensor]] (APS) was developed by Tsutomu Nakamura at [[Olympus Corporation|Olympus]] in 1985.<ref name=Nakamura85>{{cite article |last1=Matsumoto |first1=Kazuya |last2=Nakamura |first2=Tsutomu |last3=Yusa |first3=Atsushi |last4=Nagai |first4=Shohei |display-authors=1|date=1985 |title=A new MOS phototransistor operating in a non-destructive readout mode |journal=Japanese Journal of Applied Physics |volume=24 |issue=5A |page=L323|doi=10.1143/JJAP.24.L323 |bibcode=1985JaJAP..24L.323M }}</ref> The CMOS active-pixel sensor was later developed by [[Eric Fossum]] and his team at [[NASA]]'s [[Jet Propulsion Laboratory]] in the early 1990s.<ref name=fossum93>Eric R. Fossum (1993), "Active Pixel Sensors: Are CCD's Dinosaurs?" Proc. SPIE Vol. 1900, pp. 2–14, ''Charge-Coupled Devices and Solid State Optical Sensors III'', Morley M. Blouke; Ed.</ref>
+MOS image sensors are widely used in [[optical mouse]] technology. The first optical mouse, invented by [[Richard F. Lyon]] at [[Xerox]] in 1980, used a [[6 µm process|5&nbsp;µm]] [[NMOS logic|NMOS]] sensor chip.<ref name="Lyon2014">{{cite book |last1=Lyon |first1=Richard F. |author1-link=Richard F. Lyon |chapter=The Optical Mouse: Early Biomimetic Embedded Vision |title=Advances in Embedded Computer Vision |date=2014 |publisher=Springer |isbn=978-3319093871 |pages=3-22 (3) |chapter-url=https://books.google.com/books?id=p_GbBQAAQBAJ&pg=PA3}}</ref><ref name="Lyon1981">{{cite book | chapter = The Optical Mouse, and an Architectural Methodology for Smart Digital Sensors | title = VLSI Systems and Computations | pages = 1–19 | last1=Lyon | first1=Richard F. | author1-link=Richard F. Lyon |editor1=H. T. Kung |editor2=Robert F. Sproull |editor3=Guy L. Steele | publisher=Computer Science Press |date=August 1981 | doi=10.1007/978-3-642-68402-9_1 | chapter-url=http://bitsavers.trailing-edge.com/pdf/xerox/parc/techReports/VLSI-81-1_The_Optical_Mouse.pdf| isbn = 978-3-642-68404-3 }}</ref> Since the first commercial optical mouse, the [[IntelliMouse]] introduced in 1999, most optical mouse devices use CMOS sensors.<ref>{{cite article |last1=Brain |first1=Marshall |last2=Carmack |first2=Carmen |title=How Computer Mice Work |url=https://computer.howstuffworks.com/mouse4.htm |website=[[HowStuffWorks]] |access-date=9 October 2019 |language=en |date=24 April 2000}}</ref>
+===Power MOSFETs===
+{{see also|Power MOSFET|LDMOS#Applications|VMOS|FET amplifier|IGBT|MOS-controlled thyristor|Power electronics|Power semiconductor device}}
+The [[power MOSFET]] is the most widely used [[power device]] in the world.<ref name="aosmd"/> Advantages over [[bipolar junction transistor]]s in [[power electronics]] include MOSFETs not requiring a continuous flow of drive current to remain in the ON state, offering higher switching speeds, lower switching power losses, lower on-resistances, and reduced susceptibility to thermal runaway.<ref name="mouser">{{cite article |title=Power Supply Technology – Buck DC/DC Converters |url=https://www.mouser.co.uk/applications/power-supply-topology-buck/ |website=[[Mouser Electronics]] |access-date=11 August 2019}}</ref> The power MOSFET had an impact on [[power supplies]], enabling higher operating frequencies, size and weight reduction, and increased volume production.<ref>{{cite book |last1=Grant |first1=Duncan Andrew |last2=Gowar |first2=John |title=Power MOSFETS: theory and applications |date=1989 |publisher=Wiley |isbn=9780471828679 |page=239 |url=https://books.google.com/books?id=ZiZTAAAAMAAJ}}</ref>
+[[Switching power supplies]] are the most common applications for power MOSFETs.<ref name="electronicdesign"/> They are also widely used for MOS [[RF power amplifier]]s, which enabled the transition of [[mobile network]]s from analog to digital in the 1990s. This led to the wide proliferation of wireless mobile networks, which revolutionised [[telecommunication systems]].<ref name="Baliga2005"/> The [[LDMOS]] in particular is the most widely used power amplifier in mobile networks, such as [[2G]], [[3G]],<ref name="Baliga2005"/> [[4G]], and [[5G]].<ref name="Asif"/>
+Over 50&nbsp;billion discrete power MOSFETs are shipped annually, as of 2018. They are widely used for [[automotive]], [[Manufacturing|industrial]] and [[communications systems]] in particular.<ref>{{cite article |last1=Carbone |first1=James |title=Buyers can expect 30-week lead times and higher tags to continue for MOSFETs |journal=Electronics Sourcing |date=September–October 2018 |pages=18–19 |url=http://www.electronics-sourcing.com/wp-content/uploads/2018/08/ESE-SepOct18.pdf}}</ref> Power MOSFETs are commonly used in [[automotive electronics]], particularly as switching devices in [[electronic control unit]]s,<ref name="Fuji">{{cite article |title=Automotive Power MOSFETs |url=https://www.fujielectric.com/company/tech/pdf/r50-2/03.pdf |website=[[Fuji Electric]] |access-date=10 August 2019}}</ref> and as [[power converter]]s in modern [[electric vehicles]].<ref name="Gosden">{{cite article |last1=Gosden |first1=D.F. |title=Modern Electric Vehicle Technology using an AC Motor Drive |journal=Journal of Electrical and Electronics Engineering |date=March 1990 |volume=10 |issue=1 |pages=21–27 |url=https://trid.trb.org/view/353176 |publisher=[[Institution of Engineers Australia]] |issn=0725-2986}}</ref> The [[insulated-gate bipolar transistor]] (IGBT), a hybrid MOS-bipolar transistor, is also used for a wide variety of applications.<ref name="NIHF">{{cite article |title=NIHF Inductee Bantval Jayant Baliga Invented IGBT Technology |url=https://www.invent.org/inductees/bantval-jayant-baliga |website=[[National Inventors Hall of Fame]] |access-date=17 August 2019}}</ref>
+== Scaling ==
+{{see also|Dennard scaling|Moore's law|Transistor count|Edholm's law}}
+[[File:Intel gate length trend.PNG|thumb|upright=1.2|Trend of Intel CPU transistor gate length]]
+Over the past decades, the MOSFET (as used for digital logic) has continually been scaled down in size; typical MOSFET channel lengths were once several [[micrometre]]s, but modern integrated circuits are incorporating MOSFETs with channel lengths of tens of nanometers. [[Robert H. Dennard|Robert Dennard]]'s work on [[scaling law|scaling theory]] was pivotal in recognising that this ongoing reduction was possible. The semiconductor industry maintains a "roadmap", the [[International Technology Roadmap for Semiconductors|ITRS]],<ref>{{cite article | url = http://www.itrs.net | title = International Technology Roadmap for Semiconductors | url-status = dead | archive-url = https://web.archive.org/web/20151228041321/http://www.itrs.net/ | archive-date = 2015-12-28 }}</ref> which sets the pace for MOSFET development. Historically, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process, the need to use very low voltages, and with poorer electrical performance necessitating circuit redesign and innovation (small MOSFETs exhibit higher leakage currents and lower output resistance). As of 2019, the smallest MOSFETs in production are [[5&nbsp;nm]] [[FinFET]] [[semiconductor node]]s, manufactured by [[Samsung Electronics]] and [[TSMC]].<ref name="anandtech-samsung">{{cite article|url=https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|title=Samsung Completes Development of 5nm EUV Process Technology|last=Shilov|first=Anton|website=www.anandtech.com|access-date=2019-05-31}}</ref><ref>{{cite article |last1=Shilov |first1=Anton |title=TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019 |url=https://www.anandtech.com/show/13445/tsmc-first-7nm-euv-chips-taped-out-5nm-risk-in-q2}}</ref>
+Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area. Since fabrication costs for a [[Wafer (electronics)|semiconductor wafer]] are relatively fixed, the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the price per chip. In fact, over the past 30 years the number of transistors per chip has been doubled every 2–3 years once a new technology node is introduced. For example, the number of MOSFETs in a microprocessor fabricated in a [[45 nm]] technology can well be twice as many as in a [[65 nm]] chip. This doubling of transistor density was first observed by [[Gordon Moore]] in 1965 and is commonly referred to as [[Moore's law]].<ref>{{cite article | title = 1965&nbsp;– "Moore's Law" Predicts the Future of Integrated Circuits | work = Computer History Museum | url = http://www.computerhistory.org/semiconductor/timeline/1965-Moore.html}}</ref> It is also expected that smaller transistors switch faster. For example, one approach to size reduction is a scaling of the MOSFET that requires all device dimensions to reduce proportionally. The main device dimensions are the channel length, channel width, and oxide thickness. When they are scaled down by equal factors, the transistor channel resistance does not change, while [[gate capacitance]] is cut by that factor. Hence, the [[RC delay]] of the transistor scales with a similar factor. While this has been traditionally the case for the older technologies, for the state-of-the-art MOSFETs reduction of the transistor dimensions does not necessarily translate to higher chip speed because the delay due to interconnections is more significant.
+Producing MOSFETs with channel lengths much smaller than a [[micrometre]] is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. Though processes such as atomic layer deposition ([[atomic layer deposition|ALD]]) have improved fabrication for small components, the small size of the MOSFET (less than a few tens of nanometers) has created operational problems:
+; Higher subthreshold conduction: As MOSFET geometries shrink, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the ''on'' case and low current in the ''off'' case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips.<ref name=Roy>{{ cite book | first1 =Kaushik|last1=Roy |first2=Kiat Seng|last2=Yeo | title=Low Voltage, Low Power VLSI Subsystems | year = 2004 | page = Fig. 2.1, p. 44, Fig. 1.1, p. 4 | publisher = McGraw-Hill Professional | isbn = 978-0-07-143786-8 | url = https://books.google.com/books?id=jXm4pNxCSCYC&pg=PA4 | no-pp = true }}</ref><ref name=Goodnick>{{ cite book | first1 =Dragica|last1=Vasileska |first2=Stephen|last2=Goodnick | title=Computational Electronics | year = 2006 | page = 103 | publisher = Morgan & Claypool | isbn = 978-1-59829-056-1 | url = https://books.google.com/books?id=DBPnzqy5Fd8C&pg=PA103 }}</ref>
+; Increased gate-oxide leakage: The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2&nbsp;[[nanometer|nm]] (which in silicon is ~5&nbsp;[[atom]]s thick) the [[quantum mechanics|quantum mechanical]] phenomenon of [[Quantum tunneling|electron tunneling]] occurs between the gate and channel, leading to increased power consumption. [[Silicon dioxide]] has traditionally been used as the gate insulator. Silicon dioxide however has a modest dielectric constant. Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance (capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness). All else equal, a higher dielectric thickness reduces the [[quantum tunneling]] current through the dielectric between the gate and the channel. Insulators that have a larger [[dielectric constant]] than silicon dioxide (referred to as [[high-κ dielectric]]s), such as group IVb metal silicates e.g. [[hafnium]] and [[zirconium]] silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards. On the other hand, the barrier height of the new gate insulator is an important consideration; the difference in [[conduction band]] energy between the semiconductor and the dielectric (and the corresponding difference in [[valence band]] energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 [[Electronvolt|eV]]. For many alternative dielectrics the value is significantly lower, tending to increase the tunneling current, somewhat negating the advantage of higher dielectric constant. The maximum gate–source voltage is determined by the strength of the electric field able to be sustained by the gate dielectric before significant leakage occurs. As the insulating dielectric is made thinner, the electric field strength within it goes up for a fixed voltage. This necessitates using lower voltages with the thinner dielectric.
+; Increased junction leakage: To make devices smaller, junction design has become more complex, leading to higher [[Doping (semiconductors)|doping]] levels, shallower junctions, "halo" doping and so forth,<ref>{{cite article|url=http://frontiersemi.com/pdf/papers/RsLransist.pdf |title=Frontier Semiconductor Paper |access-date=2012-06-02 |url-status=dead |archive-url=https://web.archive.org/web/20120227064415/http://frontiersemi.com/pdf/papers/RsLransist.pdf |archive-date=February 27, 2012 }}</ref><ref name=Chen>{{ cite book | first = Wai-Kai|last=Chen | title = The VLSI Handbook | page = Fig. 2.28, p. 2–22 | year = 2006 | publisher = CRC Press | isbn = 978-0-8493-4199-1 | url = https://books.google.com/books?id=NDdsjtTLTd0C&pg=PT49 | no-pp = true}}</ref> all to decrease drain-induced barrier lowering (see the section on [[#Junction design|junction design]]). To keep these complex junctions in place, the annealing steps formerly used to remove damage and electrically active defects must be curtailed<ref>{{cite article|doi=10.1557/PROC-765-D7.4|first1=R.|last1=Lindsay|title=A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS|journal=MRS Proceedings|volume=765|year=2011|last2=Pawlak|last3=Kittl|last4=Henson|last5=Torregiani|last6=Giangrandi|last7=Surdeanu|last8=Vandervorst|last9=Mayur|last10=Ross|last11=McCoy|last12=Gelpey|last13=Elliott|last14=Pages|last15=Satta|last16=Lauwers|last17=Stolk|last18=Maex}}</ref> increasing junction leakage. Heavier doping is also associated with thinner depletion layers and more recombination centers that result in increased leakage current, even without lattice damage.
+; [[Drain-induced barrier lowering]] (DIBL) and ''V''<sub>T</sub> roll off: Because of the [[short-channel effect]], channel formation is not entirely done by the gate, but now the drain and source also affect the channel formation. As the channel length decreases, the depletion regions of the source and drain come closer together and make the threshold voltage (''V''<sub>T</sub>) a function of the length of the channel. This is called ''V''<sub>T</sub> roll-off. ''V''<sub>T</sub> also becomes function of drain to source voltage ''V''<sub>DS</sub>. As we increase the ''V''<sub>DS</sub>, the depletion regions increase in size, and a considerable amount of charge is depleted by the ''V''<sub>DS</sub>. The gate voltage required to form the channel is then lowered, and thus, the ''V''<sub>T</sub> decreases with an increase in ''V''<sub>DS</sub>. This effect is called drain induced barrier lowering (DIBL).
+; Lower output resistance: For analog operation, good gain requires a high MOSFET output impedance, which is to say, the MOSFET current should vary only slightly with the applied drain-to-source voltage. As devices are made smaller, the influence of the drain competes more successfully with that of the gate due to the growing proximity of these two electrodes, increasing the sensitivity of the MOSFET current to the drain voltage. To counteract the resulting decrease in output resistance, circuits are made more complex, either by requiring more devices, for example the [[cascode]] and [[cascade amplifier]]s, or by feedback circuitry using [[operational amplifiers]], for example a circuit like that in the adjacent figure.
+; Lower transconductance: The [[transconductance]] of the MOSFET decides its gain and is proportional to hole or [[electron mobility]] (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance.
+; Interconnect capacitance: Traditionally, switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, [[capacitance|interconnect capacitance]] (the capacitance of the metal-layer connections between different parts of the chip) is becoming a large percentage of capacitance.<ref>{{cite article|url=http://www.research.ibm.com/journal/rd/293/ibmrd2903G.pdf|title=VLSI wiring capacitance|date=9 February 2021|publisher=IBM Journal of Research and Development}}</ref><ref name=Soudris>{{ cite book | editor1-first = D.|editor1-last= Soudris|editor2-first=P.|editor2-last=Pirsch|editor3-first=E.|editor3-last=Barke | title = Integrated Circuit Design: Power and Timing Modeling, Optimization, and Simulation (10th Int. Workshop) | year = 2000 | page = [https://archive.org/details/springer_10.1007-3-540-45373-3/page/n49 38] | publisher = Springer | isbn = 978-3-540-41068-3 | url = https://archive.org/details/springer_10.1007-3-540-45373-3}}</ref> Signals have to travel through the interconnect, which leads to increased delay and lower performance.
+; Heat production: The ever-increasing density of MOSFETs on an integrated circuit creates problems of substantial localized heat generation that can impair circuit operation. Circuits operate more slowly at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling devices and methods are now required for many integrated circuits including microprocessors. [[Power MOSFET]]s are at risk of [[thermal runaway]]. As their on-state resistance rises with temperature, if the load is approximately a constant-current load then the power loss rises correspondingly, generating further heat. When the [[heatsink]] is not able to keep the temperature low enough, the junction temperature may rise quickly and uncontrollably, resulting in destruction of the device.
+; Process variations: With MOSFETs becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions: length, width, junction depths, oxide thickness ''etc.'', and become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain, more statistical. The random nature of manufacture means we do not know which particular example MOSFETs actually will end up in a particular instance of the circuit. This uncertainty forces a less optimal design because the design must work for a great variety of possible component MOSFETs. See [[Process variation (semiconductor)|process variation]], [[Design for manufacturability (IC)|design for manufacturability]], [[reliability engineering]], and [[statistical process control]].<ref name=Boning>{{ cite book | first1 = Michael|last1=Orshansky |first2=Sani|last2=Nassif |first3=Duane|last3=Boning | title=Design for Manufacturability And Statistical Design: A Constructive Approach | year = 2007 | publisher = Springer | location = New York 309284 | url = https://www.amazon.com/gp/reader/0387309284/ref=sib_dp_pt/002-1766819-0058402#reader-link|isbn=978-0387309286 }}</ref>
+; Modeling challenges: Modern ICs are computer-simulated with the goal of obtaining working circuits from the very first manufactured lot. As devices are miniaturized, the complexity of the processing makes it difficult to predict exactly what the final devices look like, and modeling of physical processes becomes more challenging as well. In addition, microscopic variations in structure due simply to the probabilistic nature of atomic processes require statistical (not just deterministic) predictions. These factors combine to make adequate simulation and "right the first time" manufacture difficult.
+A related scaling rule is [[Edholm's law]]. In 2004, Phil Edholm observed that the [[bandwidth (signal processing)|bandwidth]] of [[telecommunication network]]s (including the [[Internet]]) is doubling every 18 months.<ref name="Cherry">{{cite article |last1=Cherry |first1=Steven |title=Edholm's law of bandwidth |journal=IEEE Spectrum |date=2004 |volume=41 |issue=7 |pages=58–60 |doi=10.1109/MSPEC.2004.1309810|s2cid=27580722 }}</ref> Over the course of several decades, the bandwidths of [[communication networks]] has risen from [[bits per second]] to [[terabit per second|terabits per second]]. The rapid rise in [[telecommunication]] bandwidth is largely due to the same MOSFET scaling that enables Moore's law, as telecommunication networks are built from MOSFETs.<ref name="Jindal"/>
+== Timeline ==
+{{Main|List of semiconductor scale examples}}
+{{see also|Semiconductor device fabrication|Transistor density}}
+=== PMOS and NMOS ===
+{| class="wikitable sortable"
+|+ [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]] demonstrations
+! Date
+! data-sort-type="number" | [[MOSFET#Structure and channel formation|Channel length]]
+! data-sort-type="number" | [[Gate oxide|Oxide thickness]]<ref name="collins">{{cite article |title=Angstrom |url=https://www.collinsdictionary.com/dictionary/english/angstrom |website=[[Collins English Dictionary]] |access-date=2019-03-02}}</ref>
+! [[MOSFET]] [[logic family|logic]]
+! Researcher(s)
+! Organization
+! class="unsortable" | Ref
+|-
+|rowspan="4" | 1960-06
+|rowspan="2" | [[20 μm process|20,000 nm]]
+|rowspan="2" | [[100 nm]]
+|[[PMOS logic|PMOS]]
+|rowspan="2" | [[Mohamed M. Atalla]], [[Dawon Kahng]]
+|rowspan="2" | [[Bell Telephone Laboratories]]
+|rowspan="2" | <ref>{{cite book |last1=Sze |first1=Simon M. |author1-link=Simon Sze |title=Semiconductor Devices: Physics and Technology |date=2002 |publisher=[[Wiley (publisher)|Wiley]] |isbn=0-471-33372-7 |page=4 |edition=2nd |url=http://www.fulviofrisone.com/attachments/article/453/Semiconductor.Devices_Physics.Technology_Sze.2ndEd_Wiley_2002.pdf}}</ref><ref name="Atalla">{{cite article |last1=Atalla |first1=Mohamed M. |author1-link=Mohamed M. Atalla |last2=Kahng |first2=Dawon |author2-link=Dawon Kahng |title=Silicon–silicon dioxide field induced surface devices |journal=IRE-AIEE Solid State Device Research Conference |publisher=[[Carnegie Mellon University Press]] |date=June 1960}}</ref>
+|-
+|[[NMOS logic|NMOS]]
+|-
+|rowspan="2" | [[10 μm process|10,000 nm]]
+|rowspan="2" | {{#expr:1000/10}} [[nanometre|nm]]
+|PMOS
+|rowspan="2" | [[Mohamed M. Atalla]], [[Dawon Kahng]]
+|rowspan="2" | Bell Telephone Laboratories
+|rowspan="2" | <ref>{{cite book |last1=Voinigescu |first1=Sorin |title=High-Frequency Integrated Circuits |date=2013 |publisher=[[Cambridge University Press]] |isbn=9780521873024 |page=164 |url=https://books.google.com/books?id=71dHe1yb9jgC&pg=PA164}}</ref>
+|-
+|NMOS
+|-
+|rowspan="2" | 1965-05
+|8,000&nbsp;nm
+|[[Half-node|150 nm]]
+|NMOS
+|rowspan="2" | [[Chih-Tang Sah]], Otto Leistiko, A.S. Grove
+|rowspan="2" | [[Fairchild Semiconductor]]
+|rowspan="2" | <ref>{{cite article |last1=Sah |first1=Chih-Tang |author1-link=Chih-Tang Sah |last2=Leistiko |first2=Otto |last3=Grove |first3=A. S. |title=Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces |journal=[[IEEE Transactions on Electron Devices]] |date=May 1965 |volume=12 |issue=5 |pages=248–254 |doi=10.1109/T-ED.1965.15489 |bibcode=1965ITED...12..248L |url=https://pdfslide.net/documents/electron-and-hole-mobilities-in-inversion-layers-on-thermally-oxidized-silicon-57e531d33262d.html}}</ref>
+|-
+|[[6 μm process|5,000 nm]]
+|[[180 nanometer|170 nm]]
+|PMOS
+|-
+|1972-12
+|[[1 μm process|1,000 nm]]
+|?
+|PMOS
+|Hwa-Nien Yu, [[Robert H. Dennard]], Fritz H. Gaensslen
+|[[IBM T.J. Watson Research Center]]
+|<ref>{{cite article |last1=Dennard |first1=Robert H. |author1-link=Robert H. Dennard |last2=Gaensslen |first2=Fritz H. |last3=Yu |first3=Hwa-Nien |last4=Kuhn |first4=L. |title=Design of micron MOS switching devices |journal=1972 International Electron Devices Meeting |date=December 1972 |pages=168–170 |doi=10.1109/IEDM.1972.249198}}</ref><ref name="Hori">{{cite article |last1=Hori |first1=Ryoichi |last2=Masuda |first2=Hiroo |last3=Minato |first3=Osamu |last4=Nishimatsu |first4=Shigeru |last5=Sato |first5=Kikuji |last6=Kubo |first6=Masaharu |title=Short Channel MOS-IC Based on Accurate Two Dimensional Device Design |journal=[[Japanese Journal of Applied Physics]] |date=September 1975 |volume=15 |issue=S1 |pages=193 |doi=10.7567/JJAPS.15S1.193 |issn=1347-4065}}</ref><ref>{{cite article |last1=Critchlow |first1=D. L. |title=Recollections on MOSFET Scaling |journal=IEEE Solid-State Circuits Society Newsletter |date=2007 |volume=12 |issue=1 |pages=19–22 |doi=10.1109/N-SSC.2007.4785536 |doi-access=free}}</ref>
+|-
+|rowspan="2" | 1973
+|7,500&nbsp;nm
+|?
+|NMOS
+|Sohichi Suzuki
+|[[NEC]]
+|<ref name="shmj70s">{{cite article |title=1970s: Development and evolution of microprocessors |url=http://www.shmj.or.jp/english/pdf/ic/exhibi748E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019}}</ref><ref name="ucom-4">{{cite article |title=NEC 751 (uCOM-4) |publisher=The Antique Chip Collector's Page |url=http://www.antiquetech.com/chips/NEC751.htm |access-date=2010-06-11 |url-status=dead |archive-url=https://web.archive.org/web/20110525202756/http://www.antiquetech.com/chips/NEC751.htm |archive-date=2011-05-25}}</ref>
+|-
+|[[6 μm process|6,000 nm]]
+|?
+|PMOS
+|?
+|[[Toshiba]]
+|<ref name="shmj-1973-toshiba">{{cite article |title=1973: 12-bit engine-control microprocessor (Toshiba) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi739E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019}}</ref><ref>{{cite book |last1=Belzer |first1=Jack |last2=Holzman |first2=Albert G. |last3=Kent |first3=Allen |title=Encyclopedia of Computer Science and Technology: Volume 10 – Linear and Matrix Algebra to Microorganisms: Computer-Assisted Identification |date=1978 |publisher=[[CRC Press]] |isbn=9780824722609 |page=402 |url=https://books.google.com/books?id=iBsUXrgKBKkC&pg=PA402}}</ref>
+|-
+|rowspan="2" | 1974-10
+|1,000&nbsp;nm
+|rowspan="2" | [[45 nanometer|{{#expr:350/10}} nm]]
+|rowspan="2" | NMOS
+|rowspan="2" | Hwa-Nien Yu, [[Robert H. Dennard]], Fritz H. Gaensslen
+|rowspan="2" | IBM T.J. Watson Research Center
+|rowspan="2" | <ref>{{cite article |last1=Dennard |first1=Robert H. |author1-link=Robert H. Dennard |last2=Gaensslen |first2=F. H. |last3=Yu |first3=Hwa-Nien |last4=Rideout |first4=V. L. |last5=Bassous |first5=E. |last6=LeBlanc |first6=A. R. |title=Design of ion-implanted MOSFET's with very small physical dimensions |journal=[[IEEE Journal of Solid-State Circuits]] |date=October 1974 |volume=9 |issue=5 |pages=256–268 |doi=10.1109/JSSC.1974.1050511 |bibcode=1974IJSSC...9..256D |citeseerx=10.1.1.334.2417 |s2cid=283984 |url=http://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Design%20of%20ion-implanted%20MOSFETs%20with%20very%20small%20physical%20dimensions.pdf}}</ref>
+|-
+|[[500 nanometer|500 nm]]
+|-
+|1975-09
+|[[1.5 μm process|1,500 nm]]
+|[[22 nanometer|{{#expr:200/10}} nm]]
+|NMOS
+|Ryoichi Hori, Hiroo Masuda, Osamu Minato
+|[[Hitachi]]
+|<ref name="Hori"/><ref>{{cite article |last1=Kubo |first1=Masaharu |last2=Hori |first2=Ryoichi |last3=Minato |first3=Osamu |last4=Sato |first4=Kikuji |title=A threshold voltage controlling circuit for short channel MOS integrated circuits |journal=1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=February 1976 |volume=XIX |pages=54–55 |doi=10.1109/ISSCC.1976.1155515|s2cid=21048622 }}</ref>
+|-
+|1976-03
+|[[3 μm process|3,000 nm]]
+|?
+|NMOS
+|?
+|[[Intel]]
+|<ref>{{cite article|url=https://www.intel.com/pressroom/kits/quickrefyr.htm|title=Intel Microprocessor Quick Reference Guide|website=[[Intel]]|access-date=27 June 2019}}</ref>
+|-
+|1979-04
+|1,000&nbsp;nm
+|[[28 nanometer|25 nm]]
+|NMOS
+|William R. Hunter, L. M. Ephrath, Alice Cramer
+|IBM T.J. Watson Research Center
+|<ref>{{cite article |last1=Hunter |first1=William R. |last2=Ephrath |first2=L. M. |last3=Cramer |first3=Alice |last4=Grobman |first4=W. D. |last5=Osburn |first5=C. M. |last6=Crowder |first6=B. L. |last7=Luhn |first7=H. E. |title=1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography |journal=[[IEEE Journal of Solid-State Circuits]] |date=April 1979 |volume=14 |issue=2 |pages=275–281 |doi=10.1109/JSSC.1979.1051174|s2cid=26389509 }}</ref>
+|-
+|1984-12
+|[[130 nanometer|100 nm]]
+|[[5 nm]]
+|NMOS
+|Toshio Kobayashi, Seiji Horiguchi, K. Kiuchi
+|[[Nippon Telegraph and Telephone]]
+|<ref>{{cite article |last1=Kobayashi |first1=Toshio |last2=Horiguchi |first2=Seiji |last3=Kiuchi |first3=K. |title=Deep-submicron MOSFET characteristics with 5 nm gate oxide |journal=1984 International Electron Devices Meeting |date=December 1984 |pages=414–417 |doi=10.1109/IEDM.1984.190738|s2cid=46729489 }}</ref>
+|-
+|rowspan="2" | 1985-12
+|[[Half-node|150 nm]]
+|[[3 nanometer|2.5 nm]]
+|NMOS
+|Toshio Kobayashi, Seiji Horiguchi, M. Miyake, M. Oda
+|Nippon Telegraph and Telephone
+|<ref>{{cite article |last1=Kobayashi |first1=Toshio |last2=Horiguchi |first2=Seiji |last3=Miyake |first3=M. |last4=Oda |first4=M. |last5=Kiuchi |first5=K. |title=Extremely high transconductance (above 500 mS/mm) MOSFET with 2.5 nm gate oxide |journal=1985 International Electron Devices Meeting |date=December 1985 |pages=761–763 |doi=10.1109/IEDM.1985.191088|s2cid=22309664 }}</ref>
+|-
+|[[90 nanometer|75 nm]]
+|?
+|NMOS
+|Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis
+|[[MIT]]
+|<ref>{{cite article |last1=Chou |first1=Stephen Y. |last2=Antoniadis |first2=Dimitri A. |last3=Smith |first3=Henry I. |title=Observation of electron velocity overshoot in sub-100-nm-channel MOSFET's in Silicon |journal=IEEE Electron Device Letters |date=December 1985 |volume=6 |issue=12 |pages=665–667 |doi=10.1109/EDL.1985.26267|bibcode=1985IEDL....6..665C|s2cid=28493431 }}</ref>
+|-
+|1986-01
+|[[65 nanometer|60 nm]]
+|?
+|NMOS
+|Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis
+|MIT
+|<ref name="Chou">{{cite article |last1=Chou |first1=Stephen Y. |last2=Smith |first2=Henry I. |last3=Antoniadis |first3=Dimitri A. |title=Sub‐100‐nm channel‐length transistors fabricated using x‐ray lithography |journal=Journal of Vacuum Science & Technology B: Microelectronics Processing and Phenomena |date=January 1986 |volume=4 |issue=1 |pages=253–255 |doi=10.1116/1.583451 |bibcode=1986JVSTB...4..253C |issn=0734-211X}}</ref>
+|-
+|1986-12
+|[[65-nanometer process|60 nm]]
+|?
+|?
+|[[Ghavam G. Shahidi]], Dimitri A. Antoniadis, Henry I. Smith
+|[[MIT]]
+|<ref>G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, "A 60-nm Silicon MOSFET," in ''1986 International Electron Devices Meeting'', Dec 1986, pp. 222–225.</ref><ref>{{cite article |last1=Shahidi |first1=Ghavam G. |author1-link=Ghavam Shahidi |last2=Antoniadis |first2=Dimitri A. |last3=Smith |first3=Henry I. |title=Electron velocity overshoot at 300 K and 77 K in silicon MOSFETs with submicron channel lengths |journal=1986 International Electron Devices Meeting |date=December 1986 |pages=824–825 |doi=10.1109/IEDM.1986.191325|s2cid=27558025 }}</ref><ref name="Chou" />
+|-
+|1987-05
+|[[400 nm]]
+|[[10 nm process|10 nm]]
+|NMOS
+|[[Bijan Davari]], Chung-Yu Ting, Kie Y. Ahn, S. Basavaiah
+|[[IBM T.J. Watson Research Center]]
+|<ref name="Davari1987">{{cite article |last1=Davari |first1=Bijan |author1-link=Bijan Davari |last2=Ting |first2=Chung-Yu |last3=Ahn |first3=Kie Y. |last4=Basavaiah |first4=S. |last5=Hu |first5=Chao-Kun |last6=Taur |first6=Yuan |last7=Wordeman |first7=Matthew R. |last8=Aboelfotoh |first8=O. |first11=Michael R. |title=Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide |journal=1987 Symposium on VLSI Technology. Digest of Technical Papers |date=May 1987 |pages=61–62 |url=https://ieeexplore.ieee.org/document/4480422}}</ref>
+|-
+|1987-06
+|[[Die shrink|200 nm]]
+|[[4 nanometer|3.5 nm]]
+|PMOS
+|Toshio Kobayashi, M. Miyake, K. Deguchi
+|Nippon Telegraph and Telephone
+|<ref>{{cite article |last1=Kobayashi |first1=Toshio |last2=Miyake |first2=M.|last3=Deguchi |first3=K. |last4=Kimizuka |first4=M. |last5=Horiguchi |first5=Seiji |last6=Kiuchi |first6=K. |title=Subhalf-micrometer p-channel MOSFET's with 3.5-nm gate Oxide fabricated using X-ray lithography |journal=IEEE Electron Device Letters |date=1987 |volume=8 |issue=6 |pages=266–268 |doi=10.1109/EDL.1987.26625|bibcode=1987IEDL....8..266M|s2cid=38828156 }}</ref>
+|-
+|1993-12
+|[[40 nm]]
+|?
+|NMOS
+|Mizuki Ono, Masanobu Saito, Takashi Yoshitomi
+|Toshiba
+|<ref>{{cite article |last1=Ono |first1=Mizuki |last2=Saito |first2=Masanobu |last3=Yoshitomi |first3=Takashi |last4=Fiegna |first4=Claudio |last5=Ohguro |first5=Tatsuya |last6=Iwai |first6=Hiroshi |title=Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions |journal=Proceedings of IEEE International Electron Devices Meeting |date=December 1993 |pages=119–122 |doi=10.1109/IEDM.1993.347385|isbn=0-7803-1450-6|s2cid=114633315 }}</ref>
+|-
+|1996-09
+|[[16 nm]]
+|?
+|PMOS
+|Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba
+|NEC
+|<ref>{{cite article |last1=Kawaura |first1=Hisao |last2=Sakamoto |first2=Toshitsugu |last3=Baba |first3=Toshio |last4=Ochiai |first4=Yukinori |last5=Fujita |first5=Jun'ichi |last6=Matsui |first6=Shinji |last7=Sone |first7=Jun'ichi |title=Proposal of Pseudo Source and Drain MOSFETs for Evaluating 10-nm Gate MOSFETs |journal=[[Japanese Journal of Applied Physics]] |date=1997 |volume=36 |issue=3S |pages=1569 |doi=10.1143/JJAP.36.1569 |bibcode=1997JaJAP..36.1569K |language=en |issn=1347-4065}}</ref>
+|-
+|1998-06
+|[[55 nanometer|50 nm]]
+|[[3 nanometer|1.3 nm]]
+|NMOS
+|Khaled Z. Ahmed, Effiong E. Ibok, Miryeong Song
+|[[Advanced Micro Devices]] (AMD)
+|<ref>{{cite article |last1=Ahmed |first1=Khaled Z. |last2=Ibok |first2=Effiong E. |last3=Song |first3=Miryeong |last4=Yeap |first4=Geoffrey |last5=Xiang |first5=Qi |last6=Bang |first6=David S. |last7=Lin |first7=Ming-Ren |title=Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides |journal=1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) |date=1998 |pages=160–161 |doi=10.1109/VLSIT.1998.689240|isbn=0-7803-4770-6|s2cid=109823217 }}</ref><ref>{{cite article |last1=Ahmed |first1=Khaled Z. |last2=Ibok |first2=Effiong E. |last3=Song |first3=Miryeong |last4=Yeap |first4=Geoffrey |last5=Xiang |first5=Qi |last6=Bang |first6=David S. |last7=Lin |first7=Ming-Ren |title=Sub-100 nm nMOSFETs with direct tunneling thermal, nitrous and nitric oxides |journal=56th Annual Device Research Conference Digest (Cat. No.98TH8373) |date=1998 |pages=10–11 |doi=10.1109/DRC.1998.731099|isbn=0-7803-4995-4|s2cid=1849364 }}</ref>
+|-
+|2002-12
+|[[6 nanometer|6 nm]]
+|?
+|PMOS
+|Bruce Doris, Omer Dokumaci, Meikei Ieong
+|[[IBM]]
+|<ref>{{cite article |last1=Doris |first1=Bruce B. |last2=Dokumaci |first2=Omer H. |last3=Ieong |first3=Meikei K. |last4=Mocuta |first4=Anda |last5=Zhang |first5=Ying |last6=Kanarsky |first6=Thomas S. |last7=Roy |first7=R. A. |title=Extreme scaling with ultra-thin Si channel MOSFETs |journal=Digest. International Electron Devices Meeting |date=December 2002 |pages=267–270 |doi=10.1109/IEDM.2002.1175829|isbn=0-7803-7462-2|s2cid=10151651 }}</ref><ref name="Schwierz">{{cite book |last1=Schwierz |first1=Frank |last2=Wong |first2=Hei |last3=Liou |first3=Juin J. |title=Nanometer CMOS |date=2010 |publisher=Pan Stanford Publishing |isbn=9789814241083 |page=17 |url=https://books.google.com/books?id=IljcLHKwM3EC&pg=PA17 |language=en}}</ref><ref>{{cite article|url=http://www.theinquirer.net/inquirer/news/1034321/ibm-claims-worlds-smallest-silicon-transistor|title=IBM claims world's smallest silicon transistor – TheINQUIRER|website=Theinquirer.net|access-date=7 December 2017|date=2002-12-09}}</ref>
+|-
+|rowspan="2" | 2003-12
+|rowspan="2" | [[3 nm]]
+|rowspan="2" | ?
+|PMOS
+|rowspan="2" | Hitoshi Wakabayashi, Shigeharu Yamagami
+|rowspan="2" | NEC
+|rowspan="2" | <ref name="Wakabayashi">{{cite article |last1=Wakabayashi |first1=Hitoshi |last2=Yamagami |first2=Shigeharu |last3=Ikezawa |first3=Nobuyuki |last4=Ogura |first4=Atsushi |last5=Narihiro |first5=Mitsuru |last6=Arai |first6=K. |last7=Ochiai |first7=Y. |last8=Takeuchi |first8=K. |last9=Yamamoto |first9=T. |last10=Mogami |first10=T. |title=Sub-10-nm planar-bulk-CMOS devices using lateral junction control |journal=IEEE International Electron Devices Meeting 2003 |date=December 2003 |pages=20.7.1–20.7.3 |doi=10.1109/IEDM.2003.1269446|isbn=0-7803-7872-5|s2cid=2100267 }}</ref><ref name="Schwierz"/>
+|-
+|NMOS
+|}
+=== CMOS (single-gate) ===
+{| class="wikitable sortable"
+|+ [[CMOS]] demonstrations ([[Metal gate|single-gate]])
+! Date
+! data-sort-type="number" | [[MOSFET#Structure and channel formation|Channel length]]
+! data-sort-type="number" | [[Gate oxide|Oxide thickness]]<ref name="collins"/>
+! Researcher(s)
+! Organization
+! class="unsortable" | Ref
+|-
+|1963-02
+|?
+|?
+|[[Chih-Tang Sah]], [[Frank Wanlass]]
+|[[Fairchild Semiconductor]]
+|<ref name="computerhistory1963"/><ref name="sah">{{cite article |last1=Sah |first1=Chih-Tang |author1-link=Chih-Tang Sah |last2=Wanlass |first2=Frank |author2-link=Frank Wanlass |title=Nanowatt logic using field-effect metal–oxide semiconductor triodes |journal=1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=February 1963 |volume=VI |pages=32–33 |doi=10.1109/ISSCC.1963.1157450}}</ref>
+|-
+|1968
+|20,000 [[Nanometre|nm]]
+|[[130 nanometer|{{#expr:1000/10}} nm]]
+|?
+|[[RCA Laboratories]]
+|<ref name="Lojek330">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=330 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330}}</ref>
+|-
+|1970
+|[[10 μm process|10,000 nm]]
+|{{#expr:1000/10}} nm
+|?
+|RCA Laboratories
+|<ref name="Lojek330"/>
+|-
+|1976-12
+|[[3 μm process|2,000 nm]]
+|?
+|A. Aitken, R.G. Poulsen, A.T.P. MacArthur, J.J. White
+|[[Mitel|Mitel Semiconductor]]
+|<ref>{{cite article |last1=Aitken |first1=A. |last2=Poulsen |first2=R. G. |last3=MacArthur |first3=A. T. P. |last4=White |first4=J. J. |title=A fully plasma etched-ion implanted CMOS process |journal=1976 International Electron Devices Meeting |date=December 1976 |pages=209–213 |doi=10.1109/IEDM.1976.189021|s2cid=24526762 }}</ref>
+|-
+|1978-02
+|[[3 μm process|3,000 nm]]
+|?
+|Toshiaki Masuhara, Osamu Minato, Toshio Sasaki, Yoshio Sakai
+|[[Hitachi|Hitachi Central Research Laboratory]]
+|<ref name="shmj">{{cite article |title=1978: Double-well fast CMOS SRAM (Hitachi) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |website=Semiconductor History Museum of Japan |access-date=5 July 2019}}</ref><ref>{{cite article |last1=Masuhara |first1=Toshiaki |last2=Minato |first2=Osamu |last3=Sasaki |first3=Toshio |last4=Sakai |first4=Yoshio |last5=Kubo |first5=Masaharu |last6=Yasui |first6=Tokumasa |title=A high-speed, low-power Hi-CMOS 4K static RAM |journal=1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=February 1978 |volume=XXI |pages=110–111 |doi=10.1109/ISSCC.1978.1155749|s2cid=30753823 }}</ref><ref>{{cite article |last1=Masuhara |first1=Toshiaki |last2=Minato |first2=Osamu |last3=Sakai |first3=Yoshi |last4=Sasaki |first4=Toshio |last5=Kubo |first5=Masaharu |last6=Yasui |first6=Tokumasa |title=Short Channel Hi-CMOS Device and Circuits |journal=ESSCIRC 78: 4th European Solid State Circuits Conference – Digest of Technical Papers |date=September 1978 |pages=131–132 |url=https://ieeexplore.ieee.org/document/5469023}}</ref>
+|-
+|rowspan="2" | 1983-02
+|[[1.5 μm process|1,200 nm]]
+|[[32 nanometer|{{#expr:250/10}} nm]]
+|R.J.C. Chwang, M. Choi, D. Creek, S. Stern, P.H. Pelley
+|[[Intel]]
+|<ref name="Gealow">{{cite article |last1=Gealow |first1=Jeffrey Carl |title=Impact of Processing Technology on DRAM Sense Amplifier Design |url=https://core.ac.uk/download/pdf/4426308.pdf |publisher=[[Massachusetts Institute of Technology]] |website=[[COnnecting REpositories|CORE]] |date=10 August 1990 |pages=149–166 |access-date=25 June 2019}}</ref><ref>{{cite article |last1=Chwang |first1=R. J. C. |last2=Choi |first2=M. |last3=Creek |first3=D. |last4=Stern |first4=S. |last5=Pelley |first5=P. H. |last6=Schutz |first6=Joseph D. |last7=Bohr |first7=M. T. |last8=Warkentin |first8=P. A. |last9=Yu |first9=K. |title=A 70ns high density CMOS DRAM |journal=1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=February 1983 |volume=XXVI |pages=56–57 |doi=10.1109/ISSCC.1983.1156456|s2cid=29882862 }}</ref>
+|-
+|[[1 μm process|900 nm]]
+|[[16 nanometer|{{#expr:150/10}} nm]]
+|Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima
+|[[Nippon Telegraph and Telephone]] (NTT)
+|<ref name="Gealow"/><ref>{{cite article |last1=Mano |first1=Tsuneo |last2=Yamada |first2=J. |last3=Inoue |first3=Junichi |last4=Nakajima |first4=S. |title=Submicron VLSI memory circuits |journal=1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=February 1983 |volume=XXVI |pages=234–235 |doi=10.1109/ISSCC.1983.1156549|s2cid=42018248 }}</ref>
+|-
+|1983-12
+|[[1 μm process|1,000 nm]]
+|[[28 nanometer|{{#expr:225/10}} nm]]
+|G.J. Hu, Yuan Taur, [[Robert H. Dennard]], Chung-Yu Ting
+|[[IBM T.J. Watson Research Center]]
+|<ref>{{cite article |last1=Hu |first1=G. J. |last2=Taur |first2=Yuan |last3=Dennard |first3=Robert H. |author3-link=Robert H. Dennard |last4=Terman |first4=L. M. |last5=Ting |first5=Chung-Yu |title=A self-aligned 1-μm CMOS technology for VLSI |journal=1983 International Electron Devices Meeting |date=December 1983 |pages=739–741 |doi=10.1109/IEDM.1983.190615|s2cid=20070619 }}</ref>
+|-
+|rowspan="2" | 1987-02
+|[[800 nanometer|800 nm]]
+|[[20 nanometer|17 nm]]
+|T. Sumi, Tsuneo Taniguchi, Mikio Kishimoto, Hiroshige Hirano
+|[[Panasonic|Matsushita]]
+|<ref name="Gealow"/><ref>{{cite article |last1=Sumi |first1=T. |last2=Taniguchi |first2=Tsuneo |last3=Kishimoto |first3=Mikio |last4=Hirano |first4=Hiroshige |last5=Kuriyama |first5=H. |last6=Nishimoto |first6=T. |last7=Oishi |first7=H. |last8=Tetakawa |first8=S. |title=A 60ns 4Mb DRAM in a 300mil DIP |journal=1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=1987 |volume=XXX |pages=282–283 |doi=10.1109/ISSCC.1987.1157106|s2cid=60783996 }}</ref>
+|-
+|700&nbsp;nm
+|[[12 nm]]
+|Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima
+|Nippon Telegraph and Telephone (NTT)
+|<ref name="Gealow"/><ref>{{cite article |last1=Mano |first1=Tsuneo |last2=Yamada |first2=J. |last3=Inoue |first3=Junichi |last4=Nakajima |first4=S. |last5=Matsumura |first5=Toshiro |last6=Minegishi |first6=K. |last7=Miura |first7=K. |last8=Matsuda |first8=T. |last9=Hashimoto |first9=C. |last10=Namatsu |first10=H. |title=Circuit technologies for 16Mb DRAMs |journal=1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=1987 |volume=XXX |pages=22–23 |doi=10.1109/ISSCC.1987.1157158|s2cid=60984466 }}</ref>
+|-
+|1987-09
+|[[500 nm]]
+|[[14 nanometer|12.5 nm]]
+|[[Hussein I. Hanafi]], [[Robert H. Dennard]], Yuan Taur, Nadim F. Haddad
+|IBM T.J. Watson Research Center
+|<ref>{{cite article |last1=Hanafi |first1=Hussein I. |last2=Dennard |first2=Robert H. |author2-link=Robert H. Dennard |last3=Taur |first3=Yuan |last4=Haddad |first4=Nadim F. |last5=Sun |first5=J. Y. C. |last6=Rodriguez |first6=M. D. |title=0.5 μm CMOS Device Design and Characterization |journal=ESSDERC '87: 17th European Solid State Device Research Conference |date=September 1987 |pages=91–94 |url=https://ieeexplore.ieee.org/document/5436921}}</ref>
+|-
+|1987-12
+|[[250 nanometer|250 nm]]
+|?
+|Naoki Kasai, Nobuhiro Endo, Hiroshi Kitajima
+|[[NEC]]
+|<ref>{{cite article |last1=Kasai |first1=Naoki |last2=Endo |first2=Nobuhiro |last3=Kitajima |first3=Hiroshi |title=0.25 μm CMOS technology using P+polysilicon gate PMOSFET |journal=1987 International Electron Devices Meeting |date=December 1987 |pages=367–370 |doi=10.1109/IEDM.1987.191433|s2cid=9203005 }}</ref>
+|-
+|1988-02
+|400&nbsp;nm
+|[[10 nanometer|{{#expr:100/10}} nm]]
+|M. Inoue, H. Kotani, T. Yamada, Hiroyuki Yamauchi
+|Matsushita
+|<ref name="Gealow"/><ref>{{cite article |last1=Inoue |first1=M. |last2=Kotani |first2=H. |last3=Yamada |first3=T. |last4=Yamauchi |first4=Hiroyuki |last5=Fujiwara |first5=A. |last6=Matsushima |first6=J. |last7=Akamatsu |first7=Hironori |last8=Fukumoto |first8=M. |last9=Kubota |first9=M. |last10=Nakao |first10=I. |last11=Aoi |title=A 16mb Dram with an Open Bit-Line Architecture |journal=1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers |date=1988 |pages=246– |doi=10.1109/ISSCC.1988.663712|s2cid=62034618 }}</ref>
+|-
+|1990-12
+|[[110 nanometer|100 nm]]
+|?
+|[[Ghavam G. Shahidi]], [[Bijan Davari]], Yuan Taur, James D. Warnock
+|IBM T.J. Watson Research Center
+|<ref>{{cite article |last1=Shahidi |first1=Ghavam G. |author1-link=Ghavam Shahidi |last2=Davari |first2=Bijan |author2-link=Bijan Davari |last3=Taur |first3=Yuan |last4=Warnock |first4=James D. |last5=Wordeman |first5=Matthew R. |last6=McFarland |first6=P. A. |last7=Mader |first7=S. R. |last8=Rodriguez |first8=M. D. |title=Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing |journal=International Technical Digest on Electron Devices |date=December 1990 |pages=587–590 |doi=10.1109/IEDM.1990.237130|s2cid=114249312 }}</ref>
+|-
+|1993
+|[[350 nanometer|350 nm]]
+|?
+|?
+|[[Sony]]
+|rowspan="2" | <ref name="stol">{{cite article|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|access-date=25 June 2019|archive-url=https://web.archive.org/web/20071011052352/maltiel-consulting.com/Semiconductor_technology_memory.html|archive-date=2007-10-11}}</ref>
+|-
+|1996
+|[[Half-node|150 nm]]
+|?
+|?
+|[[Mitsubishi Electric]]
+|-
+|1998
+|[[180 nanometer|180 nm]]
+|?
+|?
+|[[TSMC]]
+|<ref>{{cite article |title=0.18-micron Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/0.18um.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref>
+|-
+|2003-12
+|[[5 nm]]
+|?
+|Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki Ikezawa
+|NEC
+|<ref name="Wakabayashi"/><ref>{{cite article|url=http://www.thefreelibrary.com/NEC+test-produces+world's+smallest+transistor.-a0111295563|title=NEC test-produces world's smallest transistor|website=Thefreelibrary.com|access-date=7 December 2017}}</ref>
+|}
+=== Multi-gate MOSFET (MuGFET) ===
+{| class="wikitable sortable"
+|+ [[Multi-gate MOSFET]] demonstrations
+! Date
+! data-sort-type="number" | [[MOSFET#Structure and channel formation|Channel length]]
+![[Multigate device|MuGFET]] type
+! Researcher(s)
+! Organization
+! class="unsortable" | Ref
+|-
+|1987
+|[[3 μm process|2,000 nm]]
+|DGMOS
+|Toshihiro Sekigawa
+|Electrotechnical Laboratory (ETL)
+|<ref name="Koike">{{cite article |first1=Hanpei |last1=Koike |first2=Tadashi |last2=Nakagawa |first3=Toshiro |last3=Sekigawa |first4=E. |last4=Suzuki |first5=Toshiyuki |last5=Tsutsumi |title=Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode |journal=TechConnect Briefs |date=23 February 2003 |volume=2 |issue=2003 |pages=330–333 |s2cid=189033174 |url=https://pdfs.semanticscholar.org/1a31/399021f62ae3d00dd6dd42d2bc7483598d26.pdf |archive-url=https://web.archive.org/web/20190926013047/https://pdfs.semanticscholar.org/1a31/399021f62ae3d00dd6dd42d2bc7483598d26.pdf |url-status=dead |archive-date=26 September 2019 }}</ref>
+|-
+|rowspan="3" | 1988-12
+|[[250 nanometer|250 nm]]
+|rowspan="2" | DGMOS
+|rowspan="2" | [[Bijan Davari]], Wen-Hsing Chang, Matthew R. Wordeman, C.S. Oh
+|rowspan="2" | [[IBM T.J. Watson Research Center]]
+|rowspan="2" | <ref>{{cite article |last1=Davari |first1=Bijan |author1-link=Bijan Davari |last2=Chang |first2=Wen-Hsing |last3=Wordeman |first3=Matthew R. |last4=Oh |first4=C. S. |last5=Taur |first5=Yuan |last6=Petrillo |first6=Karen E. |last7=Rodriguez |first7=M. D. |title=A high performance 0.25 mu m CMOS technology |journal=Technical Digest., International Electron Devices Meeting |date=December 1988 |pages=56–59 |doi=10.1109/IEDM.1988.32749|s2cid=114078857 }}</ref><ref>{{cite article |last1=Davari |first1=Bijan |author1-link=Bijan Davari |last2=Wong |first2=C. Y. |last3=Sun |first3=Jack Yuan-Chen |last4=Taur |first4=Yuan |title=Doping of n/sup +/ and p/sup +/ polysilicon in a dual-gate CMOS process |journal=Technical Digest., International Electron Devices Meeting |date=December 1988 |pages=238–241 |doi=10.1109/IEDM.1988.32800|s2cid=113918637 }}</ref>
+|-
+|[[180 nm]]
+|-
+|?
+|[[GAAFET]]
+|[[Fujio Masuoka]], Hiroshi Takato, Kazumasa Sunouchi, N. Okabe
+|[[Toshiba]]
+|<ref>{{cite article |last1=Masuoka |first1=Fujio |author1-link=Fujio Masuoka |last2=Takato |first2=Hiroshi |last3=Sunouchi |first3=Kazumasa |last4=Okabe |first4=N. |last5=Nitayama |first5=Akihiro |last6=Hieda |first6=K. |last7=Horiguchi |first7=Fumio |title=High performance CMOS surrounding-gate transistor (SGT) for ultra high density LSIs |journal=Technical Digest., International Electron Devices Meeting |date=December 1988 |pages=222–225 |doi=10.1109/IEDM.1988.32796|s2cid=114148274 }}</ref><ref>{{cite book |last1=Brozek |first1=Tomasz |title=Micro- and Nanoelectronics: Emerging Device Challenges and Solutions |date=2017 |publisher=[[CRC Press]] |isbn=9781351831345 |page=117 |url=https://books.google.com/books?id=dAhEDwAAQBAJ&pg=PA117}}</ref><ref name="Ishikawa">{{cite book |last1=Ishikawa |first1=Fumitaro |last2=Buyanova |first2=Irina |title=Novel Compound Semiconductor Nanowires: Materials, Devices, and Applications |date=2017 |publisher=[[CRC Press]] |isbn=9781315340722 |page=457 |url=https://books.google.com/books?id=klk6DwAAQBAJ&pg=PT457}}</ref>
+|-
+|1989-12
+|[[Half-node|200 nm]]
+|[[FinFET]]
+|Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, Eiji Takeda
+|[[Hitachi|Hitachi Central Research Laboratory]]
+|<ref>{{cite book |last1=Colinge |first1=J.P. |title=FinFETs and Other Multi-Gate Transistors |date=2008 |publisher=Springer Science & Business Media |isbn=9780387717517 |page=11 |url=https://books.google.com/books?id=t1ojkCdTGEEC&pg=PA11}}</ref><ref>{{cite article |last1=Hisamoto |first1=Digh |last2=Kaga |first2=Toru |last3=Kawamoto |first3=Yoshifumi |last4=Takeda |first4=Eiji |title=A fully depleted lean-channel transistor (DELTA): a novel vertical ultra thin SOI MOSFET |journal=International Technical Digest on Electron Devices Meeting |date=December 1989 |pages=833–836 |doi=10.1109/IEDM.1989.74182|s2cid=114072236 }}</ref><ref>{{cite article |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |website=[[IEEE Andrew S. Grove Award]] |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=4 July 2019}}</ref>
+|-
+|1998-12
+|[[20 nanometer|17 nm]]
+|FinFET
+|Digh Hisamoto, [[Chenming Hu]], [[Tsu-Jae King Liu]], Jeffrey Bokor
+|[[University of California (Berkeley)]]
+|<ref name="Liu">{{cite article |last1=Tsu‐Jae King |first1=Liu |author-link1=Tsu-Jae King Liu |title=FinFET: History, Fundamentals and Future |url=https://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse |website=[[University of California, Berkeley]] |publisher=Symposium on VLSI Technology Short Course |date=June 11, 2012 |access-date=9 July 2019 |archive-url=https://web.archive.org/web/20160528220227/http://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse |archive-date=28 May 2016 |url-status=live}}</ref><ref>{{cite article |last1=Hisamoto |first1=Digh |last2=Hu |first2=Chenming |last3=Liu |first3=Tsu-Jae King |last4=Bokor |first4=Jeffrey |last5=Lee |first5=Wen-Chin |last6=Kedzierski |first6=Jakub |last7=Anderson |first7=Erik |last8=Takeuchi |first8=Hideki |last9=Asano |first9=Kazuya |title=A folded-channel MOSFET for deep-sub-tenth micron era |journal=International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) |date=December 1998 |pages=1032–1034 |doi=10.1109/IEDM.1998.746531|isbn=0-7803-4774-9|s2cid=37774589 }}</ref>
+|-
+|2001
+|[[16 nanometer|15 nm]]
+|FinFET
+|[[Chenming Hu]], Yang‐Kyu Choi, Nick Lindert, [[Tsu-Jae King Liu]]
+|University of California (Berkeley)
+|<ref name="Liu"/><ref>{{cite article |last1=Hu |first1=Chenming |author1-link=Chenming Hu |last2=Choi |first2=Yang‐Kyu |last3=Lindert |first3=N. |last4=Xuan |first4=P. |last5=Tang |first5=S. |last6=Ha |first6=D. |last7=Anderson |first7=E. |last8=Bokor |first8=J. |last9=Tsu-Jae King |first9=Liu |title=Sub-20 nm CMOS FinFET technologies |journal=International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) |date=December 2001 |pages=19.1.1–19.1.4 |doi=10.1109/IEDM.2001.979526|isbn=0-7803-7050-3|s2cid=8908553 }}</ref>
+|-
+|2002-12
+|[[10 nm]]
+|FinFET
+|Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor
+|University of California (Berkeley)
+|<ref name="Liu"/><ref>{{cite article |last1=Ahmed |first1=Shibly |last2=Bell |first2=Scott |last3=Tabery |first3=Cyrus |last4=Bokor |first4=Jeffrey |last5=Kyser |first5=David |last6=Hu |first6=Chenming |last7=Liu |first7=Tsu-Jae King |last8=Yu |first8=Bin |last9=Chang |first9=Leland |title=FinFET scaling to 10 nm gate length |journal=Digest. International Electron Devices Meeting |date=December 2002 |pages=251–254 |doi=10.1109/IEDM.2002.1175825 |citeseerx=10.1.1.136.3757 |url=https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet4.pdf|isbn=0-7803-7462-2|s2cid=7106946 }}</ref>
+|-
+|2006-06
+|[[3 nm]]
+|GAAFET
+|Hyunjin Lee, Yang-kyu Choi, Lee-Eun Yu, Seong-Wan Ryu
+|[[KAIST]]
+|<ref>{{cite article |last1=Lee |first1=Hyunjin |last2=Choi |first2=Yang-Kyu |last3=Yu |first3=Lee-Eun |last4=Ryu |first4=Seong-Wan |last5=Han |first5=Jin-Woo |last6=Jeon |first6=K. |last7=Jang |first7=D.Y. |last8=Kim |first8=Kuk-Hwan |last9=Lee |first9=Ju-Hyun |date=June 2006 |title=Sub-5nm All-Around Gate FinFET for Ultimate Scaling |journal=Symposium on VLSI Technology, 2006 |pages=58–59 |doi=10.1109/VLSIT.2006.1705215 |isbn=978-1-4244-0005-8 |hdl=10203/698 |s2cid=26482358 |hdl-access=free}}</ref><ref>{{cite article |url=http://www.highbeam.com/doc/1G1-145838158.html|archive-url=https://web.archive.org/web/20121106011401/http://www.highbeam.com/doc/1G1-145838158.html|url-status=dead|archive-date=6 November 2012|title=Still Room at the Bottom (nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )|date=1 April 2006|work=Nanoparticle News}}</ref>
+|}
+=== Other types of MOSFET ===
+{| class="wikitable sortable"
+|+ Other [[MOSFET]] demonstrations
+! Date
+! data-sort-type="number" | [[MOSFET#Structure and channel formation|Channel<br>length<br>(nm)]]
+! data-sort-type="number" | [[Gate oxide|Oxide<br>thickness<br>(nm)]]<ref name="collins"/>
+! [[MOSFET]]<br>[[MOSFET#Types of MOSFET|type]]
+! Researcher(s)
+! Organization
+! class="unsortable" | Ref
+|-
+|1962-10
+|?
+|?
+|[[Thin-film transistor|TFT]]
+|[[Paul K. Weimer]]
+|[[RCA Laboratories]]
+|<ref>{{cite article |last1=Weimer |first1=Paul K. |author1-link=Paul K. Weimer |title=The TFT A New Thin-Film Transistor |journal=[[Proceedings of the IRE]] |date=June 1962 |volume=50 |issue=6 |pages=1462–1469 |doi=10.1109/JRPROC.1962.288190 |s2cid=51650159 |issn=0096-8390}}</ref><ref name="Kuo">{{cite article |last1=Kuo |first1=Yue |title=Thin Film Transistor Technology—Past, Present, and Future |journal=The Electrochemical Society Interface |date=1 January 2013 |volume=22 |issue=1 |pages=55–61 |doi=10.1149/2.F06131if |bibcode=2013ECSIn..22a..55K |url=https://www.electrochem.org/dl/interface/spr/spr13/spr13_p055_061.pdf |issn=1064-8208|doi-access=free }}</ref>
+|-
+|1965
+|?
+|?
+|[[GaAs]]
+|H. Becke, R. Hall, J. White
+|RCA Laboratories
+|<ref>{{cite book |last1=Ye |first1=Peide D. |last2=Xuan |first2=Yi |last3=Wu |first3=Yanqing |last4=Xu |first4=Min |chapter=Atomic-Layer Deposited High-k/III-V Metal-Oxide-Semiconductor Devices and Correlated Empirical Model |editor-last1=Oktyabrsky |editor-first1=Serge |editor-last2=Ye |editor-first2=Peide |title=Fundamentals of III-V Semiconductor MOSFETs |date=2010 |publisher=[[Springer Science & Business Media]] |pages=173–194 |doi=10.1007/978-1-4419-1547-4_7 |isbn=978-1-4419-1547-4 |chapter-url=https://books.google.com/books?id=sk2SrZH3xEcC&pg=PA173}}</ref>
+|-
+|1966-10
+|100,000
+|[[130 nanometer|{{#expr:1000/10}}]]
+|TFT
+|T.P. Brody, H.E. Kunig
+|[[Westinghouse Electric]]
+|<ref>{{cite article |last1=Brody |first1=T. P. |last2=Kunig |first2=H. E. |title=A HIGH‐GAIN InAs THIN‐FILM TRANSISTOR |journal=Applied Physics Letters |date=October 1966 |volume=9 |issue=7 |pages=259–260 |doi=10.1063/1.1754740 |bibcode=1966ApPhL...9..259B |issn=0003-6951}}</ref><ref>{{cite book |last1=Woodall |first1=Jerry M. |author1-link=Jerry Woodall |title=Fundamentals of III-V Semiconductor MOSFETs |date=2010 |publisher=[[Springer Science & Business Media]] |isbn=9781441915474 |pages=2–3 |url=https://books.google.com/books?id=sk2SrZH3xEcC&pg=PA2}}</ref>
+|-
+|1967-08
+|?
+|?
+|[[FGMOS]]
+|[[Dawon Kahng]], [[Simon Min Sze]]
+|[[Bell Telephone Laboratories]]
+|<ref>{{cite article |last1=Kahng |first1=Dawon |author1-link=Dawon Kahng |last2=Sze |first2=Simon Min |author2-link=Simon Sze |title=A floating gate and its application to memory devices |journal=[[The Bell System Technical Journal]] |date=July–August 1967 |volume=46 |issue=6 |pages=1288–1295 |doi=10.1002/j.1538-7305.1967.tb01738.x|bibcode=1967ITED...14Q.629K}}</ref>
+|-
+|1967-10
+|?
+|?
+|[[Metal–nitride–oxide–semiconductor transistor|MNOS]]
+|H.A. Richard Wegener, A.J. Lincoln, H.C. Pao
+|[[Sperry Corporation]]
+|<ref>{{cite article|last1=Wegener|first1=H. A. R.|last2=Lincoln|first2=A. J.|last3=Pao|first3=H. C.|last4=O'Connell|first4=M. R.|last5=Oleksiak|first5=R. E.|last6=Lawrence|first6=H.|title=The variable threshold transistor, a new electrically-alterable, non-destructive read-only storage device|journal=1967 International Electron Devices Meeting|date=October 1967|volume=13|pages=70|doi=10.1109/IEDM.1967.187833}}</ref>
+|-
+|1968-07
+|?
+|?
+|[[BiMOS]]
+|[[Hung-Chang Lin]], Ramachandra R. Iyer
+|[[Westinghouse Electric]]
+|<ref>{{cite article |last1=Lin |first1=Hung Chang |author1-link=Hung-Chang Lin |last2=Iyer |first2=Ramachandra R. |title=A Monolithic Mos-Bipolar Audio Amplifier |journal=IEEE Transactions on Broadcast and Television Receivers |date=July 1968 |volume=14 |issue=2 |pages=80–86 |doi=10.1109/TBTR1.1968.4320132}}</ref><ref name="Alvarez">{{cite book |last1=Alvarez |first1=Antonio R. |chapter=Introduction To BiCMOS |title=BiCMOS Technology and Applications |date=1990 |publisher=[[Springer Science & Business Media]] |doi=10.1007/978-1-4757-2029-7_1 |isbn=9780792393849 |pages=1–20 (2)}}</ref>
+|-
+|1968-10
+|?
+|?
+|[[BiCMOS]]
+|[[Hung-Chang Lin]], Ramachandra R. Iyer, C.T. Ho
+|Westinghouse Electric
+|<ref>{{cite article |last1=Lin |first1=Hung Chang |author1-link=Hung-Chang Lin |last2=Iyer |first2=Ramachandra R. |last3=Ho |first3=C. T. |title=Complementary MOS-bipolar structure |journal=1968 International Electron Devices Meeting |date=October 1968 |pages=22–24 |doi=10.1109/IEDM.1968.187949}}</ref><ref name="Alvarez"/>
+|-
+|1969
+|?
+|?
+|[[VMOS]]
+|?
+|[[Hitachi]]
+|<ref name="powerelectronics">{{cite article |title=Advances in Discrete Semiconductors March On |url=https://www.powerelectronics.com/content/advances-discrete-semiconductors-march |journal=Power Electronics Technology |publisher=[[Informa]] |pages=52–6 |access-date=31 July 2019 |date=September 2005 |archive-url=https://web.archive.org/web/20060322222716/http://powerelectronics.com/mag/509PET26.pdf |archive-date=22 March 2006 |url-status=live}}</ref><ref>{{cite book |last1=Oxner |first1=E. S. |title=Fet Technology and Application |date=1988 |publisher=[[CRC Press]] |isbn=9780824780500 |page=18 |url=https://books.google.com/books?id=0AE-0e-sAnsC&pg=PA18}}</ref>
+|-
+|1969-09
+|?
+|?
+|[[DMOS]]
+|Y. Tarui, Y. Hayashi, Toshihiro Sekigawa
+|[[Electrotechnical Laboratory]] (ETL)
+|<ref>{{cite article |last1=Tarui |first1=Y. |last2=Hayashi |first2=Y. |last3=Sekigawa |first3=Toshihiro |title=Diffusion Self-Aligned MOST; A New Approach for High Speed Device |journal=Proceedings of the 1st Conference on Solid State Devices |date=September 1969 |doi=10.7567/SSDM.1969.4-1 |s2cid=184290914 |url=https://www.semanticscholar.org/paper/Diffusion-Selfaligned-MOST%3B-A-New-Approach-for-High-Tarui-Hayashi/c4ad0fa7b03e080cc027545f7152caa28633fa9a}}</ref><ref>{{cite article |last1=McLintock |first1=G. A. |last2=Thomas |first2=R. E. |title=Modelling of the double-diffused MOST's with self-aligned gates |journal=1972 International Electron Devices Meeting |date=December 1972 |pages=24–26 |doi=10.1109/IEDM.1972.249241}}</ref>
+|-
+|1970-10
+|?
+|?
+|[[ISFET]]
+|[[Piet Bergveld]]
+|[[University of Twente]]
+|<ref name="Bergveld1970">{{cite article |last1=Bergveld |first1=P. |title=Development of an Ion-Sensitive Solid-State Device for Neurophysiological Measurements |journal=[[IEEE Transactions on Biomedical Engineering]] |date=January 1970 |volume=BME-17 |issue=1 |pages=70–71 |doi=10.1109/TBME.1970.4502688|pmid=5441220}}</ref><ref name="Toumazou">{{cite article|author=Chris Toumazou |author2=Pantelis Georgiou |url=https://www.researchgate.net/publication/260616066 |title=40 years of ISFET technology: From neuronal sensing to DNA sequencing |journal=[[Electronics Letters]] |date=December 2011 |doi=10.1049/el.2011.3231 |access-date=13 May 2016}}</ref>
+|-
+|1970-10
+|[[1 μm process|1000]]
+|?
+|DMOS
+|Y. Tarui, Y. Hayashi, Toshihiro Sekigawa
+|Electrotechnical Laboratory (ETL)
+|<ref>{{cite article |last1=Tarui |first1=Y. |last2=Hayashi |first2=Y. |last3=Sekigawa |first3=Toshihiro |title=DSA enhancement – Depletion MOS IC |journal=1970 International Electron Devices Meeting |date=October 1970 |pages=110 |doi=10.1109/IEDM.1970.188299}}</ref>
+|-
+|rowspan="2" | 1977
+|?
+|?
+|[[VDMOS]]
+|[[John Louis Moll]]
+|[[HP Labs]]
+|<ref name="powerelectronics"/>
+|-
+|?
+|?
+|[[LDMOS]]
+|?
+|Hitachi
+|<ref name="Duncan177">{{cite book |last1=Duncan |first1=Ben |title=High Performance Audio Power Amplifiers |date=1996 |publisher=[[Elsevier]] |isbn=9780080508047 |pages=[https://archive.org/details/highperfomanceau0000dunc/page/177 177–8, 406] |url=https://archive.org/details/highperfomanceau0000dunc/page/177}}</ref>
+|-
+|1979-07
+|?
+|?
+|[[IGBT]]
+|[[Bantval Jayant Baliga]], Margaret Lazeri
+|[[General Electric]]
+|<ref>{{cite book |last1=Baliga |first1=B. Jayant |title=The IGBT Device: Physics, Design and Applications of the Insulated Gate Bipolar Transistor |date=2015 |publisher=[[William Andrew (publisher)|William Andrew]] |isbn=9781455731534 |pages=xxviii, 5–12 |url=https://books.google.com/books?id=f091AgAAQBAJ}}</ref>
+|-
+|1984-12
+|[[3 μm process|2000]]
+|?
+|BiCMOS
+|H. Higuchi, Goro Kitsukawa, Takahide Ikeda, Y. Nishio
+|Hitachi
+|<ref>{{cite article |last1=Higuchi |first1=H. |last2=Kitsukawa |first2=Goro |last3=Ikeda |first3=Takahide |last4=Nishio |first4=Y. |last5=Sasaki |first5=N. |last6=Ogiue |first6=Katsumi |title=Performance and structures of scaled-down bipolar devices merged with CMOSFETs |journal=1984 International Electron Devices Meeting |date=December 1984 |pages=694–697 |doi=10.1109/IEDM.1984.190818|s2cid=41295752 }}</ref>
+|-
+|1985-05
+|[[350 nanometer|300]]
+|?
+|?
+|K. Deguchi, Kazuhiko Komatsu, M. Miyake, H. Namatsu
+|[[Nippon Telegraph and Telephone]]
+|<ref>{{cite article |last1=Deguchi |first1=K. |last2=Komatsu |first2=Kazuhiko |last3=Miyake |first3=M. |last4=Namatsu |first4=H. |last5=Sekimoto |first5=M. |last6=Hirata |first6=K. |title=Step-and-Repeat X-ray/Photo Hybrid Lithography for 0.3 μm Mos Devices |journal=1985 Symposium on VLSI Technology. Digest of Technical Papers |date=1985 |pages=74–75 |url=https://ieeexplore.ieee.org/document/4480310}}</ref>
+|-
+|1985-02
+|[[1 μm process|1000]]
+|?
+|BiCMOS
+|H. Momose, Hideki Shibata, S. Saitoh, Jun-ichi Miyamoto
+|Toshiba
+|<ref>{{cite article |last1=Momose |first1=H. |last2=Shibata |first2=Hideki |last3=Saitoh |first3=S. |last4=Miyamoto |first4=Jun-ichi |last5=Kanzaki |first5=K. |last6=Kohyama |first6=Susumu |title=1.0-/spl mu/m n-Well CMOS/Bipolar Technology |journal=[[IEEE Journal of Solid-State Circuits]] |date=1985 |volume=20 |issue=1 |pages=137–143 |doi=10.1109/JSSC.1985.1052286|bibcode=1985IJSSC..20..137M|s2cid=37353920 }}</ref>
+|-
+|1986-11
+|[[90 nm process|90]]
+|[[10 nanometer|8.3]]
+|?
+|Han-Sheng Lee, L.C. Puzio
+|[[General Motors]]
+|<ref>{{cite article |last1=Lee |first1=Han-Sheng |last2=Puzio |first2=L.C. |title=The electrical properties of subquarter-micrometer gate-length MOSFET's |journal=IEEE Electron Device Letters |date=November 1986 |volume=7 |issue=11 |pages=612–614 |doi=10.1109/EDL.1986.26492|bibcode=1986IEDL....7..612H|s2cid=35142126 }}</ref>
+|-
+|1987-09
+|?
+|[[10 nm|10]]
+|?
+|[[Hussein I. Hanafi]], Ting, Chung-Yu, Ahn, Kie Y.
+|IBM T.J. Watson Research Center
+|<ref name="Davari19872">{{cite article |last1=Davari |first1=Bijan |author1-link=Bijan Davari |last2=Ting |first2=Chung-Yu |last3=Ahn |first3=Kie Y. |last4=Basavaiah |first4=S. |last5=Hu |first5=Chao-Kun |last6=Taur |first6=Yuan |last7=Wordeman |first7=Matthew R. |last8=Aboelfotoh |first8=O. |last9=Krusin-Elbaum |first9=L. |last10=Joshi |first10=Rajiv V. |last11=Polcari |first11=Michael R. |title=Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide |journal=1987 Symposium on VLSI Technology. Digest of Technical Papers |date=1987 |pages=61–62 |url=https://ieeexplore.ieee.org/document/4480422}}</ref>
+|-
+|1987-12
+|[[800 nanometer|800]]
+|?
+|BiCMOS
+|Robert H. Havemann, R. E. Eklund, Hiep V. Tran
+|[[Texas Instruments]]
+|<ref>{{cite article |last1=Havemann |first1=Robert H. |last2=Eklund |first2=R. E. |last3=Tran |first3=Hiep V. |last4=Haken |first4=R. A. |last5=Scott |first5=D. B. |last6=Fung |first6=P. K. |last7=Ham |first7=T. E. |last8=Favreau |first8=D. P. |last9=Virkus |first9=R. L. |title=An 0.8 #181;m 256K BiCMOS SRAM technology |journal=1987 International Electron Devices Meeting |date=December 1987 |pages=841–843 |doi=10.1109/IEDM.1987.191564|s2cid=40375699 }}</ref>
+|-
+|1997-06
+|[[32 nanometer|30]]
+|?
+|EJ-MOSFET
+|Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba
+|[[NEC]]
+|<ref>{{cite article |last1=Kawaura |first1=Hisao |last2=Sakamoto |first2=Toshitsugu |last3=Baba |first3=Toshio |last4=Ochiai |first4=Yukinori |last5=Fujita |first5=Jun-ichi |last6=Matsui |first6=Shinji |last7=Sone |first7=J. |title=Transistor operations in 30-nm-gate-length EJ-MOSFETs |journal=1997 55th Annual Device Research Conference Digest |date=1997 |pages=14–15 |doi=10.1109/DRC.1997.612456|isbn=0-7803-3911-8|s2cid=38105606 }}</ref>
+|-
+|1998
+|[[32 nm|32]]
+|rowspan="2" | ?
+|rowspan="2" | ?
+|rowspan="2" | ?
+|rowspan="2" | NEC
+|rowspan="2" | <ref name="Schwierz"/>
+|-
+|1999
+|[[8 nanometer|8]]
+|-
+|2000-04
+|8
+|?
+|EJ-MOSFET
+|Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba
+|NEC
+|<ref>{{cite article |last1=Kawaura |first1=Hisao |last2=Sakamoto |first2=Toshitsugu |last3=Baba |first3=Toshio |title=Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal–oxide–semiconductor field-effect transistors |journal=[[Applied Physics Letters]] |date=12 June 2000 |volume=76 |issue=25 |pages=3810–3812 |doi=10.1063/1.126789 |bibcode=2000ApPhL..76.3810K |issn=0003-6951}}</ref>
+|}
 ==See also==
-* [[Field-effect transistor]]
+* [[field-effect transistor|Field-effect transistor]]
 * [[CMOS]]
 * [[pMOS logic]]
 * [[nMOS logic]]
+* [[BSIM]]
+* [[ggNMOS]]
+* [[High electron mobility transistor]]
+* [[Polysilicon depletion effect]]
+* [[Power MOSFET]]
+* [[Quantum Hall effect]]
+* [[Transistor model]]
+== References ==
+{{reflist}}
-==References==
+== External links ==
-{{Reflist}}
+* [https://www.wecanfigurethisout.org/VL/MOS_kit.htm How Semiconductors and Transistors Work (MOSFETs)] WeCanFigureThisOut.org
+* {{cite article|url=http://assets.nexperia.com/documents/application-note/AN11158.pdf|title=Understanding power MOSFET data sheet parameters – Nexperia PDF Application Note AN11158}}
+* {{cite article|archive-url=https://web.archive.org/web/20080928200323/http://www.automotivedesignline.com/showArticle.jhtml%3B?articleID=191900470|url=http://www.automotivedesignline.com/showArticle.jhtml%3B?articleID=191900470|archive-date=28 September 2008|title= An introduction to depletion-mode MOSFETs}}
+* {{cite article|url=http://www.alpha-europe.de/microelectronics-products/dmos-transistors/|title=Power MOSFETs|access-date=2010-03-04|archive-date=2012-07-06|archive-url=https://web.archive.org/web/20120706010707/http://www.alpha-europe.de/microelectronics-products/dmos-transistors/|url-status=dead}}
+* {{cite article|url=http://www.powerguru.org/2012/04/15/criteria-for-a-successful-selection-of-igbt-and-mosfet-modules/|title=Criteria for Successful Selection of IGBT and MOSFET Modules|access-date=2018-12-16|archive-url=https://web.archive.org/web/20121112152008/http://www.powerguru.org/2012/04/15/criteria-for-a-successful-selection-of-igbt-and-mosfet-modules/|archive-date=2012-11-12|url-status=dead}}
+* {{cite article|url=http://www.ece.byu.edu/cleanroom/virtual_cleanroom.parts/MOSFETProcess.html|title=MOSFET Process Step by Step|access-date=2016-02-06|archive-url=https://web.archive.org/web/20090822214640/http://www.ece.byu.edu/cleanroom/virtual_cleanroom.parts/MOSFETProcess.html|archive-date=2009-08-22|url-status=dead}} A Flash slide showing the fabricating process of a MOSFET in detail
+* {{cite article|url=http://www.ece.byu.edu/cleanroom/MOSFET_calc.phtml|title=MOSFET Calculator|access-date=2008-06-03|archive-url=https://web.archive.org/web/20080527192452/http://www.ece.byu.edu/cleanroom/MOSFET_calc.phtml|archive-date=2008-05-27|url-status=dead}}
+* {{cite article|url=http://ecee.colorado.edu/~bart/book/book/chapter7/ch7_7.htm#7_7_7|title=Advanced MOSFET issues|website=ecee.{{not a typo|colorado}}.edu|date=27 November 2010|access-date=6 April 2012|archive-date=15 June 2012|archive-url=https://web.archive.org/web/20120615140603/http://ecee.colorado.edu/~bart/book/book/chapter7/ch7_7.htm#7_7_7|url-status=dead}}
+* {{cite article|url=http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/mosfet.html|title=MOSFET applet}}
+* {{cite book|first1=Ulrich|last1=Nicolai|first2=Tobias|last2=Reimann|first3=Jürgen|last3=Petzoldt|first4=Josef|last4=Lutz|title=Application Manual IGBT and MOSFET Power Modules|edition=1st|publisher=ISLE Verlag|date=1998|isbn=978-3-932633-24-9|archive-url=https://web.archive.org/web/20120302072616/http://www.semikron.com/skcompub/en/application_manual-193.htm|url=http://www.semikron.com/skcompub/en/application_manual-193.htm|archive-date=2 March 2012}}
+* {{cite book|last1=Wintrich |first1=Arendt |last2=Nicolai |first2=Ulrich |last3=Tursky |first3=Werner |last4=Reimann |first4=Tobias |title=PDF-Version |url=http://www.powerguru.org/wordpress/wp-content/uploads/2012/12/SEMIKRON_application_manual_power_semiconductors.pdf |edition=2nd |year=2011 |publisher=Semikron |location=Nuremberg |isbn=978-3-938843-66-6 |url-status=dead |archive-url=https://web.archive.org/web/20130903030232/http://www.powerguru.org/wordpress/wp-content/uploads/2012/12/SEMIKRON_application_manual_power_semiconductors.pdf |archive-date=3 September 2013 }}
+* {{cite article|url=http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-002Spring-2007/CourseHome/index.htm|title=MIT Open Courseware 6.002&nbsp;– Spring 2007|access-date=2009-04-04|archive-date=2010-05-05|archive-url=https://web.archive.org/web/20100505172424/http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-002Spring-2007/CourseHome/index.htm|url-status=dead}}
+* {{cite article|url=http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-012-microelectronic-devices-and-circuits-fall-2009/|title=MIT Open Courseware 6.012&nbsp;– Fall 2009}}
+* {{cite article|url=http://users.ece.gatech.edu/~alan/index_files/ECE3040Lecture.htm|title=Georgia Tech BJT and FET Slides}}
+* {{cite article|url=http://www.circuitdesign.info/blog/2008/12/mos-diffusion-parasitics/|title=CircuitDesign: MOS Diffusion Parasitics}}
+* {{cite article|url=http://nanohub.org/resources/5306|title=Course on ''Physics of Nanoscale Transistors''|year=2008|last1=Mark Lundstrom|first1=Mark Lundstrom|access-date=2010-05-09|archive-url=https://web.archive.org/web/20120224215529/http://nanohub.org/resources/5306|archive-date=2012-02-24|url-status=dead}}
+* {{cite article|url=http://nanohub.org/resources/489|title=Notes on Ballistic MOSFETs|author=Dr. Lundstrom|year=2005|access-date=2010-05-18|archive-url=https://web.archive.org/web/20120224220310/http://nanohub.org/resources/489|archive-date=2012-02-24|url-status=dead}}
 [[Category:MOSFET]]
+[[Category:MOSFETs| ]]
+[[Category:1959 introductions]]
+[[Category:1960 introductions]]
+[[Category:20th-century inventions]]
+[[Category:Arab inventions]]
+[[Category:Digital electronics]]
+[[Category:Egyptian inventions]]
+[[Category:Integrated circuits]]
+[[Category:South Korean inventions]]
+[[Category:Transistor amplifiers]]
+[[Category:Transistor types]]

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Latest revision as of 18:01, 6 September 2024

Contents

Overview[edit]

Process[edit]

Controlling Gate[edit]

nMOS gate behavior[edit]

pMOS gate behavior[edit]

Modes of operation[edit]

Symbols[edit]

Early history[edit]

Background[edit]

Invention[edit]

Commercialization[edit]

MOS revolution[edit]

Importance[edit]

Types of MOSFET[edit]

PMOS and NMOS logic[edit]

Complementary MOS (CMOS)[edit]

Depletion-mode[edit]

Metal–insulator–semiconductor FET (MISFET)[edit]

Floating-gate MOSFET (FGMOS)[edit]

Power MOSFET[edit]

Double-diffused MOS (DMOS)[edit]

MOS capacitor[edit]

Thin-film transistor (TFT)[edit]

Bipolar–MOS transistors[edit]

MOS sensors[edit]

Multi-gate MOSFET (MuGFET)[edit]

Quantum field-effect transistor (QFET)[edit]

Radiation-hardened-by-design (RHBD)[edit]

Applications[edit]

MOS integrated circuit (MOS IC)[edit]

MOS large-scale integration (MOS LSI)[edit]

Microprocessors[edit]

CMOS circuits[edit]

Digital[edit]

Analog[edit]

MOS memory[edit]

Consumer electronics[edit]

MOS sensors[edit]

Power MOSFETs[edit]

Scaling[edit]

Timeline[edit]

PMOS and NMOS[edit]

CMOS (single-gate)[edit]

Multi-gate MOSFET (MuGFET)[edit]

Other types of MOSFET[edit]

See also[edit]

References[edit]

External links[edit]