(→Integrated graphics) |
(→Die) |
||
Line 163: | Line 163: | ||
:[[File:ice lake die sa (annotated).png|700px]] | :[[File:ice lake die sa (annotated).png|700px]] | ||
+ | == Die == | ||
=== Core === | === Core === | ||
+ | {{see also|intel/microarchitectures/sunny_cove#Die|l1=Sunny Cove § Die}} | ||
+ | * ~6.91 mm² die size | ||
+ | ** ~3.5 mm x ~1.97 mm | ||
+ | |||
:[[File:ice lake die core.png|400px]] | :[[File:ice lake die core.png|400px]] | ||
Line 170: | Line 175: | ||
=== Core group === | === Core group === | ||
+ | {{see also|intel/microarchitectures/sunny_cove#Die|l1=Sunny Cove § Die}} | ||
+ | * ~30.73 mm² die size | ||
+ | ** ~7.86 mm x ~3.91 mm | ||
+ | |||
+ | |||
:[[File:ice lake die core group.png|700px]] | :[[File:ice lake die core group.png|700px]] | ||
:[[File:ice lake die core group (annotated).png|700px]] | :[[File:ice lake die core group (annotated).png|700px]] | ||
+ | |||
=== Integrated graphics === | === Integrated graphics === |
Revision as of 14:13, 28 May 2019
Edit Values | |
Ice Lake (client) µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | 2019 |
Process | 10 nm |
Instructions | |
ISA | x86-64 |
Cache | |
L1I Cache | 32 KiB/core 8-way set associative |
L1D Cache | 48 KiB/core 12-way set associative |
L2 Cache | 512 KiB/512 KiB 12-way set associative |
L3 Cache | 2 MiB/core 16-way set associative |
Cores | |
Core Names | Ice Lake Y, Ice Lake U |
Succession | |
Contemporary | |
Ice Lake (server) |
Ice Lake (ICL) Client Configuration is Intel's successor to Cannon Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.
Contents
Codenames
Core | Abbrev | Description | Graphics | Target |
---|---|---|---|---|
Ice Lake Y | ICL-Y | Extremely low power | 2-in-1s detachable, tablets, and computer sticks | |
Ice Lake U | ICL-U | Ultra-low Power | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | |
Ice Lake H | ICL-H | High-performance Graphics | Ultimate mobile performance, mobile workstations | |
|
|
|
|
Process Technology
- See also: Cannon Lake § Process Technology
Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.
Compiler support
Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.
Compiler | Arch-Specific | Arch-Favorable |
---|---|---|
ICC | -march=icelake |
-mtune=icelake
|
GCC | -march=icelake |
-mtune=icelake
|
LLVM | -march=icelake |
-mtune=icelake
|
Visual Studio | /? |
/tune:?
|
CPUID
Core | Extended Family |
Family | Extended Model |
Model |
---|---|---|---|---|
U, Y | 0 | 0x6 | 0x7 | 0xE |
Family 6 Model 126 | ||||
? | 0 | 0x6 | ? | ? |
Family 6 Model ? |
Architecture
Ice Lake comprises of Sunny Cove cores on the ring interconnect architecture along with Gen11 GPU, and an improved System Agent with a new display engine and I/O.
Key changes from Cannon Lake/Skylake
- Enhanced "10nm+" (from "10nm", 2nd gen)
- Core
- Sunny Cove core (from Palm Cove)
- See Sunny Cove for microarchitectural details and changes
- Sunny Cove core (from Palm Cove)
- Memory
- Graphics
- Display
- Gen 11.5 (from Gen9/Gen9.5)
- DisplayPort 1.4a with Display Stream Compression(DSC) (from DisplayPort 1.2)
- HDMI 2.0 (from HDMI 1.4)
- IPU
- 4th Gen IPU (from 3rd Gen in Skylake)
- More cameras support
- New concurrent image pipeline
- on-die MIPI interface
- I/O
- Thunderbolt 3 over Type-C
This list is incomplete; you can help by expanding it.
New instructions
Ice Lake introduced a number of new instructions. See Sunny Cove § New Instructions for details.
Block Diagram
Entire SoC Overview
Individual Core
See Sunny Cove § Block Diagram.
Gen11 Graphics
See Gen11 Graphics § Block Diagram.
Overview
![]() |
This section is empty; you can help add the missing info by editing this page. |
Core
![]() |
This section is empty; you can help add the missing info by editing this page. |
IPU
Ice Lake incorporates 4th generation image processing unit (IPU). The IPU was first introduced with Skylake mobile SoCs (note that those were 3rd gen). The 4th Gen IPU found in Ice Lake introduces a number of new enhancements. It introduces new support for 4K video capture at 30fps. There is also new hardware support for better de-noising which supports up to 16 megapixels stills in low light conditions. In addition for support more camera simultaneously, the IPU incorporates a new concurrent image pipeline, supporting multiple different processing from the same camera stream, allowing a single camera to take the functionality of multiple sensors. A common example of that is devices with both IR and RGB cameras in the laptop bezel which can now be changed to a single camera. Intel says they are exposing more registers from the IPU to software in order to provide more flexibility for applications that make use of that for machine learning. It’s also worth noting that Intel integrated the MIPI interface onto the processor as well. Previously that was found on the chipset. The change significantly improves the latency, a required attribute needed for more advanced ML-specific applications. Some of those changes are designed to form the foundation for future generations of improvements.
Clock domains
Ice Lake is divided into a number of clock domains, each controlling the clock frequency of their respective unit in the processor. All clock domains are some multiple of the [virtual] bus clock (BCLK).
- BCLK - Bus/Base Clock - The system bus interface frequency (once upon a time referred to the actual FSB speed, it now serves as only a base clock reference for all other clock domains). The base clock is 100 MHz.
- Core Clock - The frequency at which the core and the L1/L2 caches operate at. (Frequency depends on the model and is represented as a multiple of BCLK).
- Ring Clock - The frequency at which the ring interconnect and LLC operate at. Data from/to the individual cores are read/written into the L3 at a rate of 32B/cycle operating at Ring Clock frequency.
- IGP Clock - The frequency at which the integrated graphics (Gen11 GPU) operates at. Data from/to the GPU are read/written into the LLC at a rate of 64B/cycle operating at this frequency as well.
- IPU - The frequency at which the image processing unit operates at
- MemClk - Memory Clock - The frequency at which the system DRAM operates at. DRAM data is transferred at a rate of 8B/cycle operating at MemClk frequency.
Die
System Agent
- System Agent
- 4th Gen IPU
- Gen11 Display
- Thunderbolt 3 over Type-C
- PCIe
Die
Core
- See also: Sunny Cove § Die
- ~6.91 mm² die size
- ~3.5 mm x ~1.97 mm
Core group
- See also: Sunny Cove § Die
- ~30.73 mm² die size
- ~7.86 mm x ~3.91 mm
Integrated graphics
- Gen11 GPU
- 64 EUs
- ~41.1 mm² silicon area
- ~5.22 mm x ~7.86 mm
SoC
- 10 nm process
- ~122.52 mm² die size
- ~11.44 mm x ~10.71 mm
- 4 Sunny Cove big cores
- 64-EU Gen11 GPU
- 4th Gen IPU
All Ice Lake Chips
List of Ice Lake-based Processors | ||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Main processor | Turbo Boost | Memory | GPU | Features | ||||||||||||||||
Model | Launched | Price | Family | Platform | Core | Cores | Threads | L3$ | TDP | Base | 1 Core | 2 Cores | 4 Cores | 6 Cores | Max Memory | Name | Base | Burst | TBT | HT |
Count: 0 |
Bibliography
- Intel 2018 Architecture Day.
- Intel. personal communication. 2019.
codename | Ice Lake (client) + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/ice lake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (client) + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |