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− | {{intel title| | + | {{intel title|Ice Lake (client)|arch}} |
{{microarchitecture | {{microarchitecture | ||
− | | atype | + | |atype=CPU |
− | | name | + | |name=Ice Lake (client) |
− | | designer | + | |designer=Intel |
− | | manufacturer | + | |manufacturer=Intel |
− | | introduction | + | |introduction=2019 |
− | | | + | |process=10 nm |
− | | | + | |isa=x86-64 |
+ | |l1i=32 KiB | ||
+ | |l1i per=core | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d=48 KiB | ||
+ | |l1d per=core | ||
+ | |l1d desc=12-way set associative | ||
+ | |l1 per=core | ||
+ | |l2=512 KiB | ||
+ | |l2 per=512 KiB | ||
+ | |l2 desc=12-way set associative | ||
+ | |l3=2 MiB | ||
+ | |l3 per=core | ||
+ | |l3 desc=16-way set associative | ||
+ | |core name=Ice Lake Y | ||
+ | |core name 2=Ice Lake U | ||
+ | |predecessor=Cannon Lake | ||
+ | |predecessor link=intel/microarchitectures/cannon lake | ||
+ | |successor=Tiger Lake | ||
+ | |successor link=intel/microarchitectures/tiger lake | ||
+ | |contemporary=Ice Lake (server) | ||
+ | |contemporary link=intel/microarchitectures/ice_lake_(server) | ||
+ | }} | ||
+ | '''Ice Lake''' ('''ICL''') '''Client Configuration''' is [[Intel]]'s successor to {{\\|Cannon Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. | ||
− | | | + | == Codenames == |
− | | | + | {| class="wikitable" |
− | | | + | |- |
− | | | + | ! Core !! Abbrev !! Description !! Graphics !! Target |
− | | | + | |- |
− | }} | + | | {{intel|Ice Lake Y|l=core}} || ICL-Y || Extremely low power || || 2-in-1s detachable, tablets, and computer sticks |
− | + | |- | |
+ | | {{intel|Ice Lake U|l=core}} || ICL-U || Ultra-low Power || || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | ||
+ | |- | ||
+ | | {{intel|Ice Lake H|l=core}} || ICL-H || High-performance Graphics || || Ultimate mobile performance, mobile workstations | ||
+ | |- | ||
+ | | <s>{{intel|Ice Lake S|l=core}}</s>? || <s>ICL-S</s> || <s>Performance-optimized lifestyle</s> || || <s>Desktop performance to value, AiOs, and minis</s> | ||
+ | |} | ||
== Process Technology== | == Process Technology== | ||
− | {{ | + | {{see also|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}} |
− | + | Ice Lake will use a second-generation enhanced [[10 nm process]] called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope. | |
+ | |||
+ | [[File:intels 10+ and 10++.png|750px]] | ||
+ | |||
+ | {{clear}} | ||
+ | |||
+ | == Compiler support == | ||
+ | Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0. | ||
+ | {| class="wikitable" | ||
+ | |- | ||
+ | ! Compiler !! Arch-Specific || Arch-Favorable | ||
+ | |- | ||
+ | | [[ICC]] || <code>-march=icelake</code> || <code>-mtune=icelake</code> | ||
+ | |- | ||
+ | | [[GCC]] || <code>-march=icelake</code> || <code>-mtune=icelake</code> | ||
+ | |- | ||
+ | | [[LLVM]] || <code>-march=icelake</code> || <code>-mtune=icelake</code> | ||
+ | |- | ||
+ | | [[Visual Studio]] || <code>/?</code> || <code>/tune:?</code> | ||
+ | |} | ||
+ | |||
+ | === CPUID === | ||
+ | {| class="wikitable tc1 tc2 tc3 tc4" | ||
+ | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ||
+ | |- | ||
+ | | rowspan="2" | {{intel|Ice Lake U|U|l=core}}, {{intel|Ice Lake Y|Y|l=core}} || 0 || 0x6 || 0x7 || 0xE | ||
+ | |- | ||
+ | | colspan="4" | Family 6 Model 126 | ||
+ | |- | ||
+ | | rowspan="2" | ? || 0 || 0x6 || ? || ? | ||
+ | |- | ||
+ | | colspan="4" | Family 6 Model ? | ||
+ | |} | ||
== Architecture == | == Architecture == | ||
Not much is known about Ice Lake's architecture. | Not much is known about Ice Lake's architecture. | ||
− | === Key changes from {{\\| | + | === Key changes from {{\\|Cannon Lake}}=== |
+ | * Enhanced "10nm+" (from "10nm", 2nd gen) | ||
+ | * {{\\|Sunny Cove|Sunny Cove core}} (from {{\\|Palm Cove}}) | ||
+ | ** ''See {{\\|Sunny Cove}} for microarchitectural details and changes'' | ||
+ | * {{intel|Gen10|l=arch}} → {{intel|Gen11|l=arch}} graphics | ||
+ | * {{intel|Gen11|l=arch}} GPUs | ||
+ | ** UHD Graphics 7xx (GT1) '''→''' UHD Graphics 8xx (GT1) (32 Execution Units, 1.3x EUs from {{\\|Cannon Lake}}) | ||
+ | ** UHD Graphics 7xx (GT2) '''→''' UHD Graphics 8xx (Gt2) (64 Execution Units, 1.6x EUs from {{\\|Cannon Lake}}) | ||
+ | * Display | ||
+ | ** DisplayPort 1.4a with Display Stream Compression(DSC) (from DisplayPort 1.2) | ||
+ | ** HDMI 2.0 (from HDMI 1.4) | ||
+ | |||
+ | {{expand list}} | ||
+ | |||
+ | ====New instructions ==== | ||
+ | Ice Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|Sunny cove#New instructions|Sunny Cove § New Instructions|l=arch}} for details. | ||
+ | |||
+ | === Block Diagram === | ||
+ | |||
+ | ==== Entire SoC Overview ==== | ||
+ | [[File:ice lake soc block diagram.svg|900px]] | ||
+ | |||
+ | ==== Individual Core ==== | ||
+ | See {{intel|Sunny Cove#Block Diagram|Sunny Cove § Block Diagram|l=arch}}. | ||
+ | |||
+ | ==== Gen11 Graphics ==== | ||
+ | See {{intel|Gen11#Block Diagram|Gen11 Graphics § Block Diagram|l=arch}}. | ||
+ | |||
+ | == All Ice Lake Chips == | ||
{{future information}} | {{future information}} | ||
− | + | <!-- NOTE: | |
+ | This table is generated automatically from the data in the actual articles. | ||
+ | If a microprocessor is missing from the list, an appropriate article for it needs to be | ||
+ | created and tagged accordingly. | ||
+ | |||
+ | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips | ||
+ | --> | ||
+ | {{comp table start}} | ||
+ | <table class="comptable sortable tc7 tc8 tc20 tc21"> | ||
+ | {{comp table header|main|20:List of Ice Lake-based Processors}} | ||
+ | {{comp table header|main|10:Main processor|4:{{intel|Turbo Boost}}|Memory|3:GPU|2:Features}} | ||
+ | {{comp table header|cols|Launched|Price|Family|Platform|Core|Cores|Threads|L3$|TDP|Base|1 Core|2 Cores|4 Cores|6 Cores|Max Memory|Name|Base|Burst|{{intel|TBT}}|{{intel|Hyper-Threading|HT}}}} | ||
+ | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Ice Lake]] | ||
+ | |?full page name | ||
+ | |?model number | ||
+ | |?first launched | ||
+ | |?release price | ||
+ | |?microprocessor family | ||
+ | |?platform | ||
+ | |?core name | ||
+ | |?core count | ||
+ | |?thread count | ||
+ | |?l3$ size | ||
+ | |?tdp | ||
+ | |?base frequency#GHz | ||
+ | |?turbo frequency (1 core)#GHz | ||
+ | |?turbo frequency (2 cores)#GHz | ||
+ | |?turbo frequency (4 cores)#GHz | ||
+ | |?turbo frequency (6 cores)#GHz | ||
+ | |?max memory#GiB | ||
+ | |?integrated gpu | ||
+ | |?integrated gpu base frequency | ||
+ | |?integrated gpu max frequency | ||
+ | |?has intel turbo boost technology 2_0 | ||
+ | |?has simultaneous multithreading | ||
+ | |format=template | ||
+ | |template=proc table 3 | ||
+ | |userparam=21 | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Ice Lake]]}} | ||
+ | </table> | ||
+ | {{comp table end}} |
Revision as of 21:24, 29 January 2019
Edit Values | |
Ice Lake (client) µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | 2019 |
Process | 10 nm |
Instructions | |
ISA | x86-64 |
Cache | |
L1I Cache | 32 KiB/core 8-way set associative |
L1D Cache | 48 KiB/core 12-way set associative |
L2 Cache | 512 KiB/512 KiB 12-way set associative |
L3 Cache | 2 MiB/core 16-way set associative |
Cores | |
Core Names | Ice Lake Y, Ice Lake U |
Succession | |
Contemporary | |
Ice Lake (server) |
Ice Lake (ICL) Client Configuration is Intel's successor to Cannon Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.
Contents
Codenames
Core | Abbrev | Description | Graphics | Target |
---|---|---|---|---|
Ice Lake Y | ICL-Y | Extremely low power | 2-in-1s detachable, tablets, and computer sticks | |
Ice Lake U | ICL-U | Ultra-low Power | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | |
Ice Lake H | ICL-H | High-performance Graphics | Ultimate mobile performance, mobile workstations | |
|
|
|
|
Process Technology
- See also: Cannon Lake § Process Technology
Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.
Compiler support
Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.
Compiler | Arch-Specific | Arch-Favorable |
---|---|---|
ICC | -march=icelake |
-mtune=icelake
|
GCC | -march=icelake |
-mtune=icelake
|
LLVM | -march=icelake |
-mtune=icelake
|
Visual Studio | /? |
/tune:?
|
CPUID
Core | Extended Family |
Family | Extended Model |
Model |
---|---|---|---|---|
U, Y | 0 | 0x6 | 0x7 | 0xE |
Family 6 Model 126 | ||||
? | 0 | 0x6 | ? | ? |
Family 6 Model ? |
Architecture
Not much is known about Ice Lake's architecture.
Key changes from Cannon Lake
- Enhanced "10nm+" (from "10nm", 2nd gen)
- Sunny Cove core (from Palm Cove)
- See Sunny Cove for microarchitectural details and changes
- Gen10 → Gen11 graphics
- Gen11 GPUs
- UHD Graphics 7xx (GT1) → UHD Graphics 8xx (GT1) (32 Execution Units, 1.3x EUs from Cannon Lake)
- UHD Graphics 7xx (GT2) → UHD Graphics 8xx (Gt2) (64 Execution Units, 1.6x EUs from Cannon Lake)
- Display
- DisplayPort 1.4a with Display Stream Compression(DSC) (from DisplayPort 1.2)
- HDMI 2.0 (from HDMI 1.4)
This list is incomplete; you can help by expanding it.
New instructions
Ice Lake introduced a number of new instructions. See Sunny Cove § New Instructions for details.
Block Diagram
Entire SoC Overview
Individual Core
See Sunny Cove § Block Diagram.
Gen11 Graphics
See Gen11 Graphics § Block Diagram.
All Ice Lake Chips
List of Ice Lake-based Processors | ||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Main processor | Turbo Boost | Memory | GPU | Features | ||||||||||||||||
Model | Launched | Price | Family | Platform | Core | Cores | Threads | L3$ | TDP | Base | 1 Core | 2 Cores | 4 Cores | 6 Cores | Max Memory | Name | Base | Burst | TBT | HT |
Count: 0 |
Facts about "Ice Lake (client) - Microarchitectures - Intel"
codename | Ice Lake (client) + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/ice lake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (client) + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |