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Difference between revisions of "intel/microarchitectures/ice lake (client)"
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Revision as of 12:08, 9 January 2019
| Edit Values | |
| Ice Lake (client) µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Cache | |
| L1I Cache | 32 KiB/core 8-way set assosiative |
| L1D Cache | 48 KiB/core |
| Cores | |
| Core Names | Ice Lake S |
| Succession | |
| Contemporary | |
| Ice Lake (server) | |
Ice Lake (ICL) Client Configuration is Intel's successor to Cannon Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.
Contents
Codenames
| Core | Abbrev | Description | Graphics | Target |
|---|---|---|---|---|
| Ice Lake Y | ICL-Y | Extremely low power | 2-in-1s detachable, tablets, and computer sticks | |
| Ice Lake U | ICL-U | Ultra-low Power | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | |
| Ice Lake H | ICL-H | High-performance Graphics | Ultimate mobile performance, mobile workstations | |
| Ice Lake S | ICL-S | Performance-optimized lifestyle | Desktop performance to value, AiOs, and minis | |
| Ice Lake X | ICL-X | Extreme Performance | High-end desktops & enthusiasts market | |
| Ice Lake DT | ICL-DT | Workstation | Workstations & entry-level servers |
Process Technology
- See also: Cannon Lake § Process Technology
Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.
Compiler support
Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| ICC | -march=icelake |
-mtune=icelake
|
| GCC | -march=icelake |
-mtune=icelake
|
| LLVM | -march=icelake |
-mtune=icelake
|
| Visual Studio | /? |
/tune:?
|
CPUID
| Core | Extended Family |
Family | Extended Model |
Model |
|---|---|---|---|---|
| U, Y | 0 | 0x6 | 0x7 | 0xE |
| Family 6 Model 126 | ||||
| ? | 0 | 0x6 | ? | ? |
| Family 6 Model ? | ||||
Architecture
Not much is known about Ice Lake's architecture.
Key changes from Cannon Lake
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
- Enhanced "10nm+" (from "10nm", 2nd gen)
- Gen10 → Gen11 graphics
- Gen11 GPUs
- UHD Graphics 710 → UHD Graphics 810 (32 Execution Units, 1.3x EUs from Cannon Lake)
- UHD Graphics 715 → UHD Graphics 815 (64 Execution Units, 1.6x EUs from Cannon Lake)
- UHD Graphics 720 → UHD Graphics 820 (64 Execution Units, 1.6x EUs from Cannon Lake)
- UHD Graphics 730 → UHD Graphics 830 (64 Execution Units, 1.6x EUs from Cannon Lake)
- UHD Graphics P730 → UHD Graphics P830 (64 Execution Units, 1.6x EUs from Cannon Lake)
- Display
- DisplayPort 1.4a with Display Stream Compression(DSC) (from DisplayPort 1.2)
- HDMI 2.0 (from HDMI 1.4)
New instructions
Ice Lake introduced a number of new instructions:
-
CLWB- Force cache line write-back without flush -
RDPID- Read Processor ID - Additional AVX-512 extensions:
-
AVX512VPOPCNTDQ- AVX-512 Vector Population Count Doubleword and Quadword -
AVX512VNNI- AVX-512 Vector Neural Network Instructions -
AVX512GFNI- AVX-512 Galois Field New Instructions -
AVX512VAES- AVX-512 Vector AES -
AVX512VBMI2- AVX-512 Vector Bit Manipulation, Version 2 -
AVX512BITALG- AVX-512 Bit Algorithms -
AVX512VPCLMULQDQ- AVX-512 Vector Vector Carry-less Multiply
-
-
SSE_GFNI- SSE-based Galois Field New Instructions -
AVX_GFNI- AVX-based Galois Field New Instructions - Split Lock Detection - detection and cause an exception for split locks
- Fast Short REP MOV
All Ice Lake Chips
| |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| List of Ice Lake-based Processors | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Main processor | Turbo Boost | Memory | GPU | Features | ||||||||||||||||
| Model | Launched | Price | Family | Platform | Core | Cores | Threads | L3$ | TDP | Base | 1 Core | 2 Cores | 4 Cores | 6 Cores | Max Memory | Name | Base | Burst | TBT | HT |
| Count: 0 | ||||||||||||||||||||
Facts about "Ice Lake (client) - Microarchitectures - Intel"
| codename | Ice Lake (client) + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/ice lake (client) + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Ice Lake (client) + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |