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Difference between revisions of "intel/microarchitectures/ice lake (client)"
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Revision as of 10:03, 8 December 2018

Edit Values
Ice Lake (client) µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2018
Process10 nm
Instructions
ISAx86-64
Cores
Core NamesIce Lake S
Succession
Contemporary
Ice Lake (server)

Ice Lake (ICL) Client Configuration is Intel's successor to Cannon Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.

Codenames

Core Abbrev Description Graphics Target
Ice Lake Y ICL-Y Extremely low power 2-in-1s detachable, tablets, and computer sticks
Ice Lake U ICL-U Ultra-low Power Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Ice Lake H ICL-H High-performance Graphics Ultimate mobile performance, mobile workstations
Ice Lake S ICL-S Performance-optimized lifestyle Desktop performance to value, AiOs, and minis
Ice Lake X ICL-X Extreme Performance High-end desktops & enthusiasts market
Ice Lake DT ICL-DT Workstation Workstations & entry-level servers

Process Technology

See also: Cannon Lake § Process Technology

Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

intels 10+ and 10++.png

Compiler support

Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=icelake -mtune=icelake
GCC -march=icelake -mtune=icelake
LLVM -march=icelake -mtune=icelake
Visual Studio /? /tune:?

CPUID

Core Extended
Family 		Family Extended
Model 		Model
U, Y 0 0x6 0x7 0xE
Family 6 Model 126
 ? 0 0x6  ?  ?
Family 6 Model ?

Architecture

Not much is known about Ice Lake's architecture.

Key changes from Cannon Lake

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

New instructions

Ice Lake introduced a number of new instructions:

  • CLWB - Force cache line write-back without flush
  • RDPID - Read Processor ID
  • Additional AVX-512 extensions:
  • SSE_GFNI - SSE-based Galois Field New Instructions
  • AVX_GFNI - AVX-based Galois Field New Instructions
  • Split Lock Detection - detection and cause an exception for split locks
  • Fast Short REP MOV

All Ice Lake Chips

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
 List of Ice Lake-based Processors
 Main processorTurbo BoostMemoryGPUFeatures
ModelLaunchedPriceFamilyPlatformCoreCoresThreadsL3$TDPBase1 Core2 Cores4 Cores6 CoresMax MemoryNameBaseBurstTBTHT
Count: 0
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Facts about "Ice Lake (client) - Microarchitectures - Intel"
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codenameIce Lake (client) +
designerIntel +
first launched2018 +
full page nameintel/microarchitectures/ice lake (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIce Lake (client) +
process10 nm (0.01 μm, 1.0e-5 mm) +