Difference between revisions of "amd/epyc embedded"

Latest revision as of 16:17, 27 December 2025

AMD EPYC Embedded

EPYC Embedded logo
Developer	AMD
Manufacturer	GlobalFoundries
Type	System on chips
Introduction	February 22, 2018 (announced) February 22, 2018 (launch)
Architecture	Embedded x86 SoCs
ISA	x86-64
µarch	Zen
Word size	64 bit 8 octets 16 nibbles
Process	14 nm 0.014 μm 1.4e-5 mm
Technology	CMOS
Clock	1,500 MHz-2,700 MHz
Socket	Socket SP4, Socket SP4r2
Succession
←
Opteron

EPYC Embedded is a family of 64-bit multi-core x86 embedded microprocessors designed and introduced by AMD. Those processors are primarily aimed at networking, storage, and edge computing devices. EPYC Embedded effectively succeeded the Opteron A1100 series of embedded microprocessors (although those were actually based on ARM, not x86).

Overview[edit]

The EPYC Embedded family is a low-power variant of the EPYC line that primarily marketed towards embedded devices such as networking, storage, and edge computing devices. Those parts have lower TDPs and come in a much smaller package allowing for denser integration.

AMD EPYC CPU Generations[edit]

AMD EPYC CPU Generations
Gen	Year	Codename	Product line	Cores	Socket	Memory
Server
1st	2017	Naples	7001 series	32× Zen	Socket SP3 (LGA)	DDR4
2nd	2019	Rome	7002 series	64× Zen 2
3rd	2021	Milan	7003 series	64× Zen 3
3rd	2022	Milan-X	7004 series	64× Zen 3
4th	2022	Genoa	9004 series	96× Zen 4	Socket SP5 (LGA)	DDR5
	2023	Genoa-X		96× Zen 4
		Bergamo		128× Zen 4c
		Siena	8004 series	64× Zen 4c	Socket SP6 (LGA)
	2024	Raphael-X	4004 series	16× Zen 4	Socket AM5 (LGA)
5th	2024	Turin (-X)	9005 series	128× Zen 5	Socket SP5 (LGA)	DDR5
		Turin Dense	9005 series	192× Zen 5c	Socket SP5 (LGA)
		Sorano	8005 series	64× Zen 5c	Socket SP6 (LGA)
	2025	Grado	4005 series	16× Zen 5	Socket AM5 (LGA)
6th	2026	Venice	9006 series (Verona / Murano )	96× Zen 6	Socket SP8 (LGA)	DDR5/6
		Venice Classic		128× Zen 6c	Socket SP7 (LGA)
		Venice Dense		256× Zen 6c	Socket SP7 (LGA)
7st	2027	Verano	9007 series	256× Zen 7	Socket SP7 (LGA)	DDR5/6
Embedded
1st	2018	Snowy Owl	Embedded 3001 series	16× Zen	Package SP4 (BGA)	DDR4
1st	2019	Naples	Embedded 7001 series	32× Zen	Socket SP3 (LGA)
2nd	2021	Rome	Embedded 7002 series	64× Zen 2
3rd	2022	Milan	Embedded 7003 series	64× Zen 3
4th	2023	Genoa	Embedded 9004 series	96× Zen 4	Socket SP5 (LGA)	DDR5
4th	2023	Siena	Embedded 8004 series	64× Zen 4c	Socket SP6 (LGA)
5th	2025	Turin (-X)	Embedded 9005 series	128× Zen 5	Socket SP5 (LGA)
		Turin Dense	Embedded 9005 series	192× Zen 5c	Socket SP5 (LGA)
		Grado	Embedded 4005 series	16× Zen 5	Socket AM5 (LGA)
		Prado	Embedded 2005 series	16× Zen 5	Socket AM5 (LGA)

Members[edit]

EPYC Embedded 3001 Series (Zen)[edit]

See also: Snowy Owl and Zen µarch

Introduced in early 2018, the 3000 embedded series is based on the Zen microarchitecture using the same dies as the server EPYC processors. 3000-series come in anywhere from 4 to 16 cores as well as with and without SMT support. Models with 8 or less cores come in a single-die configuration and uses a single-chip module Package SP4r4 while models with more than eight cores come in a dual-die configuration and use a multi-chip module Package SP4. Both packages are ball grid arrays (BGAs) and are pin-compatible with each other. Geared toward embedded applications means those parts have lower TDP than their server counterparts. Depending on the die configuration, the features of the dual-die config are mostly double that of the single-die config.

Dual-die Models
- Mem: Quad-channel 64-bit DDR4-2666 w/ ECC, up to 1 TiB
- I/O: x64 PCIe lanes MUX'ed with SATA/GbE and can be mixed configured PCIe and up to 16 SATA ports and up to 10 x 10GbE ports
- TDP: 65-100 W
Single-die Models
- Mem: Dual-channel 64-bit DDR4-2666/2133 w/ ECC, up to 512 GiB
- I/O: x32 PCIe lanes MUX'ed with SATA/GbE and can be mixed configured PCIe and up to 8 SATA ports and up to 4 x 10GbE ports
- TDP: 30-50 W

The ISA and Technology applies to all models.

ISA: Everything up to AVX2 (i.e., SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2), and SHA
Tech: Precision Boost, 2-way SMT, AMD-Vi, AMD-V, Secure Memory Encryption (SME), and Secure Encrypted Virtualization (SEV)

	List EPYC Embedded 3000-Series Processors
Model	Price	Launched	Cores	Thread	L2$	L3$	TDP	Base	Turbo (Max)	Memory	PCIe Lanes
	Single-Chip Package (1 die)
3101		21 February 2018	4	4	2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	35 W 35,000 mW 0.0469 hp 0.035 kW	2.1 GHz 2,100 MHz 2,100,000 kHz	2.9 GHz 2,900 MHz 2,900,000 kHz	DDR4-2666
3151		21 February 2018	4	8	2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	45 W 45,000 mW 0.0603 hp 0.045 kW	2.7 GHz 2,700 MHz 2,700,000 kHz	2.9 GHz 2,900 MHz 2,900,000 kHz	DDR4-2666
3201		21 February 2018	8	8	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	30 W 30,000 mW 0.0402 hp 0.03 kW	1.5 GHz 1,500 MHz 1,500,000 kHz	3.1 GHz 3,100 MHz 3,100,000 kHz	DDR4-2133
3251	$ 315.00 € 283.50 £ 255.15 ¥ 32,548.95	21 February 2018	8	16	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	55 W 55,000 mW 0.0738 hp 0.055 kW	2.5 GHz 2,500 MHz 2,500,000 kHz	3.1 GHz 3,100 MHz 3,100,000 kHz	DDR4-2666
3255			8	16	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	55 W 55,000 mW 0.0738 hp 0.055 kW	2.5 GHz 2,500 MHz 2,500,000 kHz	3.1 GHz 3,100 MHz 3,100,000 kHz	DDR4-2666
	Multi-Chip Package (2 dies)
3301	$ 450.00 € 405.00 £ 364.50 ¥ 46,498.50	21 February 2018	12	12	6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	65 W 65,000 mW 0.0872 hp 0.065 kW	2 GHz 2,000 MHz 2,000,000 kHz	3 GHz 3,000 MHz 3,000,000 kHz	DDR4-2666
3351		21 February 2018	12	24	6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	80 W 80,000 mW 0.107 hp 0.08 kW	1.9 GHz 1,900 MHz 1,900,000 kHz	3 GHz 3,000 MHz 3,000,000 kHz	DDR4-2666
3401		21 February 2018	16	16	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	85 W 85,000 mW 0.114 hp 0.085 kW	1.85 GHz 1,850 MHz 1,850,000 kHz	3 GHz 3,000 MHz 3,000,000 kHz	DDR4-2666
3451	$ 880.00 € 792.00 £ 712.80 ¥ 90,930.40	21 February 2018	16	32	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	100 W 100,000 mW 0.134 hp 0.1 kW	2.15 GHz 2,150 MHz 2,150,000 kHz	3 GHz 3,000 MHz 3,000,000 kHz	DDR4-2666
Count: 9

EPYC Embedded Series[edit]

EPYC Embedded 2005 Series[edit]

"Fire Range" • EPYC Embedded (Zen 5)

Model Name		Codename    Cores (C/T)   Clock     	Socket	     Process  L3 Cache	TDP	Released

EPYC Embedded 2435	Fire Range	 8/16	2.8/4.5 GHz	Socket FL1	4 nm	32 MB	45 W	Nov 2025
EPYC Embedded 2655	Fire Range	12/24	2.7/4.5 GHz	Socket FL1	4 nm	64 MB	55 W	Nov 2025
EPYC Embedded 2875	Fire Range	16/32	3.0/4.5 GHz	Socket FL1	4 nm	64 MB	75 W	Nov 2025

EPYC Embedded 3001 Series[edit]

"Snowy Owl" • EPYC Embedded (Zen)

Model Name		Codename   Cores (C/T)	   Clock	Socket	      Process L3 Cache	TDP	Released

EPYC Embedded 3101	Snowy Owl	4/4	2.1/2.9 GHz	BGA SP4r2	14 nm	 8 MB	35 W	Feb 2018
EPYC Embedded 3151	Snowy Owl	4/8	2.7/2.9 GHz	BGA SP4r2	14 nm	16 MB	45 W	Feb 2018
EPYC Embedded 3201	Snowy Owl	8/8	1.5/3.1 GHz	BGA SP4r2	14 nm	16 MB	30 W	Feb 2018
EPYC Embedded 3251	Snowy Owl	8/16	2.5/3.1 GHz	BGA SP4r2	14 nm	16 MB	55 W	Feb 2018
EPYC Embedded 3255	Snowy Owl	8/16	2.5/3.1 GHz	BGA SP4r2	14 nm	16 MB	55 W	Feb 2018
EPYC Embedded 3351	Snowy Owl      12/24	1.9/3.0 GHz	BGA SP4r2	14 nm	32 MB	80 W	Feb 2018
EPYC Embedded 3451	Snowy Owl      16/32	2.15/3.0 GHz	BGA SP4r2	14 nm	32 MB  100 W	Feb 2018

EPYC Embedded 4004 Series[edit]

"Raphael-R" • EPYC Embedded (Zen 4)

Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	 TDP	Released

EPYC Embedded 4124P	Raphael-R     4/8	3.8/5.1 GHz	Socket AM5	5 nm	32 MB	 65 W	May 2024
EPYC Embedded 4244P	Raphael-R     6/12	3.8/5.1 GHz	Socket AM5	5 nm	32 MB	 65 W	May 2024
EPYC Embedded 4344P	Raphael-R     8/16	3.8/5.3 GHz	Socket AM5	5 nm	32 MB	 65 W	May 2024
EPYC Embedded 4364P	Raphael-R     8/16	4.5/5.4 GHz	Socket AM5	5 nm	32 MB	105 W	May 2024
EPYC Embedded 4464P	Raphael-R    12/24	3.7/5.4 GHz	Socket AM5	5 nm	64 MB	 65 W	May 2024
EPYC Embedded 4484PX	Raphael-R    12/24	4.4/5.6 GHz	Socket AM5	5 nm   128 MB	120 W	May 2024
EPYC Embedded 4564P	Raphael-R    16/32	4.5/5.7 GHz	Socket AM5	5 nm	64 MB	170 W	May 2024
EPYC Embedded 4584PX	Raphael-R    16/32	4.2/5.7 GHz	Socket AM5	5 nm   128 MB	120 W	May 2024

EPYC Embedded 4005 Series[edit]

"Grado" • EPYC Embedded (Zen 5)

Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	 TDP	Released

EPYC Embedded 4245P	Grado		 6/12	3.9/5.4 GHz	Socket AM5	4 nm	32 MB	 65 W	May 2025
EPYC Embedded 4345P	Grado		 8/16	3.8/5.5 GHz	Socket AM5	4 nm	32 MB	 65 W	May 2025
EPYC Embedded 4465P	Grado		12/24	3.4/5.4 GHz	Socket AM5	4 nm	64 MB	 65 W	May 2025
EPYC Embedded 4545P	Grado		16/32	3.0/5.4 GHz	Socket AM5	4 nm	64 MB	 65 W	May 2025
EPYC Embedded 4565P	Grado		16/32	4.3/5.7 GHz	Socket AM5	4 nm	64 MB	170 W	May 2025
EPYC Embedded 4585PX	Grado		16/32	4.3/5.7 GHz	Socket AM5	4 nm   128 MB	170 W	May 2025

EPYC Embedded 7002 Series[edit]

"Rome" • EPYC Embedded (Zen 2)

Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	TDP	Released

EPYC Embedded 7232P	Rome		 8/16	3.1/3.2 GHz	Socket SP3	7 nm	16 MB	120 W	Aug 2019
EPYC Embedded 7252	Rome		 8/16	3.1/3.2 GHz	Socket SP3	7 nm	32 MB	120 W	Aug 2019
EPYC Embedded 7262	Rome		 8/16	3.2/3.4 GHz	Socket SP3	7 nm	32 MB	155 W	Aug 2019
EPYC Embedded 7272	Rome		12/24	2.9/3.2 GHz	Socket SP3	7 nm	32 MB	120 W	Aug 2019
EPYC Embedded 7282	Rome		16/32	2.8/3.2 GHz	Socket SP3	7 nm	32 MB	120 W	Aug 2019
EPYC Embedded 7302	Rome		16/32	3.0/3.3 GHz	Socket SP3	7 nm	32 MB	155 W	Aug 2019
EPYC Embedded 7302P	Rome		16/32	3.0/3.3 GHz	Socket SP3	7 nm	32 MB	155 W	Aug 2019
EPYC Embedded 7352	Rome		24/48	2.3/3.2 GHz	Socket SP3	7 nm	32 MB	155 W	Aug 2019
EPYC Embedded 7402	Rome		24/48	2.8/3.35 GHz	Socket SP3	7 nm	32 MB	180 W	Aug 2019
EPYC Embedded 7402P	Rome		24/48	2.8/3.35 GHz	Socket SP3	7 nm	128 MB	180 W	Aug 2019
EPYC Embedded 7452	Rome		32/64	2.2/3.35 GHz	Socket SP3	7 nm	128 MB	155 W	Aug 2019
EPYC Embedded 7502	Rome		32/64	2.5/3.35 GHz	Socket SP3	7 nm	128 MB	180 W	Aug 2019
EPYC Embedded 7502P	Rome		32/64	2.5/3.35 GHz	Socket SP3	7 nm	128 MB	180 W	Aug 2019
EPYC Embedded 7542	Rome		32/64	 2.9/3.4 GHz	Socket SP3	7 nm	128 MB	225 W	Aug 2019
EPYC Embedded 7552	Rome		48/96	 2.2/3.3 GHz	Socket SP3	7 nm	192 MB	200 W	Aug 2019
EPYC Embedded 7642	Rome		48/96	 2.4/3.4 GHz	Socket SP3	7 nm	256 MB	225 W	Aug 2019
EPYC Embedded 7662	Rome		64/128	 2.0/3.3 GHz	Socket SP3	7 nm	256 MB	200 W	Aug 2019 +
EPYC 7702		Rome		64/128	2.0/3.35 GHz	Socket SP3	7 nm	256 MB	200 W	Aug 2019 -
EPYC 7702P		Rome		64/128	2.0/3.35 GHz	Socket SP3	7 nm	256 MB	200 W	Aug 2019 -
EPYC Embedded 7742	Rome		64/128	2.25/3.4 GHz	Socket SP3	7 nm	256 MB	225 W	Aug 2019

EPYC Embedded 7003 Series[edit]

"Milan" • EPYC Embedded (Zen 3)

Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	TDP	Released

EPYC 7203		Milan		 8/16	2.8/3.4 GHz	Socket SP3	7 nm	 64 MB	120 W	Sep 2023
EPYC 7203P		Milan		 8/16	2.8/3.4 GHz	Socket SP3	7 nm	 64 MB	120 W	Sep 2023
EPYC 72F3		Milan		 8/16	3.7/4.1 GHz	Socket SP3	7 nm	256 MB	180 W	Mar 2021
EPYC 7303		Milan		16/32	2.4/3.4 GHz	Socket SP3	7 nm	 64 MB	130 W	Sep 2023
EPYC 7303P		Milan		16/32	2.4/3.4 GHz	Socket SP3	7 nm	 64 MB	130 W	Sep 2023
EPYC Embedded 7313	Milan		16/32	3.0/3.7 GHz	Socket SP3	7 nm	128 MB	155 W	Mar 2021
EPYC Embedded 7313P	Milan		16/32	3.0/3.7 GHz	Socket SP3	7 nm	128 MB	155 W	Mar 2021
EPYC 7343		Milan		16/32	3.2/3.9 GHz	Socket SP3	7 nm	128 MB	190 W	Mar 2021
EPYC 73F3		Milan		16/32	3.5/4.0 GHz	Socket SP3	7 nm	256 MB	240 W	Mar 2021
EPYC Embedded 7413	Milan		24/48	2.65/3.6 GHz	Socket SP3	7 nm	128 MB	180 W	Mar 2021
EPYC Embedded 7443	Milan		24/48	2.85/4.0 GHz	Socket SP3	7 nm	128 MB	200 W	Mar 2021
EPYC Embedded 7443P	Milan		24/48	2.85/4.0 GHz	Socket SP3	7 nm	128 MB	200 W	Mar 2021
EPYC 7453		Milan		28/56	2.75/3.45 GHz	Socket SP3	7 nm	 64 MB	225 W	Mar 2021
EPYC 74F3		Milan		24/48	 2.8/4.0 GHz	Socket SP3	7 nm	256 MB	240 W	Mar 2021
EPYC 7513		Milan		32/64	 2.6/3.65 GHz	Socket SP3	7 nm	128 MB	200 W	Mar 2021
EPYC Embedded 7543	Milan		32/64	 2.8/3.7 GHz	Socket SP3	7 nm	256 MB	225 W	Mar 2021
EPYC Embedded 7543P	Milan		32/64	 2.8/3.7 GHz	Socket SP3	7 nm	256 MB	225 W	Mar 2021
EPYC 75F3		Milan		32/64	 2.95/4.0 GHz	Socket SP3	7 nm	256 MB	280 W	Mar 2021 -
EPYC Embedded 7643	Milan		48/96	 2.3/3.6 GHz	Socket SP3	7 nm	256 MB	225 W	Mar 2021
EPYC 7643P		Milan		48/96	 2.3/3.6 GHz	Socket SP3	7 nm	256 MB	225 W	Sep 2023
EPYC 7663		Milan		56/112	 2.0/3.5 GHz	Socket SP3	7 nm	256 MB	240 W	Mar 2021
EPYC 7663P		Milan		56/112	 2.0/3.5 GHz	Socket SP3	7 nm	256 MB	240 W	Sep 2023
EPYC Embedded 7713	Milan		64/128	2.0/3.675 GHz	Socket SP3	7 nm	256 MB	225 W	Mar 2021
EPYC Embedded 7713P	Milan		64/128	2.0/3.675 GHz	Socket SP3	7 nm	256 MB	225 W	Mar 2021
EPYC 7763		Milan		64/128	 2.45/3.5 GHz	Socket SP3	7 nm	256 MB	280 W	Mar 2021 -

EPYC Embedded 8004 Series[edit]

"Siena" • EPYC Embedded (Zen 4c)

Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	TDP	Released

EPYC Embedded 8C24P	Siena		12/24	2.45/3.0 GHz	Socket SP6	5 nm	 32 MB	100 W	Sep 2023
EPYC Embedded 8124P	Siena		16/32	2.45/3.0 GHz	Socket SP6	5 nm	 64 MB	125 W	Sep 2023
EPYC Embedded 8224P	Siena		24/48	2.55/3.0 GHz	Socket SP6	5 nm	 64 MB	160 W	Sep 2023
EPYC Embedded 8324P	Siena		32/64	2.65/3.0 GHz	Socket SP6	5 nm	128 MB	180 W	Sep 2023
EPYC Embedded 8434P	Siena		48/96	 2.5/3.1 GHz	Socket SP6	5 nm	128 MB	200 W	Oct 2024
EPYC Embedded 8534P	Siena		64/128	 2.3/3.1 GHz	Socket SP6	5 nm	128 MB	200 W	Oct 2024

EPYC Embedded 9004 Series[edit]

"Genoa" (9xx4) • EPYC Embedded (Zen 4)
"Bergamo" (97x4) • EPYC Embedded (Zen 4c)

Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	TDP	Released

EPYC Embedded 9124	Genoa		16/32	 3.0/3.7 GHz	Socket SP5	5 nm	 64 MB	200 W	Mar 2023
EPYC Embedded 9254	Genoa		24/48	2.9/4.15 GHz	Socket SP5	5 nm	128 MB	200 W	Mar 2023
EPYC Embedded 9354	Genoa		32/64	3.25/3.8 GHz	Socket SP5	5 nm	256 MB	280 W	Mar 2023
EPYC Embedded 9354P	Genoa		32/64	3.25/3.8 GHz	Socket SP5	5 nm	256 MB	280 W	Mar 2023
EPYC Embedded 9454	Genoa		48/96	2.75/3.8 GHz	Socket SP5	5 nm	256 MB	290 W	Mar 2023
EPYC Embedded 9454P	Genoa		48/96	2.75/3.8 GHz	Socket SP5	5 nm	256 MB	290 W	Mar 2023
EPYC Embedded 9534	Genoa		64/128	2.45/3.7 GHz	Socket SP5	5 nm	256 MB	280 W	Mar 2023 +
EPYC Embedded 9554	Genoa		64/128	3.1/3.75 GHz	Socket SP5	5 nm	256 MB	360 W	Mar 2023
EPYC Embedded 9554P	Genoa		64/128	3.1/3.75 GHz	Socket SP5	5 nm	256 MB	360 W	Mar 2023
EPYC Embedded 9654	Genoa		96/192	 2.4/3.7 GHz	Socket SP5	5 nm	384 MB	360 W	Mar 2023
EPYC Embedded 9654P	Genoa		96/192	 2.4/3.7 GHz	Socket SP5	5 nm	384 MB	360 W	Mar 2023

EPYC 9734		Bergamo		112/224	 2.2/3.0 GHz	Socket SP5	5 nm	256 MB	340 W	Jun 2023
EPYC 9754		Bergamo		128/256	2.25/3.1 GHz	Socket SP5	5 nm	256 MB	360 W	Jun 2023
EPYC 9754S		Bergamo		128/256	2.25/3.1 GHz	Socket SP5	5 nm	256 MB	360 W	Jun 2023

EPYC Embedded 9005 Series[edit]

"Turin" • EPYC Embedded (Zen 5/5c)

Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	TDP	Released

EPYC Embedded 9015	Turin		 8/16	 3.6/4.1 GHz	Socket SP5	4 nm	 64 MB	125 W	Oct 2024
EPYC 9115		Turin		16/32	 2.6/4.1 GHz	Socket SP5	4 nm	 64 MB	125 W	Oct 2024
EPYC Embedded 9135	Turin		16/32	3.65/4.3 GHz	Socket SP5	4 nm	 64 MB	200 W	Oct 2024
EPYC 9175F		Turin		16/32	 4.2/5.0 GHz	Socket SP5	4 nm	512 MB	320 W	Oct 2024
EPYC Embedded 9255	Turin		24/48	3.25/4.8 GHz	Socket SP5	4 nm	128 MB	200 W	Oct 2024
EPYC 9275F		Turin		24/48	 4.1/4.8 GHz	Socket SP5	4 nm	256 MB	320 W	Oct 2024
EPYC Embedded 9335	Turin		32/64	 3.0/4.4 GHz	Socket SP5	4 nm	128 MB	210 W	Oct 2024
EPYC Embedded 9355	Turin		32/64	3.55/4.4 GHz	Socket SP5	4 nm	256 MB	280 W	Oct 2024
EPYC Embedded 9355P	Turin		32/64	3.55/4.4 GHz	Socket SP5	4 nm	256 MB	280 W	Oct 2024
EPYC 9365		Turin		36/72	 3.4/4.3 GHz	Socket SP5	4 nm	192 MB	300 W	Oct 2024
EPYC 9375F		Turin		32/64	3.85/4.8 GHz	Socket SP5	4 nm	256 MB	320 W	Oct 2024
EPYC Embedded 9455	Turin		48/96	3.15/4.4 GHz	Socket SP5	4 nm	256 MB	300 W	Oct 2024
EPYC Embedded 9455P	Turin		48/96	3.15/4.4 GHz	Socket SP5	4 nm	256 MB	300 W	Oct 2024
EPYC 9475F		Turin		48/96	3.65/4.8 GHz	Socket SP5	4 nm	256 MB	400 W	Oct 2024
EPYC Embedded 9535	Turin		64/128	 2.4/4.3 GHz	Socket SP5	4 nm	256 MB	300 W	Oct 2024
EPYC Embedded 9555	Turin		64/128	 3.2/4.4 GHz	Socket SP5	4 nm	256 MB	360 W	Oct 2024
EPYC Embedded 9555P	Turin		64/128	 3.2/4.4 GHz	Socket SP5	4 nm	256 MB	360 W	Oct 2024
EPYC 9565		Turin		72/144	3.15/4.3 GHz	Socket SP5	4 nm	384 MB	400 W	Oct 2024
EPYC 9575F		Turin		64/128	 3.3/5.0 GHz	Socket SP5	4 nm	256 MB	400 W	Oct 2024
EPYC 9645		Turin		96/192	 2.3/3.7 GHz	Socket SP5	3 nm	256 MB	320 W	Oct 2024
EPYC Embedded 9655	Turin		96/192	 2.6/4.5 GHz	Socket SP5	4 nm	384 MB	400 W	Oct 2024
EPYC Embedded 9655P	Turin		96/192	 2.6/4.5 GHz	Socket SP5	4 nm	384 MB	400 W	Oct 2024
EPYC Embedded 9745	Turin		128/256	 2.4/3.7 GHz	Socket SP5	3 nm	256 MB	400 W	Oct 2024
EPYC Embedded 9755	Turin		128/256	 2.7/4.1 GHz	Socket SP5	4 nm	512 MB	500 W	Oct 2024
EPYC 9825		Turin		144/288	 2.2/3.7 GHz	Socket SP5	3 nm	384 MB	390 W	Oct 2024
EPYC Embedded 9845	Turin		160/320	 2.1/3.7 GHz	Socket SP5	3 nm	320 MB	390 W	Oct 2024
EPYC Embedded 9965	Turin		192/384	2.25/3.7 GHz	Socket SP5	3 nm	384 MB	500 W	Oct 2024

EPYC Embedded 9006 Series[edit]

"Venice" • EPYC Embedded (Zen 6/6c)

"Venice Classic" • "Venice Dense"

EPYC Embedded Annapurna Series[edit]

Documents[edit]

EPYC 3000 series Product Brief

designer	AMD +
first announced	February 22, 2018 +
first launched	February 22, 2018 +
full page name	amd/epyc embedded +
instance of	system on a chip family +
instruction set architecture	x86-64 +
main designer	AMD +
manufacturer	GlobalFoundries +
microarchitecture	Zen +
name	AMD EPYC Embedded +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	Socket SP4 + and Socket SP4r2 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +

@@ Line 31: / Line 31: @@
 == Overview ==
 The EPYC Embedded family is a low-power variant of the {{amd|EPYC}} line that primarily marketed towards embedded devices such as networking, storage, and edge computing devices. Those parts have lower TDPs and come in a much smaller package allowing for denser integration.
+{{clear}}
+== [[AMD]] [[EPYC]] CPU Generations ==
+{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;"
+|+ AMD EPYC CPU Generations
+! Gen
+! Year
+! Codename
+! Product line
+! Cores
+! Socket
+! Memory
+|-
+! colspan="7" | Server
+|-
+| 1st
+| 2017
+| {{amd|Naples|l=core}}
+| 7001 series
+| 32× {{amd|Zen|l=arch}}
+| rowspan="4" | {{amd|SP3|Socket SP3|l=package}} (LGA)
+| rowspan="4" | DDR4
+|-
+| 2nd
+| 2019
+| {{amd|Rome|l=core}}
+| 7002 series
+| 64× {{amd|Zen 2|l=arch}}
+|-
+| rowspan="2" |3rd
+| 2021
+| {{amd|Milan|l=core}}
+| 7003 series
+| rowspan="2" | 64× {{amd|Zen 3|l=arch}}
+|-
+| 2022
+| {{amd|Milan|l=core}}-X
+| 7004 series
+|-
+| rowspan="5" | 4th
+| 2022
+| {{amd|Genoa|l=core}}
+| rowspan="3" | 9004 series
+| rowspan="2" | 96× {{amd|Zen 4|l=arch}}
+| rowspan="3" | {{amd|SP5|Socket SP5|l=package}} (LGA)
+| rowspan="5" | DDR5
+|-
+| rowspan="3" | 2023
+| {{amd|Genoa|l=core}}-X
+|-
+| {{amd|Bergamo|l=core}}
+| 128× {{amd|Zen 4|l=arch}}c
+|-
+| {{amd|Siena|l=core}}
+| 8004 series
+| 64× {{amd|Zen 4|l=arch}}c
+| {{amd|SP6|Socket SP6|l=package}} (LGA)
+|-
+| 2024
+| {{amd|Raphael|l=core}}-X
+| 4004 series
+| 16× {{amd|Zen 4|l=arch}}
+| {{amd|AM5|Socket AM5|l=package}} (LGA)
+|-
+| rowspan="4" | 5th
+| rowspan="3" | 2024
+| {{amd|Turin|l=core}} (-X)
+| rowspan="2" | 9005 series
+| 128× {{amd|Zen 5|l=arch}}
+| rowspan="2" | {{amd|SP5|Socket SP5|l=package}} (LGA)
+| rowspan="4" | DDR5
+|-
+| {{amd|Turin|l=core}} Dense
+| 192× {{amd|Zen 5|l=arch}}c
+|-
+| {{amd|Sorano|l=core}}
+| 8005 series
+| 64× {{amd|Zen 5|l=arch}}c
+| {{amd|SP6|Socket SP6|l=package}} (LGA)
+|-
+| 2025
+| {{amd|Grado|l=core}}
+| 4005 series
+| 16× {{amd|Zen 5|l=arch}}
+| {{amd|AM5|Socket AM5|l=package}} (LGA)
+|-
+| rowspan="3" | 6th
+| rowspan="3" | 2026
+| {{amd|Venice|l=core}}
+| rowspan="3" | 9006 series <br>(''Verona'' /<br>''Murano'' )
+| 96× {{amd|Zen 6|l=arch}}
+| {{amd|SP7|Socket SP8|l=package}} (LGA)
+| rowspan="3" | DDR5/6
+|-
+| {{amd|Venice|l=core}} Classic
+| 128× {{amd|Zen 6|l=arch}}c
+| rowspan="2" | {{amd|SP7|Socket SP7|l=package}} (LGA)
+|-
+| {{amd|Venice|l=core}} Dense
+| 256× {{amd|Zen 6|l=arch}}c
+|-
+| 7st
+| 2027
+| {{amd|Verano|l=core}}
+| 9007 series
+| 256× {{amd|Zen 7|l=arch}}
+| {{amd|SP7|Socket SP7|l=package}} (LGA)
+| DDR5/6
+|-
+! colspan="7" | Embedded
+|-
+| rowspan="2" | 1st
+| 2018
+| {{amd|Snowy Owl|l=core}}
+| Embedded 3001 series
+| 16× {{amd|Zen|l=arch}}
+| {{amd|SP4|Package SP4|l=package}} (BGA)
+| rowspan="4" | DDR4
+|-
+| 2019
+| {{amd|Naples|l=core}}
+| Embedded 7001 series
+| 32× {{amd|Zen|l=arch}}
+| rowspan="3" | {{amd|SP3|Socket SP3|l=package}} (LGA)
+|-
+| 2nd
+| 2021
+| {{amd|Rome|l=core}}
+| Embedded 7002 series
+| 64× {{amd|Zen 2|l=arch}}
+|-
+| 3rd
+| 2022
+| {{amd|Milan|l=core}}
+| Embedded 7003 series
+| 64× {{amd|Zen 3|l=arch}}
+|-
+| rowspan="2" | 4th
+| rowspan="2" | 2023
+| {{amd|Genoa|l=core}}
+| Embedded 9004 series
+| 96× {{amd|Zen 4|l=arch}}
+| {{amd|SP5|Socket SP5|l=package}} (LGA)
+| rowspan="6" | DDR5
+|-
+| {{amd|Siena|l=core}}
+| Embedded 8004 series
+| 64× {{amd|Zen 4|l=arch}}c
+| {{amd|SP6|Socket SP6|l=package}} (LGA)
+|-
+| rowspan="4" | 5th
+| rowspan="4" | 2025
+| {{amd|Turin|l=core}} (-X)
+| rowspan="2" | Embedded 9005 series
+| 128× {{amd|Zen 5|l=arch}}
+| rowspan="2" | {{amd|SP5|Socket SP5|l=package}} (LGA)
+|-
+| {{amd|Turin|l=core}} Dense
+| 192× {{amd|Zen 5|l=arch}}c
+|-
+| {{amd|Grado|l=core}}
+| Embedded 4005 series
+| 16× {{amd|Zen 5|l=arch}}
+| {{amd|AM5|Socket AM5|l=package}} (LGA)
+|-
+| ''{{amd|Prado|l=core}}''
+| Embedded 2005 series
+| 16× {{amd|Zen 5|l=arch}}
+| {{amd|AM5|Socket AM5|l=package}} (LGA)
+|-
+|}
 == Members ==
-=== 3000 Series (Zen) ===
+=== [[EPYC Embedded]] 3001 Series (Zen) ===
 {{see also|amd/cores/snowy_owl|amd/microarchitectures/zen|l1=Snowy Owl|l2=Zen µarch}}
+Introduced in early [[2018]], the 3000 embedded series is based on the {{amd|Zen|Zen microarchitecture|l=arch}} using the same dies as the server {{amd|EPYC}} processors. 3000-series come in anywhere from [[4 cores|4]] to [[16 cores]] as well as with and without [[SMT]] support. Models with 8 or less cores come in a single-die configuration and uses a single-chip module {{amd|Package SP4r4}} while models with more than eight cores come in a dual-die configuration and use a multi-chip module {{amd|Package SP4}}. Both packages are ball grid arrays (BGAs) and are pin-compatible with each other. Geared toward embedded applications means those parts have lower TDP than their server counterparts. Depending on the die configuration, the features of the dual-die config are mostly double that of the single-die config.
+* Dual-die Models
+** '''Mem:''' Quad-channel 64-bit DDR4-2666 w/ ECC, up to 1 TiB
+** '''I/O:''' x64 PCIe lanes MUX'ed with SATA/GbE and can be mixed configured PCIe and up to 16 SATA ports and up to 10 x 10GbE  ports
+** '''TDP:''' 65-100 W
+* Single-die Models
+** '''Mem:''' Dual-channel 64-bit DDR4-2666/2133 w/ ECC, up to 512 GiB
+** '''I/O:''' x32 PCIe lanes MUX'ed with SATA/GbE and can be mixed configured PCIe and up to 8 SATA ports and up to 4 x 10GbE  ports
+** '''TDP:''' 30-50 W
+The ISA and Technology applies to all models.
+* '''ISA:''' Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}
+* '''Tech:''' {{amd|Precision Boost}}, 2-way [[SMT]], {{amd|AMD-Vi}}, {{amd|AMD-V}}, {{amd|Secure Memory Encryption}} (SME), and {{amd|Secure Encrypted Virtualization}} (SEV)
 <!-- NOTE:
             This table is generated automatically from the data in the actual articles.
@@ Line 43: / Line 232: @@
 -->
 {{comp table start}}
-<table class="comptable sortable tc4 tc5 tc13">
+<table class="comptable sortable tc4 tc5 tc9 tc10 tc12">
-{{comp table header|main|12:List EPYC Embedded 3000-Series Processors}}
+{{comp table header|main|11:List EPYC Embedded 3000-Series Processors}}
-{{comp table header|cols|Price|Launched|Cores|Thread|L2$|L3$|%TDP|%Base|%Turbo (Max)|%Turbo (All)|Memory|PCIe Lanes}}
+{{comp table header|cols|Price|Launched|Cores|Thread|L2$|L3$|%TDP|%Base|%Turbo (Max)|Memory|PCIe Lanes}}
-{{comp table header|lsep|12:Single-Chip Package (1 die)}}
+{{comp table header|lsep|11:Single-Chip Package (1 die)}}
 {{#ask: [[Category:microprocessor models by amd]] [[microarchitecture::Zen]] [[family::EPYC Embedded]] [[core count::<8]]
   |?full page name
@@ Line 58: / Line 247: @@
   |?tdp
   |?base frequency#GHz
- |?turbo frequency (13 cores)#GHz
   |?turbo frequency (1 core)#GHz
   |?supported memory type
@@ Line 64: / Line 252: @@
   |format=template
   |template=proc table 3
-  |userparam=14
+  |userparam=13
   |mainlabel=-
 }}
-{{comp table header|lsep|12:Multi-Chip Package (2 dies)}}
+{{comp table header|lsep|11:Multi-Chip Package (2 dies)}}
 {{#ask: [[Category:microprocessor models by amd]] [[microarchitecture::Zen]] [[family::EPYC Embedded]] [[core count::>9]]
   |?full page name
@@ Line 79: / Line 267: @@
   |?tdp
   |?base frequency#GHz
- |?turbo frequency (13 cores)#GHz
   |?turbo frequency (1 core)#GHz
   |?supported memory type
@@ Line 85: / Line 272: @@
   |format=template
   |template=proc table 3
-  |userparam=14
+  |userparam=13
   |mainlabel=-
 }}
@@ Line 91: / Line 278: @@
 </table>
 {{comp table end}}
+== [[EPYC Embedded]] Series ==
+=== [[EPYC Embedded]] 2005 Series ===
+:;"Fire Range" • [[EPYC]] Embedded ({{amd|Zen 5|l=arch}})
+<pre>
+Model Name		Codename    Cores (C/T)   Clock     	Socket	     Process  L3 Cache	TDP	Released
+EPYC Embedded 2435	Fire Range	 8/16	2.8/4.5 GHz	Socket FL1	4 nm	32 MB	45 W	Nov 2025
+EPYC Embedded 2655	Fire Range	12/24	2.7/4.5 GHz	Socket FL1	4 nm	64 MB	55 W	Nov 2025
+EPYC Embedded 2875	Fire Range	16/32	3.0/4.5 GHz	Socket FL1	4 nm	64 MB	75 W	Nov 2025
+</pre>
+=== [[EPYC Embedded]] 3001 Series ===
+:;"Snowy Owl" • [[EPYC]] Embedded ({{amd|Zen|l=arch}})
+<pre>
+Model Name		Codename   Cores (C/T)	   Clock	Socket	      Process L3 Cache	TDP	Released
+EPYC Embedded 3101	Snowy Owl	4/4	2.1/2.9 GHz	BGA SP4r2	14 nm	 8 MB	35 W	Feb 2018
+EPYC Embedded 3151	Snowy Owl	4/8	2.7/2.9 GHz	BGA SP4r2	14 nm	16 MB	45 W	Feb 2018
+EPYC Embedded 3201	Snowy Owl	8/8	1.5/3.1 GHz	BGA SP4r2	14 nm	16 MB	30 W	Feb 2018
+EPYC Embedded 3251	Snowy Owl	8/16	2.5/3.1 GHz	BGA SP4r2	14 nm	16 MB	55 W	Feb 2018
+EPYC Embedded 3255	Snowy Owl	8/16	2.5/3.1 GHz	BGA SP4r2	14 nm	16 MB	55 W	Feb 2018
+EPYC Embedded 3351	Snowy Owl      12/24	1.9/3.0 GHz	BGA SP4r2	14 nm	32 MB	80 W	Feb 2018
+EPYC Embedded 3451	Snowy Owl      16/32	2.15/3.0 GHz	BGA SP4r2	14 nm	32 MB  100 W	Feb 2018
+</pre>
+=== [[EPYC Embedded]] 4004 Series ===
+:;"Raphael-R" • [[EPYC]] Embedded ({{amd|Zen 4|l=arch}})
+<pre>
+Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	 TDP	Released
+EPYC Embedded 4124P	Raphael-R     4/8	3.8/5.1 GHz	Socket AM5	5 nm	32 MB	 65 W	May 2024
+EPYC Embedded 4244P	Raphael-R     6/12	3.8/5.1 GHz	Socket AM5	5 nm	32 MB	 65 W	May 2024
+EPYC Embedded 4344P	Raphael-R     8/16	3.8/5.3 GHz	Socket AM5	5 nm	32 MB	 65 W	May 2024
+EPYC Embedded 4364P	Raphael-R     8/16	4.5/5.4 GHz	Socket AM5	5 nm	32 MB	105 W	May 2024
+EPYC Embedded 4464P	Raphael-R    12/24	3.7/5.4 GHz	Socket AM5	5 nm	64 MB	 65 W	May 2024
+EPYC Embedded 4484PX	Raphael-R    12/24	4.4/5.6 GHz	Socket AM5	5 nm   128 MB	120 W	May 2024
+EPYC Embedded 4564P	Raphael-R    16/32	4.5/5.7 GHz	Socket AM5	5 nm	64 MB	170 W	May 2024
+EPYC Embedded 4584PX	Raphael-R    16/32	4.2/5.7 GHz	Socket AM5	5 nm   128 MB	120 W	May 2024
+</pre>
+=== [[EPYC Embedded]] 4005 Series ===
+:;"Grado" • [[EPYC]] Embedded ({{amd|Zen 5|l=arch}})
+<pre>
+Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	 TDP	Released
+EPYC Embedded 4245P	Grado		 6/12	3.9/5.4 GHz	Socket AM5	4 nm	32 MB	 65 W	May 2025
+EPYC Embedded 4345P	Grado		 8/16	3.8/5.5 GHz	Socket AM5	4 nm	32 MB	 65 W	May 2025
+EPYC Embedded 4465P	Grado		12/24	3.4/5.4 GHz	Socket AM5	4 nm	64 MB	 65 W	May 2025
+EPYC Embedded 4545P	Grado		16/32	3.0/5.4 GHz	Socket AM5	4 nm	64 MB	 65 W	May 2025
+EPYC Embedded 4565P	Grado		16/32	4.3/5.7 GHz	Socket AM5	4 nm	64 MB	170 W	May 2025
+EPYC Embedded 4585PX	Grado		16/32	4.3/5.7 GHz	Socket AM5	4 nm   128 MB	170 W	May 2025
+</pre>
+=== [[EPYC Embedded]] 7002 Series ===
+:;"Rome" • [[EPYC]] Embedded ({{amd|Zen 2|l=arch}})
+<pre>
+Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	TDP	Released
+EPYC Embedded 7232P	Rome		 8/16	3.1/3.2 GHz	Socket SP3	7 nm	16 MB	120 W	Aug 2019
+EPYC Embedded 7252	Rome		 8/16	3.1/3.2 GHz	Socket SP3	7 nm	32 MB	120 W	Aug 2019
+EPYC Embedded 7262	Rome		 8/16	3.2/3.4 GHz	Socket SP3	7 nm	32 MB	155 W	Aug 2019
+EPYC Embedded 7272	Rome		12/24	2.9/3.2 GHz	Socket SP3	7 nm	32 MB	120 W	Aug 2019
+EPYC Embedded 7282	Rome		16/32	2.8/3.2 GHz	Socket SP3	7 nm	32 MB	120 W	Aug 2019
+EPYC Embedded 7302	Rome		16/32	3.0/3.3 GHz	Socket SP3	7 nm	32 MB	155 W	Aug 2019
+EPYC Embedded 7302P	Rome		16/32	3.0/3.3 GHz	Socket SP3	7 nm	32 MB	155 W	Aug 2019
+EPYC Embedded 7352	Rome		24/48	2.3/3.2 GHz	Socket SP3	7 nm	32 MB	155 W	Aug 2019
+EPYC Embedded 7402	Rome		24/48	2.8/3.35 GHz	Socket SP3	7 nm	32 MB	180 W	Aug 2019
+EPYC Embedded 7402P	Rome		24/48	2.8/3.35 GHz	Socket SP3	7 nm	128 MB	180 W	Aug 2019
+EPYC Embedded 7452	Rome		32/64	2.2/3.35 GHz	Socket SP3	7 nm	128 MB	155 W	Aug 2019
+EPYC Embedded 7502	Rome		32/64	2.5/3.35 GHz	Socket SP3	7 nm	128 MB	180 W	Aug 2019
+EPYC Embedded 7502P	Rome		32/64	2.5/3.35 GHz	Socket SP3	7 nm	128 MB	180 W	Aug 2019
+EPYC Embedded 7542	Rome		32/64	 2.9/3.4 GHz	Socket SP3	7 nm	128 MB	225 W	Aug 2019
+EPYC Embedded 7552	Rome		48/96	 2.2/3.3 GHz	Socket SP3	7 nm	192 MB	200 W	Aug 2019
+EPYC Embedded 7642	Rome		48/96	 2.4/3.4 GHz	Socket SP3	7 nm	256 MB	225 W	Aug 2019
+EPYC Embedded 7662	Rome		64/128	 2.0/3.3 GHz	Socket SP3	7 nm	256 MB	200 W	Aug 2019 +
+EPYC 7702		Rome		64/128	2.0/3.35 GHz	Socket SP3	7 nm	256 MB	200 W	Aug 2019 -
+EPYC 7702P		Rome		64/128	2.0/3.35 GHz	Socket SP3	7 nm	256 MB	200 W	Aug 2019 -
+EPYC Embedded 7742	Rome		64/128	2.25/3.4 GHz	Socket SP3	7 nm	256 MB	225 W	Aug 2019
+</pre>
+=== [[EPYC Embedded]] 7003 Series ===
+:;"Milan" • [[EPYC]] Embedded ({{amd|Zen 3|l=arch}})
+<pre>
+Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	TDP	Released
+EPYC 7203		Milan		 8/16	2.8/3.4 GHz	Socket SP3	7 nm	 64 MB	120 W	Sep 2023
+EPYC 7203P		Milan		 8/16	2.8/3.4 GHz	Socket SP3	7 nm	 64 MB	120 W	Sep 2023
+EPYC 72F3		Milan		 8/16	3.7/4.1 GHz	Socket SP3	7 nm	256 MB	180 W	Mar 2021
+EPYC 7303		Milan		16/32	2.4/3.4 GHz	Socket SP3	7 nm	 64 MB	130 W	Sep 2023
+EPYC 7303P		Milan		16/32	2.4/3.4 GHz	Socket SP3	7 nm	 64 MB	130 W	Sep 2023
+EPYC Embedded 7313	Milan		16/32	3.0/3.7 GHz	Socket SP3	7 nm	128 MB	155 W	Mar 2021
+EPYC Embedded 7313P	Milan		16/32	3.0/3.7 GHz	Socket SP3	7 nm	128 MB	155 W	Mar 2021
+EPYC 7343		Milan		16/32	3.2/3.9 GHz	Socket SP3	7 nm	128 MB	190 W	Mar 2021
+EPYC 73F3		Milan		16/32	3.5/4.0 GHz	Socket SP3	7 nm	256 MB	240 W	Mar 2021
+EPYC Embedded 7413	Milan		24/48	2.65/3.6 GHz	Socket SP3	7 nm	128 MB	180 W	Mar 2021
+EPYC Embedded 7443	Milan		24/48	2.85/4.0 GHz	Socket SP3	7 nm	128 MB	200 W	Mar 2021
+EPYC Embedded 7443P	Milan		24/48	2.85/4.0 GHz	Socket SP3	7 nm	128 MB	200 W	Mar 2021
+EPYC 7453		Milan		28/56	2.75/3.45 GHz	Socket SP3	7 nm	 64 MB	225 W	Mar 2021
+EPYC 74F3		Milan		24/48	 2.8/4.0 GHz	Socket SP3	7 nm	256 MB	240 W	Mar 2021
+EPYC 7513		Milan		32/64	 2.6/3.65 GHz	Socket SP3	7 nm	128 MB	200 W	Mar 2021
+EPYC Embedded 7543	Milan		32/64	 2.8/3.7 GHz	Socket SP3	7 nm	256 MB	225 W	Mar 2021
+EPYC Embedded 7543P	Milan		32/64	 2.8/3.7 GHz	Socket SP3	7 nm	256 MB	225 W	Mar 2021
+EPYC 75F3		Milan		32/64	 2.95/4.0 GHz	Socket SP3	7 nm	256 MB	280 W	Mar 2021 -
+EPYC Embedded 7643	Milan		48/96	 2.3/3.6 GHz	Socket SP3	7 nm	256 MB	225 W	Mar 2021
+EPYC 7643P		Milan		48/96	 2.3/3.6 GHz	Socket SP3	7 nm	256 MB	225 W	Sep 2023
+EPYC 7663		Milan		56/112	 2.0/3.5 GHz	Socket SP3	7 nm	256 MB	240 W	Mar 2021
+EPYC 7663P		Milan		56/112	 2.0/3.5 GHz	Socket SP3	7 nm	256 MB	240 W	Sep 2023
+EPYC Embedded 7713	Milan		64/128	2.0/3.675 GHz	Socket SP3	7 nm	256 MB	225 W	Mar 2021
+EPYC Embedded 7713P	Milan		64/128	2.0/3.675 GHz	Socket SP3	7 nm	256 MB	225 W	Mar 2021
+EPYC 7763		Milan		64/128	 2.45/3.5 GHz	Socket SP3	7 nm	256 MB	280 W	Mar 2021 -
+</pre>
+=== [[EPYC Embedded]] 8004 Series ===
+:;"Siena" • [[EPYC]] Embedded ({{amd|Zen 4|l=arch}}c)
+<pre>
+Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	TDP	Released
+EPYC Embedded 8C24P	Siena		12/24	2.45/3.0 GHz	Socket SP6	5 nm	 32 MB	100 W	Sep 2023
+EPYC Embedded 8124P	Siena		16/32	2.45/3.0 GHz	Socket SP6	5 nm	 64 MB	125 W	Sep 2023
+EPYC Embedded 8224P	Siena		24/48	2.55/3.0 GHz	Socket SP6	5 nm	 64 MB	160 W	Sep 2023
+EPYC Embedded 8324P	Siena		32/64	2.65/3.0 GHz	Socket SP6	5 nm	128 MB	180 W	Sep 2023
+EPYC Embedded 8434P	Siena		48/96	 2.5/3.1 GHz	Socket SP6	5 nm	128 MB	200 W	Oct 2024
+EPYC Embedded 8534P	Siena		64/128	 2.3/3.1 GHz	Socket SP6	5 nm	128 MB	200 W	Oct 2024
+</pre>
+=== [[EPYC Embedded]] 9004 Series ===
+:;"Genoa" (9xx4) • [[EPYC]] Embedded ({{amd|Zen 4|l=arch}})
+:;"Bergamo" (97x4) • [[EPYC]] Embedded ({{amd|Zen 4|l=arch}}c)
+<pre>
+Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	TDP	Released
+EPYC Embedded 9124	Genoa		16/32	 3.0/3.7 GHz	Socket SP5	5 nm	 64 MB	200 W	Mar 2023
+EPYC Embedded 9254	Genoa		24/48	2.9/4.15 GHz	Socket SP5	5 nm	128 MB	200 W	Mar 2023
+EPYC Embedded 9354	Genoa		32/64	3.25/3.8 GHz	Socket SP5	5 nm	256 MB	280 W	Mar 2023
+EPYC Embedded 9354P	Genoa		32/64	3.25/3.8 GHz	Socket SP5	5 nm	256 MB	280 W	Mar 2023
+EPYC Embedded 9454	Genoa		48/96	2.75/3.8 GHz	Socket SP5	5 nm	256 MB	290 W	Mar 2023
+EPYC Embedded 9454P	Genoa		48/96	2.75/3.8 GHz	Socket SP5	5 nm	256 MB	290 W	Mar 2023
+EPYC Embedded 9534	Genoa		64/128	2.45/3.7 GHz	Socket SP5	5 nm	256 MB	280 W	Mar 2023 +
+EPYC Embedded 9554	Genoa		64/128	3.1/3.75 GHz	Socket SP5	5 nm	256 MB	360 W	Mar 2023
+EPYC Embedded 9554P	Genoa		64/128	3.1/3.75 GHz	Socket SP5	5 nm	256 MB	360 W	Mar 2023
+EPYC Embedded 9654	Genoa		96/192	 2.4/3.7 GHz	Socket SP5	5 nm	384 MB	360 W	Mar 2023
+EPYC Embedded 9654P	Genoa		96/192	 2.4/3.7 GHz	Socket SP5	5 nm	384 MB	360 W	Mar 2023
+EPYC 9734		Bergamo		112/224	 2.2/3.0 GHz	Socket SP5	5 nm	256 MB	340 W	Jun 2023
+EPYC 9754		Bergamo		128/256	2.25/3.1 GHz	Socket SP5	5 nm	256 MB	360 W	Jun 2023
+EPYC 9754S		Bergamo		128/256	2.25/3.1 GHz	Socket SP5	5 nm	256 MB	360 W	Jun 2023
+</pre>
+=== [[EPYC Embedded]] 9005 Series ===
+:;"Turin" • [[EPYC]] Embedded ({{amd|Zen 5|l=arch}}/5c)
+<pre>
+Model Name		Codename    Cores (C/T)	   Clock	Socket	     Process  L3 Cache	TDP	Released
+EPYC Embedded 9015	Turin		 8/16	 3.6/4.1 GHz	Socket SP5	4 nm	 64 MB	125 W	Oct 2024
+EPYC 9115		Turin		16/32	 2.6/4.1 GHz	Socket SP5	4 nm	 64 MB	125 W	Oct 2024
+EPYC Embedded 9135	Turin		16/32	3.65/4.3 GHz	Socket SP5	4 nm	 64 MB	200 W	Oct 2024
+EPYC 9175F		Turin		16/32	 4.2/5.0 GHz	Socket SP5	4 nm	512 MB	320 W	Oct 2024
+EPYC Embedded 9255	Turin		24/48	3.25/4.8 GHz	Socket SP5	4 nm	128 MB	200 W	Oct 2024
+EPYC 9275F		Turin		24/48	 4.1/4.8 GHz	Socket SP5	4 nm	256 MB	320 W	Oct 2024
+EPYC Embedded 9335	Turin		32/64	 3.0/4.4 GHz	Socket SP5	4 nm	128 MB	210 W	Oct 2024
+EPYC Embedded 9355	Turin		32/64	3.55/4.4 GHz	Socket SP5	4 nm	256 MB	280 W	Oct 2024
+EPYC Embedded 9355P	Turin		32/64	3.55/4.4 GHz	Socket SP5	4 nm	256 MB	280 W	Oct 2024
+EPYC 9365		Turin		36/72	 3.4/4.3 GHz	Socket SP5	4 nm	192 MB	300 W	Oct 2024
+EPYC 9375F		Turin		32/64	3.85/4.8 GHz	Socket SP5	4 nm	256 MB	320 W	Oct 2024
+EPYC Embedded 9455	Turin		48/96	3.15/4.4 GHz	Socket SP5	4 nm	256 MB	300 W	Oct 2024
+EPYC Embedded 9455P	Turin		48/96	3.15/4.4 GHz	Socket SP5	4 nm	256 MB	300 W	Oct 2024
+EPYC 9475F		Turin		48/96	3.65/4.8 GHz	Socket SP5	4 nm	256 MB	400 W	Oct 2024
+EPYC Embedded 9535	Turin		64/128	 2.4/4.3 GHz	Socket SP5	4 nm	256 MB	300 W	Oct 2024
+EPYC Embedded 9555	Turin		64/128	 3.2/4.4 GHz	Socket SP5	4 nm	256 MB	360 W	Oct 2024
+EPYC Embedded 9555P	Turin		64/128	 3.2/4.4 GHz	Socket SP5	4 nm	256 MB	360 W	Oct 2024
+EPYC 9565		Turin		72/144	3.15/4.3 GHz	Socket SP5	4 nm	384 MB	400 W	Oct 2024
+EPYC 9575F		Turin		64/128	 3.3/5.0 GHz	Socket SP5	4 nm	256 MB	400 W	Oct 2024
+EPYC 9645		Turin		96/192	 2.3/3.7 GHz	Socket SP5	3 nm	256 MB	320 W	Oct 2024
+EPYC Embedded 9655	Turin		96/192	 2.6/4.5 GHz	Socket SP5	4 nm	384 MB	400 W	Oct 2024
+EPYC Embedded 9655P	Turin		96/192	 2.6/4.5 GHz	Socket SP5	4 nm	384 MB	400 W	Oct 2024
+EPYC Embedded 9745	Turin		128/256	 2.4/3.7 GHz	Socket SP5	3 nm	256 MB	400 W	Oct 2024
+EPYC Embedded 9755	Turin		128/256	 2.7/4.1 GHz	Socket SP5	4 nm	512 MB	500 W	Oct 2024
+EPYC 9825		Turin		144/288	 2.2/3.7 GHz	Socket SP5	3 nm	384 MB	390 W	Oct 2024
+EPYC Embedded 9845	Turin		160/320	 2.1/3.7 GHz	Socket SP5	3 nm	320 MB	390 W	Oct 2024
+EPYC Embedded 9965	Turin		192/384	2.25/3.7 GHz	Socket SP5	3 nm	384 MB	500 W	Oct 2024
+</pre>
+=== [[EPYC Embedded]] 9006 Series ===
+:;"Venice" • [[EPYC]] Embedded ({{amd|Zen 6|l=arch}}/6c)
+:"Venice Classic" • "Venice Dense"
+=== [[EPYC Embedded]] Annapurna Series ===
+:;
 == Documents ==
@@ Line 96: / Line 472: @@
 == See also ==
+* AMD {{amd|Ryzen Embedded}}
 * Intel {{intel|Xeon D}}
 * Cavium {{cavium|ThunderX2}}

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