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{{armh title|Hunter-ELP|arch}}
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{{armh title|Cortex-X4 (Hunter-ELP)|arch}}
 
{{microarchitecture
 
{{microarchitecture
−
|atype=CPU
+
| atype = CPU
−
|name=Hunter-ELP
+
| name = Cortex-X4 (Hunter-ELP)
−
|designer=ARM Holdings
+
| codename = Cortex-X4
−
|manufacturer=TSMC
+
| core name = '''Cortex-X4'''
−
|predecessor=Cortex-X3
+
| designer = ARM Holdings
−
|predecessor link=arm holdings/microarchitectures/cortex-x3
+
| manufacturer = TSMC
−
|successor=Chaberton-ELP
+
| introduction = 2023
−
|successor link=arm holdings/microarchitectures/chaberton-elp
+
| process = 10 nm
−
|contemporary=Hunter
+
| process 2 = 7 nm
−
|contemporary link=arm holdings/microarchitectures/hunter
+
| process 3 = 5 nm
 +
| cores = 1
 +
| cores 2 = 2
 +
| cores 3 = 4
 +
| cores 4 = 6
 +
| cores 5 = 8
 +
| cores 6 = 10
 +
| cores 7 = 12
 +
| cores 8 = 14
 +
| type = Superscalar
 +
| type 2 = Pipelined
 +
| oooe = Yes
 +
| speculative = Yes
 +
| renaming = Yes
 +
| stages = 384
 +
| decode = 10-way
 +
| isa = ARMv9.2-A
 +
| feature = Hardware virtualization
 +
| extension = FPU
 +
| extension 2 = NEON
 +
| l1i = 64 KiB
 +
| l1i per = core
 +
| l1i desc = 4-way set associative
 +
| l1d = 64 KiB
 +
| l1d per = core
 +
| l1d desc = 4-way set associative
 +
| l2 = 2 MiB
 +
| l2 per = core
 +
| l2 desc = 8-way set associative
 +
| l3 = 32 MiB
 +
| l3 per = cluster
 +
| l3 desc = 16-way set associative
 +
| predecessor = '''Cortex-X3''' (Makalu-ELP)
 +
| predecessor link = arm holdings/microarchitectures/cortex-x3
 +
| successor = '''Cortex-X5''' (Chaberton-ELP)
 +
| successor link = arm holdings/microarchitectures/chaberton-elp
 +
| contemporary = '''Cortex-A720''' (Hunter)
 +
| contemporary link = arm holdings/microarchitectures/hunter
 +
| contemporary 2 = '''Cortex-A520''' (Hayes)
 +
| contemporary 2 link = arm holdings/microarchitectures/hayes
 
}}
 
}}
−
'''Hunter-ELP''' is the successor to the {{\\|Cortex-X3}}, a performance-enhanced version of the {{\\|Hunter}}, low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market.
+
 
 +
'''Cortex-X4''' ''(Hunter-ELP)'' is the successor to the '''{{\\|Cortex-X3}}''' ''(Makalu-ELP)'', a performance-enhanced version of the <br>'''Cortex-A720''' ''({{\\|Hunter}})'', low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market.
 +
 
 +
=== [[Cortex]]-X ===
 +
:;[[ARM]] • [[Cortex]]
 +
{| class="wikitable" style="text-align: center;
 +
|-
 +
! Year !! Cortex-X Core !! Cortex-A Core
 +
|-
 +
| [[2020]] || {{armh|Cortex-X1|l=arch}} (''{{armh|Hera|l=arch}}'') <br>{{armh|Cortex-X1C|l=arch}} (''{{armh|Hera-C|l=arch}}'') || {{armh|Cortex-A78|l=arch}} (''{{armh|Hercules|l=arch}}'') <!--<br>{{armh|Cortex-A78AE|l=arch}} (''{{armh|Hercules-AE|l=arch}}'')--> <br>{{armh|Cortex-A78C|l=arch}} (''{{armh|Hera Prime|l=arch}}'')
 +
|-
 +
| [[2021]] || {{armh|Cortex-X2|l=arch}} <br>(''{{armh|Matterhorn-ELP|l=arch}}'') || {{armh|Cortex-A710|l=arch}} (''{{armh|Matterhorn|l=arch}}'') <br>{{armh|Cortex-A510|l=arch}} (''{{armh|Klein|l=arch}}'')
 +
|-
 +
| [[2022]] || {{armh|Cortex-X3|l=arch}} (''{{armh|Makalu-ELP|l=arch}}'') || {{armh|Cortex-A715|l=arch}} (''{{armh|Makalu|l=arch}}'')
 +
|-
 +
| [[2023]] || {{armh|Cortex-X4|l=arch}} (''{{armh|Hunter-ELP|l=arch}}'') || {{armh|Cortex-A720|l=arch}} (''{{armh|Hunter|l=arch}}'') <br>{{armh|Cortex-A520|l=arch}} (''{{armh|Hayes|l=arch}}'')
 +
|-
 +
| [[2024]] || <s>{{armh|Cortex-X5|l=arch}} (''{{armh|Chaberton-ELP|l=arch}}'')</s> <br>{{armh|Cortex-X925|l=arch}} (''{{armh|Blackhawk|l=arch}}'') || {{armh|Cortex-A720AE|l=arch}} (''{{armh|Hunter-AE|l=arch}}'') <br>{{armh|Cortex-A725|l=arch}} (''{{armh|Chaberton|l=arch}}'')
 +
|-
 +
| [[2025]] || {{armh|Cortex-X930|l=arch}} (''{{armh|Travis|l=arch}}'') || {{armh|Cortex-A730|l=arch}} (''{{armh|Gelas|l=arch}}'') <br>{{armh|Cortex-A530|l=arch}} (''{{armh|Nevis|l=arch}}'')
 +
|-
 +
|}
 +
 
 +
== Architecture ==
 +
=== Key changes from {{\\|Cortex-X3}} ===
 +
The processor implements the following changes:
 +
* Instruction set ARMv9.2-A
 +
* Decode width: 10
 +
* Rename / Dispatch width: 10 (increased from 8)
 +
* Reorder buffer (ROB): 384 entries (increased from 320)
 +
* Execution ports: 21 (increased from 15)
 +
* Pipeline length: 10 (increased from 9)
 +
* Up to 2 MiB of private L2 cache (increased from 1 MiB)
 +
* Micro-operation (MOP) cache removed (previously 1.5k entries)
 +
* DSU-120
 +
** Up to 14 cores (up from 12 cores)
 +
** Up to 32 MiB of shared L3 cache (increased from 16 MiB)
 +
Performance claims:
 +
* 15% peak performance improvement over the Cortex-X3 in smartphones
 +
:(3.4GHz, 2MB L2, 8MB L3).
 +
* 13% IPC uplift over the Cortex-X3, when based on the same process, clock speed,
 +
:and L3 cache (but 2 MiB L2 vs 1 MiB L2) setup (also known as ISO-process).
 +
 
 +
=== Comparison ===
 +
 
 +
:;"Prime" core
 +
{| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;
 +
|-
 +
![[Microarchitecture|Architecture]]
 +
!{{armh|Cortex-A78|l=arch}}
 +
!{{armh|Cortex-X1|l=arch}}
 +
!{{armh|Cortex-X2|l=arch}}
 +
!{{armh|Cortex-X3|l=arch}}
 +
!{{armh|Cortex-X4|l=arch}}
 +
!{{armh|Cortex-X925|l=arch}}
 +
!{{armh|Cortex-X930|l=arch}}
 +
|-
 +
!Code name
 +
|''{{armh|Hercules|l=arch}}''
 +
|''Hera''
 +
|''{{armh|Matterhorn|l=arch}}-ELP''
 +
|''{{armh|Makalu|l=arch}}-ELP''
 +
|''{{armh|Hunter-ELP|l=arch}}''
 +
|''Blackhawk''
 +
|''Travis''
 +
|-
 +
!ISA
 +
| colspan="2" |[[ARMv8]].2-A
 +
| colspan="2" |ARMv9.0-A
 +
| colspan="3" |ARMv9.2-A
 +
|-
 +
!Peak clock speed
 +
| colspan="3" |~3.0&nbsp;GHz
 +
|~3.3&nbsp;GHz
 +
|~3.4&nbsp;GHz
 +
|~3.8&nbsp;GHz
 +
|~4.2&nbsp;GHz
 +
|-
 +
!Max in-flight
 +
|2x 160
 +
|2x 224
 +
|2x 288
 +
|2x 320
 +
|2x 384
 +
|2x 768
 +
|
 +
|-
 +
!L0 (Mops entries)
 +
|1536 <ref>{{cite book |title=Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence |url=https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging }}</ref>
 +
| colspan="2" |3072
 +
|1536
 +
|0
 +
|
 +
|
 +
|-
 +
!L1-I + L1-D
 +
|32+32 KiB
 +
| colspan="2" |64+64 KiB
 +
| colspan="2" |64+64 KiB
 +
|64+64 KiB
 +
|
 +
|-
 +
!L2
 +
|128–512 KiB
 +
| colspan="3" |0.25–1 MiB
 +
|0.5–2 MiB
 +
|2–3 MiB
 +
|
 +
|-
 +
!L3
 +
| colspan="2" |0–8 MiB <ref>{{cite book |last=Schor |first=David |date=2020-05-26 |title=Arm Cortex-X1: The First From The Cortex-X Custom Program |url=https://fuse.wikichip.org/news/3543/arm-cortex-x1-the-first-from-the-cortex-x-custom-program/ |website=WikiChip Fuse }}</ref>
 +
| colspan="2" |0–16 MiB
 +
| colspan="2" |0–32 MiB
 +
|
 +
|-
 +
!Decode width
 +
|4
 +
| colspan="2" |5
 +
|6
 +
|10 <ref>{{cite book |date=2023-05-29 |title=Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive |url=https://www.androidauthority.com/arm-cortex-x4-explained-3328008/ |website=Android Authority}}</ref>
 +
|10
 +
|
 +
|-
 +
!Dispatch
 +
|6/cycle
 +
| colspan="3" |8/cycle
 +
| colspan="2" |10/cycle
 +
|
 +
|-
 +
|}
 +
 
 +
== Processors ==
 +
<!--
 +
* [[Snapdragon 6]] Gen 4 (SM6650) • 4nm (TSMC N4P)
 +
:1× @2.3GHz Kryo Prime (Cortex-A720) +
 +
:3× @2.2GHz Kryo Gold (Cortex-A720) +
 +
:4× @1.8GHz Kryo Silver (Cortex-A520) -->
 +
* [[Snapdragon 7]]+ Gen 3 (SM7675-AB) • 4nm (TSMC N4P)
 +
:1× 2.8 GHz Kryo Prime (Cortex-X4) +
 +
:4× 2.6 GHz Kryo Gold (Cortex-A720) +
 +
:3× 1.9 GHz Kryo Silver (Cortex-A520) <!--
 +
* [[Snapdragon 7]]s Gen 3 (SM7635) • 4nm
 +
:1× @2.5GHz Kryo Prime (Cortex-A720) +
 +
:3× @2.4GHz Kryo Gold (Cortex-A720) +
 +
:4× @1.8GHz Kryo Silver (Cortex-A520) -->
 +
* [[Snapdragon 8]] Gen 3 (SM8650-AB) • 4 nm (TSMC N4P)
 +
:1× @3.3GHz Kryo Prime (Cortex-X4) +
 +
:3× @3.15GHz Kryo Gold (Cortex-A720) +
 +
:2× @2.96GHz Kryo Gold (Cortex-A720) +
 +
:2× @2.27GHz Kryo Silver (Cortex-A520)
 +
* [[Snapdragon 8]] Gen 3 (SM8650-AA) •  Q4 2024
 +
:1× @3.05GHz Kryo Prime (Cortex-X4) +
 +
:5× @2.96GHz Kryo Gold (Cortex-A720) +
 +
:2× @2.04GHz Kryo Silver (Cortex-A520)
 +
* [[Snapdragon 8]] Gen 3 for Galaxy (SM8650-AC)
 +
:1× @3.4GHz Kryo Prime (Cortex-X4) +
 +
:3× @3.15GHz Kryo Gold (Cortex-A720) +
 +
:2× @2.96GHz Kryo Gold (Cortex-A720) +
 +
:2× @2.27GHz Kryo Silver (Cortex-A520)
 +
* [[Snapdragon 8]]s Gen 3 (SM8635)
 +
:1× @3.0GHz Kryo Prime (Cortex-X4) +
 +
:4× @2.8GHz Kryo Gold (Cortex-A720) +
 +
:3× @2.0GHz Kryo Silver (Cortex-A520)
 +
 
 +
== References ==

Latest revision as of 09:01, 13 May 2025

Edit Values
Cortex-X4 (Hunter-ELP) µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
Introduction2023
Process10 nm, 7 nm, 5 nm
Core Configs1, 2, 4, 6, 8, 10, 12, 14
Pipeline
TypeSuperscalar, Pipelined
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages384
Decode10-way
Instructions
ISAARMv9.2-A
ExtensionsFPU, NEON
Cache
L1I Cache64 KiB/core
4-way set associative
L1D Cache64 KiB/core
4-way set associative
L2 Cache2 MiB/core
8-way set associative
L3 Cache32 MiB/cluster
16-way set associative
Cores
Core NamesCortex-X4
Succession
Contemporary
Cortex-A720 (Hunter)
Cortex-A520 (Hayes)

Cortex-X4 (Hunter-ELP) is the successor to the Cortex-X3 (Makalu-ELP), a performance-enhanced version of the
Cortex-A720 (Hunter), low-power high-performance ARM microarchitecture designed by Arm for the mobile market.

Cortex-X[edit]

ARM • Cortex
Year Cortex-X Core Cortex-A Core
2020 Cortex-X1 (Hera)
Cortex-X1C (Hera-C) 		Cortex-A78 (Hercules)
Cortex-A78C (Hera Prime)
2021 Cortex-X2
(Matterhorn-ELP) 		Cortex-A710 (Matterhorn)
Cortex-A510 (Klein)
2022 Cortex-X3 (Makalu-ELP) Cortex-A715 (Makalu)
2023 Cortex-X4 (Hunter-ELP) Cortex-A720 (Hunter)
Cortex-A520 (Hayes)
2024 Cortex-X5 (Chaberton-ELP)
Cortex-X925 (Blackhawk) 		Cortex-A720AE (Hunter-AE)
Cortex-A725 (Chaberton)
2025 Cortex-X930 (Travis) Cortex-A730 (Gelas)
Cortex-A530 (Nevis)

Architecture[edit]

Key changes from Cortex-X3[edit]

The processor implements the following changes:

  • Instruction set ARMv9.2-A
  • Decode width: 10
  • Rename / Dispatch width: 10 (increased from 8)
  • Reorder buffer (ROB): 384 entries (increased from 320)
  • Execution ports: 21 (increased from 15)
  • Pipeline length: 10 (increased from 9)
  • Up to 2 MiB of private L2 cache (increased from 1 MiB)
  • Micro-operation (MOP) cache removed (previously 1.5k entries)
  • DSU-120
    • Up to 14 cores (up from 12 cores)
    • Up to 32 MiB of shared L3 cache (increased from 16 MiB)

Performance claims:

  • 15% peak performance improvement over the Cortex-X3 in smartphones
(3.4GHz, 2MB L2, 8MB L3).
  • 13% IPC uplift over the Cortex-X3, when based on the same process, clock speed,
and L3 cache (but 2 MiB L2 vs 1 MiB L2) setup (also known as ISO-process).

Comparison[edit]

"Prime" core
Architecture Cortex-A78 Cortex-X1 Cortex-X2 Cortex-X3 Cortex-X4 Cortex-X925 Cortex-X930
Code name Hercules Hera Matterhorn-ELP Makalu-ELP Hunter-ELP Blackhawk Travis
ISA ARMv8.2-A ARMv9.0-A ARMv9.2-A
Peak clock speed ~3.0 GHz ~3.3 GHz ~3.4 GHz ~3.8 GHz ~4.2 GHz
Max in-flight 2x 160 2x 224 2x 288 2x 320 2x 384 2x 768
L0 (Mops entries) 1536 [1] 3072 1536 0
L1-I + L1-D 32+32 KiB 64+64 KiB 64+64 KiB 64+64 KiB
L2 128–512 KiB 0.25–1 MiB 0.5–2 MiB 2–3 MiB
L3 0–8 MiB [2] 0–16 MiB 0–32 MiB
Decode width 4 5 6 10 [3] 10
Dispatch 6/cycle 8/cycle 10/cycle

Processors[edit]

1× 2.8 GHz Kryo Prime (Cortex-X4) +
4× 2.6 GHz Kryo Gold (Cortex-A720) +
3× 1.9 GHz Kryo Silver (Cortex-A520)
1× @3.3GHz Kryo Prime (Cortex-X4) +
3× @3.15GHz Kryo Gold (Cortex-A720) +
2× @2.96GHz Kryo Gold (Cortex-A720) +
2× @2.27GHz Kryo Silver (Cortex-A520)
1× @3.05GHz Kryo Prime (Cortex-X4) +
5× @2.96GHz Kryo Gold (Cortex-A720) +
2× @2.04GHz Kryo Silver (Cortex-A520)
1× @3.4GHz Kryo Prime (Cortex-X4) +
3× @3.15GHz Kryo Gold (Cortex-A720) +
2× @2.96GHz Kryo Gold (Cortex-A720) +
2× @2.27GHz Kryo Silver (Cortex-A520)
1× @3.0GHz Kryo Prime (Cortex-X4) +
4× @2.8GHz Kryo Gold (Cortex-A720) +
3× @2.0GHz Kryo Silver (Cortex-A520)

References[edit]

  1. ↑ Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence.
  2. ↑ Schor, David (2020-05-26). Arm Cortex-X1: The First From The Cortex-X Custom Program.
  3. ↑ (2023-05-29) Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/hunter-elp&oldid=103425"
Facts about "Cortex-X4 (Hunter-ELP) - Microarchitectures - ARM"
RDF feed
codenameCortex-X4 (Hunter-ELP) +
core count1 +, 2 +, 4 +, 6 +, 8 +, 10 +, 12 + and 14 +
designerARM Holdings +
first launched2023 +
full page namearm holdings/microarchitectures/hunter-elp +
instance ofmicroarchitecture +
instruction set architectureARMv9.2-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-X4 (Hunter-ELP) +
pipeline stages384 +
process10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) +