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Difference between revisions of "arm holdings/microarchitectures/neoverse n2"
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{{armh title|Zeus|arch}}
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{{armh title|Neoverse N2|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
−
|name=Zeus
+
|name=Neoverse N2
 +
|codename=Perseus
 +
|features={{\\|Perseus}}
 
|designer=ARM Holdings
 
|designer=ARM Holdings
 
|manufacturer=TSMC
 
|manufacturer=TSMC
−
|introduction=2020
+
|introduction=September 22, 2020
 
|process=7 nm
 
|process=7 nm
 +
|core name=[[Neoverse]] (Genesis)
 +
|cores=4
 +
|cores 2=8
 +
|cores 3=16
 +
|cores 4=32
 +
|cores 5=64
 +
|cores 6=96
 +
|cores 7=128
 +
|type=Superscalar
 +
|type 2=Superpipeline
 
|oooe=Yes
 
|oooe=Yes
 
|speculative=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|renaming=Yes
−
|predecessor=Ares
+
|stages=13
−
|predecessor link=arm_holdings/microarchitectures/ares
+
|decode=5-way
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|successor=Poseidon
+
|isa=ARMv9.0-A
−
|successor link=arm_holdings/microarchitectures/poseidon
+
|extension=SVE2
 +
|predecessor=Neoverse N1
 +
|predecessor link=arm_holdings/microarchitectures/neoverse n1
 +
|predecessor 2=Neoverse E1
 +
|predecessor 2 link=arm_holdings/microarchitectures/neoverse e1
 +
|predecessor 3=Neoverse V1
 +
|predecessor 3 link=arm_holdings/microarchitectures/neoverse v1
 +
|successor=Neoverse N3
 +
|successor link=arm_holdings/microarchitectures/neoverse n3
 +
|successor 2=Neoverse E3
 +
|successor 2 link=arm_holdings/microarchitectures/neoverse e3
 +
|successor 3=Neoverse V3
 +
|successor 3 link=arm_holdings/microarchitectures/poseidon
 
}}
 
}}
−
'''Zeus''' is the successor to {{\\|Ares}}, a high-performance Constantinopolitan Greek
+
 
−
[[File:7nm / Ares|thumb]]
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'''[[Neoverse N2]]''' (codename ''"{{\\|Perseus}}"'') is the successor to [[Neoverse N1]] (''{{\\|Ares}}''), a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market.  
−
[[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
+
 
 +
This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  
 
== History ==
 
== History ==
−
[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]]
+
[[File:arm server roadmap techcon 2018.jpg|thumb|left|Arm's server roadmap.]]
−
Zeus was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
+
 
 +
{{\\|Ares}} was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon [[2018]] keynote.
  
 
== Release Dates ==
 
== Release Dates ==
−
Ares is expected to show up in products around 2020.
+
[[Neoverse N2]] is expected to show up in products around [[2020]]. It was officially announced by [[Arm]] on September 22, [[2020]].
 +
 
 +
On August 28, [[2023]], [[Arm]] announced the [[Neoverse]] CSS N2 (Genesis), a customizable CPU subsystem implementation by [[Arm]] to reduce the time to market for customers.
  
 
== Process Technology ==
 
== Process Technology ==
−
Zeus specifically designed takes advantage of the power and area advantages of the [[7 nm process|7nm+ process]].
+
[[Neoverse N2]] specifically designed takes advantage of the power and area advantages of the [[7 nm process|7nm+ process]].
 +
{{see also|Neoverse}}
 +
 
 +
== All Neoverse N2 Processors ==
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 
 +
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc4 tc6 tc9">
 +
{{comp table header|main|9:List of Neoverse N2-based Processors}}
 +
{{comp table header|main|7:Main processor|2:Integrated Graphics}}
 +
{{comp table header|cols|Part number|Family|Arch|Cores|%Frequency|Process|Launched|GPU|%Frequency}}
 +
{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Neoverse N2]]
 +
|?full page name
 +
|?name
 +
|?model number
 +
|?family
 +
|?microarchitecture
 +
|?core count
 +
|?base frequency#GHz
 +
|?process
 +
|?first launched
 +
|?integrated gpu
 +
|?integrated gpu base frequency
 +
|format=template
 +
|template=proc table 3
 +
|userparam=11
 +
|mainlabel=-
 +
|valuesep=,
 +
}}
 +
{{comp table count|ask=[[Category:all microprocessor models]] [[microarchitecture::Neoverse N2]]}}
 +
</table>
 +
{{comp table end}}
  
 
== Architecture ==
 
== Architecture ==
−
{{future information}}
+
The [[Neoverse N2]] (codename "Perseus") is derived from the [[Cortex-A710]] and implements the ARMv9.0-A instruction set.
  
−
=== Key changes from {{\\|Ares}} ===
+
=== Key changes from {{\\|Neoverse N1}} ===
 +
* ARMv9.0-A instruction set (from ARMv8.2-A)
 
* [[7nm+ process]] (from [[7nm]])
 
* [[7nm+ process]] (from [[7nm]])
 +
* CMN-700 mesh interconnect (from CMN-600)
 +
* BTB capacity: 8K entries
 +
* Micro-op cache: 1536 entries
 +
* Rename / Dispatch width: 5
 +
* ROB: 160+ entry
 +
* Pipeline depth: 10 cycles
 +
* Execution ports: 13
 +
* SVE2 support
  
 
{{expand list}}
 
{{expand list}}
 +
 +
=== Models ===
 +
:;[[Microsoft]] • [[Alibaba]]
 +
*'''Microsoft Azure Cobalt 100''' • 128-core [[Neoverse N2]] CPU
 +
*'''Alibaba Yitian 710''' • [[Neoverse N2]] CPU
  
 
== Bibliography ==
 
== Bibliography ==
 
* Drew Henry keynote, TechCon 2018 keynote.
 
* Drew Henry keynote, TechCon 2018 keynote.
 +
 +
[[Category:arm holdings]]

Latest revision as of 22:56, 23 March 2025

Edit Values
Neoverse N2 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionSeptember 22, 2020
Process7 nm
Core Configs4, 8, 16, 32, 64, 96, 128
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages13
Decode5-way
Instructions
ISAARMv9.0-A
FeaturesPerseus
ExtensionsSVE2
Cores
Core NamesNeoverse (Genesis)
Succession

Neoverse N2 (codename "Perseus") is the successor to Neoverse N1 (Ares), a high-performance ARM microarchitecture designed by ARM Holdings for the server market.

This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

History[edit]

Arm's server roadmap.

Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.

Release Dates[edit]

Neoverse N2 is expected to show up in products around 2020. It was officially announced by Arm on September 22, 2020.

On August 28, 2023, Arm announced the Neoverse CSS N2 (Genesis), a customizable CPU subsystem implementation by Arm to reduce the time to market for customers.

Process Technology[edit]

Neoverse N2 specifically designed takes advantage of the power and area advantages of the 7nm+ process.

See also: Neoverse


All Neoverse N2 Processors[edit]

 List of Neoverse N2-based Processors
 Main processorIntegrated Graphics
ModelPart numberFamilyArchCoresFrequencyProcessLaunchedGPUFrequency
Count: 0

Architecture[edit]

The Neoverse N2 (codename "Perseus") is derived from the Cortex-A710 and implements the ARMv9.0-A instruction set.

Key changes from Neoverse N1[edit]

  • ARMv9.0-A instruction set (from ARMv8.2-A)
  • 7nm+ process (from 7nm)
  • CMN-700 mesh interconnect (from CMN-600)
  • BTB capacity: 8K entries
  • Micro-op cache: 1536 entries
  • Rename / Dispatch width: 5
  • ROB: 160+ entry
  • Pipeline depth: 10 cycles
  • Execution ports: 13
  • SVE2 support

This list is incomplete; you can help by expanding it.

Models[edit]

Microsoft • Alibaba

Bibliography[edit]

  • Drew Henry keynote, TechCon 2018 keynote.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/neoverse_n2&oldid=103053"
Facts about "Neoverse N2 - Microarchitectures - ARM"
RDF feed
codenameNeoverse N2 +
core count4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 +
designerARM Holdings +
first launchedSeptember 22, 2020 +
full page namearm holdings/microarchitectures/neoverse n2 +
instance ofmicroarchitecture +
instruction set architectureARMv9.0-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse N2 +
pipeline stages13 +
process7 nm (0.007 μm, 7.0e-6 mm) +