{{intel title|Skylake|arch}}

| name             = Skylake

| designer         = Intel

| manufacturer     = Intel

| introduction     = August 5, 2015

| process         = 14 nm

| cores           = 2

| cores 2         = 4

| cores 3         = 6

| cores 4         = 8

| cores 5         = 10

| pipeline        = Yes

| type            = Superscalar

| OoOE            = Yes

| speculative      = Yes

| renaming        = Yes

| inst            = Yes

| feature          =  

| extension        = MOVBE

| extension 2      = MMX

| extension 3      = SSE

| extension 4      = SSE2

| extension 5      = SSE3

| extension 6      = SSSE3

| extension 7      = SSE4.1

| extension 8      = SSE4.2

| extension 9      = POPCNT

| extension 10    = AVX

| extension 11    = AVX2

| extension 12    = AES

| extension 13    = PCLMUL

| extension 14    = FSGSBASE

| extension 15    = RDRND

| extension 16    = FMA3

| extension 17    = F16C

| extension 18    = BMI

| extension 19    = BMI2

| extension 20    = VT-x

| extension 21    = VT-d

| extension 22    = TXT

| extension 23    = TSX

| extension 24    = RDSEED

| extension 25    = ADCX

| extension 26    = PREFETCHW

| extension 27    = CLFLUSHOPT

| extension 28    = XSAVE

| extension 29    = SGX

| extension 30    = MPX

| extension 31    = AVX-512

| l1d desc        = 8-way set associative

| l2              = 256 KiB

| l2 per          = core

| l2 desc          = 4-way set associative

| l3              = 2 MiB

| l3 per          = core

| core names      = Yes

| core name        = Skylake Y

| core name 2     = Skylake U

| core name 3      = Skylake H

| core name 4      = Skylake S

| core name 5      = Skylake X

| core name 6      = Skylake W

| succession      = Yes

| predecessor      = Broadwell

| predecessor link = intel/microarchitectures/broadwell

| successor        = Kaby Lake

'''Skylake''' ('''SKL''') is [[Intel]]'s successor to {{\\|Broadwell}}, a [[14 nm process]] [[microarchitecture]] for mainstream desktops, servers, and mobile devices. Skylake succeeded the short-lived {{\\|Broadwell}} which experienced severe delays. Skylake is the "Architecture" phase as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]].

For desktop and mobile, Skylake is branded as 6th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v5}}, {{intel|Xeon E5|Xeon E5 v5}}, and {{intel|Xeon E7|Xeon E7 v5}}.

== Codenames ==

| Skylake Y || SKL-Y || 2-in-1s detachable, tablets, and computer sticks

| Skylake U || SKL-U || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

| Skylake H || SKL-H || Ultimate mobile performance, mobile workstations

| Skylake S || SKL-S || Desktop performance to value, AiOs, and minis

| Skylake X || SKL-X || High-end desktops & enthusiasts market

| Skylake W || SKL-W || Workstations

== Process Technology ==

{{main|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}}

Overall Skylake builds upon Intel's previous microarchitecture, {{\\|Broadwell}}, but includes a more beefed up front end, more optimized execution engine, and numerous number of smaller enhancements. Intel designed Skylake to encompass a wide range of devices and applications with a large emphasis on mobile with models ranging from as low as 4.5 W to as high as 100 W.

* Bus/Interface to Chipset

** {{intel|Direct Media Interface|DMI 3.0}} (from 2.0)

*** Skylake S and Skylake H cores, connected by 4-lane DMI 3.0

*** Skylake Y and Skylake U cores have chipset in the same package (simplified {{intel|on Package I/O|OPIO}})

*** Increase in transfer rate from 5.0 GT/s to  8.0 GT/s (~3.93GB/s up from 2GB/s) per lane

*** Limits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset

* Front End

** Larger legacy pipeline delivery (5 µOPs, up from 4)

** Larger IDQ delivery (6 µOPs, up from 4)

** 2.28x larger allocation queue (64/thread, up from 28/thread)

** Improved [[branch prediction unit]]

* Execution Engine

** Larger [[re-order buffer]] (224 entries, up from 192)

** Larger scheduler (97 entries, up from 64)

*** Larger Integer Register File (180 entries, up from 160)

** Larger store buffer (56 entries, up from 42)

* Most ALU operations have 4 op/cycle 1 for 8 and 32-bit registers. 64-bit ops are still limited to 3 op/cycle. (16-bit throughput varies per op, can be 4, 3.5 or 2 op/cycle).

* MOVSX and MOVZX have 4 op/cycle throughput for 16->32 and 32->64 forms, in addition to Haswell's 8->32, 8->64 and 16->64 bit forms.

* ADC and SBB have throughput of 1 op/cycle, same as Haswell.

* Vector moves have throughput of 4 op/cycle (move elimination).

* Not only zeroing vector vpXORxx and vpSUBxx ops, but also vPCMPxxx on the same register, have throughput of 4 op/cycle.

* Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5, now both are 4.

* Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle.

* Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle.

* Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle.

===== New GPU Features & Changes =====

 

In {{\\|Broadwell}}, the [[eDRAM]] was statically attached to the LLC (last level cache, L3$), effectively stealing half a [[Mebibyte]] per core in the process, but behaving as an architectural true level 4 cache. This was fundamentally changed in Skylake. In Skylake, Intel removed the [[eDRAM]] from the LLC to its own array, re-freeing the 512 KiB (hence the 1.5 MiB/core in Broadwell and 2 MiB back in Skylake), but also removing the undesired dependency between the capacity of the eDRAM and the number of cores. Skylake's cache is effectively no longer a true level 4 cache but rather a memory side cache. This has a number of benefits such as that each and every memory access that goes through the [[memory controller]] gets looked up in the eDRAM. On a satisfied hit, the value is obtained from there. On a miss, a value gets allocated and stored in the eDRAM (subject to a number of restrictions, for example no I/O devices requests get cached on the eDRAM).

 

{| class="wikitable"

! colspan="2" | Skylake vs Broadwell eDRAM Architecture

 

The new eDRAM changes mean it's no longer architectural - capable of caching any data (including "unreachable memory", display engines, effectively any memory transfer not bound by software restrictions) and is entirely invisible to software (one exception noted later) in terms of coherency (note that no flushing is thus necessary to maintain coherency), ordering, or other organizational details. For optimal graphics performance, the graphics driver may decide to limit certain memory accesses to only the eDRAM, only the LLC, or in both of them.

 

* Improved underlying implementation of the memory QoS for higher resolution displays and the integrated [[image signal processor]] (ISP)

* Up to 24 EUs GT2 (same as {{\\|Haswell}}); 48 EUs for GT3, and up to 72 EUs on {{intel|Iris Pro Graphics}}

 

:{| class="wikitable"

* {{x86|SGX|<code>SGX</code>}} - Software Guard Extensions

* {{x86|AVX-512|<code>AVX-512</code>}} - Advanced Vector Extensions 512 (Only on high-end {{intel|Xeon}} models (SKX))

===="Speed Shift" (new power management)====

Intel introduced '''{{intel|Speed Shift}}''' with Skylake, a new methodology for quickly alternating core frequencies in response to power loads. Intel introduced a new unit called [[Package Control Unit]] (PCU) which is effectively a full fledged [[microcontroller]] (containing power management logic and [[firmware]]) that collects and tracks many internal SoC statistics as well as external power telemetry (e.g. Psys and iMon). PCU is also capable of interfacing with the OS, [[BIOS]], and {{intel|Dynamic Platform and Thermal Framework|DPTF}}. Speed Shift improves the performance of frequency shifting by off-loading the control from the [[operating system]] to the PCU.

Speed Shift effectively eliminates the need for the OS to manages the P-states - though it does have the final say (unless special exceptions occur such as thermal throttling). Intel calls this "autonomous P-state", allowing Speed Shift to kick in in a matter of just ~1 millisecond (whereas the operating system-based p-states control can be as slow as 30 ms). Speed Shift effectively reduces hitting peak frequency in around ~30 ms from over 100 ms (OS-based implementation as before). While Speed Shift is capable of full range shift by default, the operating system can set the minimum QoS, maximum frequency and power/performance hints when desired. The final result should be higher performance and specially higher responsiveness at power constrained form factors.

===== Power of System (Psys) =====

Psys (Power of System) is a way for the PCU to monitor the performance and the total platform power provided to the chip. The chip uses a number of autonomous algorithms (one for "Low Range" and one for "High Range"). The Low Range algorithm frequency is lowered to conserve energy. Algorithm is capable of overriding the low P state - a state calculated ever millisecond based on the active workload and system characteristics. The High Range algorithm deals with elevating frequency for the benefit of increase performance (at the cost of increase energy/inefficiency). The exact ratio of ΔPower/ΔPerformance ≤ αPreference can be finely controlled via the OS and user preferences.

 

 

 

=== Block Diagram ===

[[File:skylake block diagram.svg]]

*** 32 KiB 8-way set associative

**** 64 B line size

*** 32 KiB 8-way set associative

*** 64 B line size

*** 4 cycles for fastest load-to-use

*** 64 Bytes/cycle load bandwidth

*** 32 Bytes/cycle store bandwidth

*** unified, 256 KiB 4-way set associative

*** 64B/cycle bandwidth to L1$

** L3 Cache:

**** Read: 32 B/cycle (@ ring clock)

** L4 Cache:

*** 128 MiB

Skylake TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB.

**** dynamic partition; divided between the two threads

**** 8 entries; fully associative

**** fixed partition; divided between the two threads

Skylake, like its predecessor {{\\|Broadwell}}, also has a dual-threaded and out-of-order pipeline.

Skylake had its front-end bandwidth of µOPs deliver to the execution engine increase. The µOPs Cache now delivers 6 µOPs per clock (previously the cache only delivered 4 µOPs/clock), likewise the decoders now deliver 5 µOPs/clock (previously they were capable of only 4µOPs/clock). The [[branch predictor]] has also been improved. The branch predictor now has reduced penalty (i.e. lower latency) for wrong direct jump target prediction. Additionally, the instruction fetch unit is capable of looking much deeper into the stream of bytes. Finally, the allocation queue which interfaces between the front-end ([[in-order]]) and the [[execution engine]] ([[out-of-order]]) itself has been more than doubled to accommodate 64/thread (from 28/thread in Broadwell).

Like the front-end, the execution engine's ReOrder buffer has been increased to 224 entries (from 192 in Broadwell) in order to extract more [[instruction-level parallelism]]. Likewise the scheduler itself was increased considerably to 97 entries (from 64 in Broadwell). The [[integer]] [[register file]] was also slightly increased from 160 entries to 180.

The scheduler had its ports rearranged to better balance various instructions. For example, divide and [[sqrt]] instructions latency and throughput were improved. The latency and throughput of [[floating point]] ADD, MUL, and FMA were made uniformed at 4 cycles with a throughput of 2 ops/clock. Likewise the latency of {{x86|AES|AES instructions}} were significantly reduced from 7 cycles down to 4.

{| class="wikitable" style="text-align: center;"

! colspan="8" | Dispatch Ports

! Port 0 !! Port 1 !! Port 2 !! Port 3 !! Port 4 !! Port 5 !! Port 6 !! Port 7

| ALU<br>Vec ALU || ALU<br>Fast LEA<br>Vec ALU || Load Addr<br>Store Addr || Load Addr<br>Store Addr || Store Data || ALU<br>Fast LEA<br>Vec ALU || ALU<br>Shift || Store Addr

{| class="wikitable"

| BM<info>Bit Manipulation</info> || 2 || andn, bextr, blsi, blsmsk, bzhi, etc

Skylake has had its store buffer enlarged to 56 entries (up from 42 in {{\\|Broadwell}}). Special care was taken to reduce the penalty for page-split loads: previously scenarios involving page-split loads were thought to be rarer than they actually are. This was addressed in Skylake with page-split loads are now made equal to other splits loads. Expect page split load penalty down to 5 cycles from 100 cycles in Broadwell. The average latency to forward a load to store has also been improved and stores that miss in the L1$ generate L2$ requests to the next level cache much earlier in Sklake than before.

The bandwidth from L2$ to L3$ has been improved and write bandwidth from L2$ to L3$ has also been increased from 4 cycles/line to 2 cycles/line.

Quad-core Skylake die:

: [[File:skylake (quad-core).png|850px]]

: [[File:skylake (quad-core) (annotated).png|850px]]

| count = 4

| width = 650px

'''{{x86|MPX}}''' - Memory Protection Extensions

* {{x86|BNDCL}}

* {{x86|BNDCN}}

* {{x86|BNDCU}}

* {{x86|BNDLDX}}

* {{x86|BNDMK}}

'''{{x86|AVX-512}}''' - Advanced Vector Extensions 512; These instructions can only be found on selected high-end {{intel|Xeon}} models (codename '''SKX''')