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{{core | {{core | ||
|name=Genoa | |name=Genoa | ||
− | |no image= | + | |no image=Yes |
|developer=AMD | |developer=AMD | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
+ | |first announced= | ||
+ | |first launched=November 10, 2022 | ||
|isa=x86-64 | |isa=x86-64 | ||
|microarch=Zen 4 | |microarch=Zen 4 | ||
|word=64 bit | |word=64 bit | ||
|proc=5 nm | |proc=5 nm | ||
+ | |proc 2=6 nm | ||
|tech=CMOS | |tech=CMOS | ||
+ | |package name 1=amd,socket_sp5 | ||
|predecessor=Milan | |predecessor=Milan | ||
|predecessor link=amd/cores/milan | |predecessor link=amd/cores/milan | ||
+ | |successor= | ||
+ | |successor link= | ||
}} | }} | ||
− | '''Genoa''' is codename | + | '''Genoa''' is the codename of [[AMD]]'s {{amd|EPYC#9004 Series (Zen 4)|EPYC 9004 series}} of high-performance microprocessors based on the {{amd|Zen 4|l=arch}} microarchitecture for single- and dual-socket server platforms. Launched in November 2022 it succeeded the third generation of EPYC processors, the {{amd|EPYC#7003 Series (Zen 3)|EPYC 7003}} "{{\\|Milan}}" series.<ref name="pr20221110">[https://ir.amd.com/news-events/press-releases/detail/1100/offering-unmatched-performance-leadership-energy "Offering Unmatched Performance, Leadership Energy Efficiency and Next-Generation Architecture, AMD Brings 4th Gen AMD EPYC™ Processors to The Modern Data Center"] (Press release). AMD.com. November 10, 2022. Retrieved February 2022.</ref> |
+ | EPYC 9004 processors identify as members of {{amd|CPUID#Family 25 (19h)|AMD CPU Family 19h, Model 11h}} (engineering samples as Model 10h). | ||
− | {{future | + | == Overview == |
+ | {{empty section}} | ||
+ | |||
+ | === Memory Interface === | ||
+ | The "Genoa" I/O die integrates 12 {{wp|DDR5 SDRAM|DDR5}} memory controllers and interfaces, three per I/O die quadrant, which support raw data rates up to 4800 MT/s. Up to 2 DIMMs per channel are supported. Each channel has two independent 40-bit (32 data, 8 ECC) DDR5 subchannels. The memory controllers support {{wp|ECC memory}} (80b x4, 80b x8, and 72b x4 ECC, i.e. EC4 and EC8 DIMMs) and DDR5 DRAMs with 16/24/32 Gb density on the following DIMM types: | ||
+ | |||
+ | * {{abbr|SR}}/{{abbr|DR}} {{abbr|RDIMM}} built with x4 and x8 DDR5 devices (1Rx4 16/32/48 GiB, 1Rx8 16/24 GiB, 2Rx4 64/80/96 GiB, 2Rx8 32/40/48 GiB) | ||
+ | * 4R/8R {{abbr|LRDIMM}} ({{abbr|2S2R|<nowiki>4 Rank = Dual Rank × 2 dies stacked</nowiki>}}, 2S4R) | ||
+ | * 4R/8R/16R {{abbr|3DS DIMM}} built with x4 devices (2S2Rx4 128/192 GiB, 2S4Rx4 256/384 GiB, 2S8Rx4 512 GiB) | ||
+ | |||
+ | {{abbr|UDIMM}}, {{abbr|NVDIMM-N}}, {{abbr|NVDIMM-P}} types are not supported. | ||
+ | |||
+ | The maximum total memory capacity is 6 TiB per socket using 3DS DIMMs of e.g. 12 × 512 GiB capacity. | ||
+ | |||
+ | === Input/Output Interfaces === | ||
+ | The "Genoa" I/O die integrates eight 16-lane {{wp|PCI Express|PCIe}} Gen 5 (32 GT/s) controllers and interfaces. Link bifurcation permits configuration of the PCIe lanes as x16, x8, x4, x2, or x1 wide independent links, e.g. 1x8 + 1x4 + 4x1. Each controller supports up to nine PCIe links, or up to eight if any lane is is configured as SATA link, and per link lane reversal which can simplify signal routing on the motherboard. | ||
+ | |||
+ | Two supplementary I/O interfaces support the PCIe Gen 3 (8 GT/s) protocol. Each of these interfaces has four lanes configurable x4, x2, x1 and supports up to four links. | ||
+ | |||
+ | On dual-socket systems four, or optionally three depending on bandwidth requirements, x16 links are repurposed for {{amd|Infinity Fabric|cache coherent inter-socket traffic}}. The raw data rate of these {{abbr|xGMI}} links is also 32 GT/s. A {{abbr|WAFL}} link occupying two lanes on one of the supplementary interfaces connects the Control Fabrics of each processor, i.e. the {{abbr|PSP}}, {{abbr|SMU}}s and other IPs, primarily for temperature monitoring, power and frequency control. | ||
+ | |||
+ | In summary on 1P systems up to 128 PCIe Gen 5 and 8 PCIe Gen 3 lanes are available for I/O. On 2P systems up to 64 or 80 PCIe Gen 5 and 6 PCIe Gen 3 lanes per socket. | ||
+ | |||
+ | Up to four of the x16 interfaces can be configured as cache-coherent {{wp|Compute Express Link|Compute Express Link}}. "Genoa" supports version 1.1 of the protocol, specifically accelerators without local memory such as a {{abbr|NIC}} using the CXL.io and CXL.cache protocols, and memory expanders using the CXL.io and CXL.memory protocols. One accelerator per interface can be attached with a 1x16 or 1x8 link, or up to four memory expanders with 1x16, 2x8, or 4x4 links. Unused lanes are available for PCIe and configurable 1x8, 2x4, or 3x4. | ||
+ | |||
+ | The lanes on two x16 interfaces can be configured as SATA Gen 3 links, unused lanes are available for PCIe. On 1P systems up to 32 SATA ports total are available, on 2P systems 16 ports per socket as one of the interfaces is reserved for xGMI duty. | ||
+ | |||
+ | The processors integrate a controller hub with four USB 3.2 Gen 1×1 (5 Gb/s) ports (the I/O die actually implements USB 3.2 Gen 2×1<ref name="AMD-55901-11B1-*">{{cite techdoc|title=Processor Programming Reference (PPR) for AMD Family 19h Models 11h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55901_0.25.zip|publ=AMD|pid=55901|rev=0.25|date=2022-11-10}}</ref> which may be available on future {{amd|Ryzen Threadripper}} processors) and several low-speed interfaces listed below. | ||
+ | |||
+ | For link configuration details see {{amd|Socket SP5|l=package}}. | ||
+ | |||
+ | === Feature Summary === | ||
+ | * 16 to 96 {{amd|Zen 4|l=arch}} [[x86]] CPU cores with 2-way [[SMT]] | ||
+ | ** Op cache holding up to 6,750 Ops, 2 × 32 KiB L1, and 1 MiB L2 cache per core | ||
+ | ** x86 extensions ('''new'''): {{x86|ABM}}, {{x86|ADX}}, {{x86|AES}}, {{x86|AVX}}, {{x86|AVX2}}, '''{{x86|AVX512F}}''', '''{{x86|AVX512BW}}''', '''{{x86|AVX512CD}}''', '''{{x86|AVX512DQ}}''', '''{{x86|AVX512VL}}''', '''{{x86|AVX512_BF16}}''', '''{{x86|AVX512_BITALG}}''', '''{{x86|AVX512_IFMA}}''', '''{{x86|AVX512_VBMI}}''', '''{{x86|AVX512_VBMI2}}''', '''{{x86|AVX512_VNNI}}''', '''{{x86|AVX512_VPOPCNTDQ}}''', {{x86|BMI1}}, {{x86|BMI2}}, {{x86|CLFLUSH}}, {{x86|CLFLUSHOPT}}, {{x86|CLWB}}, {{x86|CLZERO}}, {{x86|CMOV}}, {{x86|CMPXCHG8B}}, {{x86|CMPXCHG16B}}, {{x86|EMMX}}, {{x86|F16C}}, {{x86|FMA3}}, {{x86|FPU}}, {{x86|FSGSBASE}}, {{x86|FXSR}}, '''{{x86|GFNI}}''', {{x86|INVLPGB}}, {{x86|INVPCID}}, {{x86|LahfSahf}}, {{x86|MCOMMIT}}, {{x86|MMX}}, {{x86|MONITOR}}, {{x86|MONITORX}}, {{x86|MOVBE}}, {{x86|MSR}}, {{x86|PCLMULQDQ}}, {{x86|PKU}}, {{x86|POPCNT}}, {{x86|PREFETCH}}, {{x86|RDPID}}, {{x86|RDPRU}}, {{x86|RDRAND}}, {{x86|RDTSCP}}, {{x86|RDSEED}}, {{x86|SHA}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4A}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|SysCallSysRet}}, {{x86|SysEnterSysExit}}, {{x86|TSC}}, {{x86|VAES}}, {{x86|VPCLMULQDQ}}, {{x86|WBNOINVD}}, {{x86|XSAVE}}, {{x86|XSAVEC}}, {{x86|XSAVEOPT}} | ||
+ | ** Security extensions: {{x86|CET|CET_SS}}, {{x86|GMET}}, {{x86|NX}}, {{x86|SME|SEV}}, {{x86|SME|SEV-ES}}, {{x86|SME|SEV-SNP}}, {{x86|SMAP}}, {{x86|SME|SME/TSME}}, {{x86|SMEP}}, {{x86|UMIP}} | ||
+ | ** Speculation control: {{x86|IBPB}}, {{x86|IBRS}}, {{x86|PSFD}}, {{x86|SSBD}}, {{x86|STIBP}} | ||
+ | * 32 MiB L3 cache per Core Complex (8 CPU cores), 64 to 384 MiB total | ||
+ | |||
+ | * 12 × 80-bit DDR5 SDRAM interface up to 2400 MHz, PC5-38400 (DDR5-4800), 460.8 GB/s | ||
+ | ** Two independent 40-bit (32 data, 8 ECC) DDR5 subchannels per channel | ||
+ | ** Up to 2 DIMMs per channel, 24 total | ||
+ | ** {{abbr|SR}}/{{abbr|DR}} {{abbr|RDIMM}}, {{abbr|4R}}/{{abbr|8R}} {{abbr|LRDIMM}}, 4R/8R/16R {{abbr|3DS DIMM}} | ||
+ | ** ECC supported (x4, x8, x16, chipkill)<!--AMD-55901-0.97 Sec 3.7--> | ||
+ | ** DRAM bus parity and write data {{abbr|CRC}} options<!--ibid--> | ||
+ | ** Up to 6 TiB total | ||
+ | |||
+ | * Eight 16-lane PCIe Gen 5 (32 GT/s) controllers | ||
+ | ** Configurable x16, x8, x4, x2, x1 | ||
+ | ** Up to 9 links per controller | ||
+ | ** {{abbr|xGMI}} protocol supported on 4 × 16 lanes, 2P systems only | ||
+ | ** {{abbr|CXL}} 1.1 protocol supported on 4 × 16 lanes | ||
+ | ** SATA Gen 3 protocol supported on 2 × 16 lanes | ||
+ | |||
+ | * Two 4-lane PCIe Gen 3 (8 GT/s) controllers | ||
+ | ** {{abbr|WAFL}} protocol supported on two lanes, 2P systems only | ||
+ | |||
+ | * Four USB 3.2 Gen 1×1 (5 Gb/s) ports | ||
+ | |||
+ | * Low speed interfaces (some are alternative functions on shared pins): | ||
+ | ** 3 × 2-wire or 1 × 4-wire + 1 × 2-wire {{abbr|UART}} | ||
+ | ** 2 × 1/2/4-bit {{abbr|SPI/eSPI}} | ||
+ | ** 4 × {{abbr|I<sup>3</sup>C}} | ||
+ | ** 6 × {{abbr|I<sup>2</sup>C}} | ||
+ | ** 2 × {{abbr|SMBus}} | ||
+ | ** 4 × {{abbr|SGPIO}} | ||
+ | ** 2 × SATA {{abbr|DevSlp}} | ||
+ | ** 76 × {{abbr|GPIO}} | ||
+ | ** Sideband Interface a.k.a. {{abbr|APML}}-I3C ({{abbr|SB-RMI}}, {{abbr|SB-TSI}}) for health monitoring by a {{abbr|BMC}} | ||
+ | ** 2 × Serial VID Interface (SVI3) for voltage control | ||
+ | ** {{abbr|JTAG}} | ||
+ | |||
+ | * {{amd|secure processor|AMD Secure Processor}}, [[Secure Boot]], Hardware root-of-trust | ||
+ | |||
+ | * {{abbr|TDP}} range 200 to 400 Watt, configurable | ||
+ | |||
+ | === Naming Scheme === | ||
+ | {{chip identification | ||
+ | | title = | ||
+ | | parts = 7 | ||
+ | | ex 1 = EPYC | ||
+ | | ex 2 = | ||
+ | | ex 3 = 9 | ||
+ | | ex 4 = 6 | ||
+ | | ex 5 = 5 | ||
+ | | ex 6 = 4 | ||
+ | | ex 7 = P | ||
+ | | desc 1 = <table style="text-align:left"><th colspan="2">Product Family</th> | ||
+ | <tr><td>EPYC</td></tr> | ||
+ | </table> | ||
+ | | desc 3 = <table style="text-align:left"><th colspan="2">Product Series</th> | ||
+ | <tr><th>9xxx</th><td>High-performance server CPU/{{abbr|SoC}}</td></tr> | ||
+ | </table> | ||
+ | | desc 4 = <table style="text-align:left"><th colspan="2">Product Model</th> | ||
+ | <tr><th>0</th><td>8 cores</td></tr> | ||
+ | <tr><th>1</th><td>16 cores</td></tr> | ||
+ | <tr><th>2</th><td>24 cores</td></tr> | ||
+ | <tr><th>3</th><td>32 cores</td></tr> | ||
+ | <tr><th>4</th><td>48 cores</td></tr> | ||
+ | <tr><th>5</th><td>64 cores</td></tr> | ||
+ | <tr><th>6</th><td>84-96 cores</td></tr> | ||
+ | </table> | ||
+ | | desc 5 = '''Performance Level''', higher number is better | ||
+ | | desc 6 = <table style="text-align:left"><th colspan="2">Generation</th> | ||
+ | <tr><th>4</th><td>Fourth generation, 9004 "Genoa" series, {{amd|Zen 4|l=arch}} microarchitecture</td></tr> | ||
+ | </table> | ||
+ | | desc 7 = <table style="text-align:left"><th colspan="2">Feature Modifier</th> | ||
+ | <tr><th>(none)</th><td>1P, 2P</td></tr> | ||
+ | <tr><th>P</th><td>1P (single socket) only</td></tr> | ||
+ | <tr><th>F</th><td>Frequency optimized</td></tr> | ||
+ | </table> | ||
+ | }} | ||
+ | |||
+ | Source: <ref name="AMD-58015-*">{{cite techdoc|title=AMD EPYC™ 9004 Series Architecture Overview|url=https://www.amd.com/system/files/documents/58015-epyc-9004-tg-architecture-overview.pdf|publ=AMD|pid=58015|rev=1.1|date=2022-12}}</ref> | ||
+ | |||
+ | == Genoa Processors == | ||
+ | <!-- NOTE: | ||
+ | This table is generated automatically from the data in the actual articles. | ||
+ | If a microprocessor is missing from the list, an appropriate article for it needs to be | ||
+ | created and tagged accordingly. | ||
+ | |||
+ | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips | ||
+ | --> | ||
+ | {{comp table start}} | ||
+ | <table class="comptable sortable"> | ||
+ | {{comp table header|main|15:List of Genoa Processors}} | ||
+ | {{comp table header|cols|{{abbr|C|Cores}}|{{abbr|T|Threads}}|L2|L3|Frequ.|Turbo|Turbo 1C|Memory|{{abbr|cTDP}}↓|{{abbr|TDP}}|cTDP↑|Launched|Price 1k|{{abbr|OPN}}}} | ||
+ | {{comp table header|lsep|15:[[Uniprocessors]]}} | ||
+ | {{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]] [[max cpu count::1]] | ||
+ | |?full page name | ||
+ | |?name | ||
+ | |?core count | ||
+ | |?thread count | ||
+ | |?l2$ size | ||
+ | |?l3$ size | ||
+ | |?base frequency#GHz | ||
+ | |?turbo frequency#GHz | ||
+ | |?turbo frequency (1 core)#GHz | ||
+ | |?supported memory type | ||
+ | |?tdp down |?tdp |?tdp up | ||
+ | |?first launched | ||
+ | |?release price | ||
+ | |?part number | ||
+ | |sort=model number | ||
+ | |format=template | ||
+ | |template=proc table 3 | ||
+ | |userparam=16 | ||
+ | |mainlabel=- | ||
+ | |valuesep=,<br/> | ||
+ | }} | ||
+ | |||
+ | {{comp table header|lsep|15:[[Multiprocessors]] (dual-socket)}} | ||
+ | {{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]] [[max cpu count::>>1]] | ||
+ | |?full page name | ||
+ | |?name | ||
+ | |?core count | ||
+ | |?thread count | ||
+ | |?l2$ size | ||
+ | |?l3$ size | ||
+ | |?base frequency#GHz | ||
+ | |?turbo frequency#GHz | ||
+ | |?turbo frequency (1 core)#GHz | ||
+ | |?supported memory type | ||
+ | |?tdp down |?tdp |?tdp up | ||
+ | |?first launched | ||
+ | |?release price | ||
+ | |?part number | ||
+ | |sort=model number | ||
+ | |format=template | ||
+ | |template=proc table 3 | ||
+ | |userparam=16 | ||
+ | |mainlabel=- | ||
+ | |valuesep=,<br/> | ||
+ | }} | ||
+ | |||
+ | {{comp table header|lsep|15:Frequency-optimized SKUs}} | ||
+ | {{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]] [[part of::Frequency-optimized SKUs]] | ||
+ | |?full page name | ||
+ | |?name | ||
+ | |?core count | ||
+ | |?thread count | ||
+ | |?l2$ size | ||
+ | |?l3$ size | ||
+ | |?base frequency#GHz | ||
+ | |?turbo frequency#GHz | ||
+ | |?turbo frequency (1 core)#GHz | ||
+ | |?supported memory type | ||
+ | |?tdp down |?tdp |?tdp up | ||
+ | |?first launched | ||
+ | |?release price | ||
+ | |?part number | ||
+ | |sort=model number | ||
+ | |format=template | ||
+ | |template=proc table 3 | ||
+ | |userparam=16 | ||
+ | |mainlabel=- | ||
+ | |valuesep=,<br/> | ||
+ | }} | ||
+ | |||
+ | {{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Genoa]]}} | ||
+ | </table> | ||
+ | {{comp table end}} | ||
+ | |||
+ | === SKU Comparison === | ||
+ | Below are a number of SKU comparison graphs based on their specifications. | ||
+ | |||
+ | <div style="float: left; margin: 10px"> | ||
+ | {{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]] | ||
+ | |?core count | ||
+ | |?base frequency | ||
+ | |charttitle=Cores vs. Base Frequency | ||
+ | |numbersaxislabel=Frequency (MHz) | ||
+ | |labelaxislabel=Core Count | ||
+ | |height=400 | ||
+ | |width=400 | ||
+ | |theme=vector | ||
+ | |group=property | ||
+ | |grouplabel=subject | ||
+ | |charttype=scatter | ||
+ | |format=jqplotseries | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | </div> | ||
+ | |||
+ | <div style="float: left; margin: 10px"> | ||
+ | {{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]] | ||
+ | |?core count | ||
+ | |?turbo frequency | ||
+ | |charttitle=Cores vs. Turbo Frequency | ||
+ | |numbersaxislabel=Frequency (MHz) | ||
+ | |labelaxislabel=Core Count | ||
+ | |height=400 | ||
+ | |width=400 | ||
+ | |theme=vector | ||
+ | |group=property | ||
+ | |grouplabel=subject | ||
+ | |charttype=scatter | ||
+ | |format=jqplotseries | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | </div> | ||
+ | |||
+ | <div style="float: left; margin: 10px"> | ||
+ | {{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]] | ||
+ | |?core count | ||
+ | |?tdp | ||
+ | |charttitle=Cores vs. TDP | ||
+ | |numbersaxislabel=TDP (W) | ||
+ | |labelaxislabel=Core Count | ||
+ | |height=400 | ||
+ | |width=400 | ||
+ | |theme=vector | ||
+ | |group=property | ||
+ | |grouplabel=subject | ||
+ | |charttype=scatter | ||
+ | |format=jqplotseries | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | </div> | ||
+ | |||
+ | <div style="float: left; margin: 10px"> | ||
+ | {{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]] | ||
+ | |?turbo frequency | ||
+ | |?tdp | ||
+ | |charttitle=Frequency vs. TDP | ||
+ | |numbersaxislabel=TDP (W) | ||
+ | |labelaxislabel=Frequency (MHz) | ||
+ | |height=400 | ||
+ | |width=400 | ||
+ | |theme=vector | ||
+ | |group=property | ||
+ | |grouplabel=subject | ||
+ | |charttype=scatter | ||
+ | |format=jqplotseries | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | </div> | ||
+ | |||
+ | {{clear}} | ||
+ | |||
+ | == References == | ||
+ | <references/> | ||
+ | |||
+ | == See also == | ||
+ | {{amd zen 4 core see also}} |
Latest revision as of 01:41, 2 April 2023
Edit Values | |
Genoa | |
General Info | |
Designer | AMD |
Manufacturer | TSMC |
Introduction | November 10, 2022 (launched) |
Microarchitecture | |
ISA | x86-64 |
Microarchitecture | Zen 4 |
Word Size | 8 octets 64 bit16 nibbles |
Process | 5 nm 0.005 μm , 6 nm5.0e-6 mm 0.006 μm 6.0e-6 mm |
Technology | CMOS |
Packaging | |
Package | SP5 (FC-OLGA) |
Dimension | 75.4 mm 7.54 cm × 72 mm2.969 in 7.2 cm 2.835 in |
Pitch | 0.81 mm 0.0319 in × 0.94 mm0.037 in |
Contacts | 6096 |
Socket | Socket SP5 |
Succession | |
Genoa is the codename of AMD's EPYC 9004 series of high-performance microprocessors based on the Zen 4 microarchitecture for single- and dual-socket server platforms. Launched in November 2022 it succeeded the third generation of EPYC processors, the EPYC 7003 "Milan" series.[1]
EPYC 9004 processors identify as members of AMD CPU Family 19h, Model 11h (engineering samples as Model 10h).
Contents
Overview[edit]
![]() |
This section is empty; you can help add the missing info by editing this page. |
Memory Interface[edit]
The "Genoa" I/O die integrates 12 DDR5 memory controllers and interfaces, three per I/O die quadrant, which support raw data rates up to 4800 MT/s. Up to 2 DIMMs per channel are supported. Each channel has two independent 40-bit (32 data, 8 ECC) DDR5 subchannels. The memory controllers support ECC memory (80b x4, 80b x8, and 72b x4 ECC, i.e. EC4 and EC8 DIMMs) and DDR5 DRAMs with 16/24/32 Gb density on the following DIMM types:
- SR/DR RDIMM built with x4 and x8 DDR5 devices (1Rx4 16/32/48 GiB, 1Rx8 16/24 GiB, 2Rx4 64/80/96 GiB, 2Rx8 32/40/48 GiB)
- 4R/8R LRDIMM (2S2R, 2S4R)
- 4R/8R/16R 3DS DIMM built with x4 devices (2S2Rx4 128/192 GiB, 2S4Rx4 256/384 GiB, 2S8Rx4 512 GiB)
UDIMM, NVDIMM-N, NVDIMM-P types are not supported.
The maximum total memory capacity is 6 TiB per socket using 3DS DIMMs of e.g. 12 × 512 GiB capacity.
Input/Output Interfaces[edit]
The "Genoa" I/O die integrates eight 16-lane PCIe Gen 5 (32 GT/s) controllers and interfaces. Link bifurcation permits configuration of the PCIe lanes as x16, x8, x4, x2, or x1 wide independent links, e.g. 1x8 + 1x4 + 4x1. Each controller supports up to nine PCIe links, or up to eight if any lane is is configured as SATA link, and per link lane reversal which can simplify signal routing on the motherboard.
Two supplementary I/O interfaces support the PCIe Gen 3 (8 GT/s) protocol. Each of these interfaces has four lanes configurable x4, x2, x1 and supports up to four links.
On dual-socket systems four, or optionally three depending on bandwidth requirements, x16 links are repurposed for cache coherent inter-socket traffic. The raw data rate of these xGMI links is also 32 GT/s. A WAFL link occupying two lanes on one of the supplementary interfaces connects the Control Fabrics of each processor, i.e. the PSP, SMUs and other IPs, primarily for temperature monitoring, power and frequency control.
In summary on 1P systems up to 128 PCIe Gen 5 and 8 PCIe Gen 3 lanes are available for I/O. On 2P systems up to 64 or 80 PCIe Gen 5 and 6 PCIe Gen 3 lanes per socket.
Up to four of the x16 interfaces can be configured as cache-coherent Compute Express Link. "Genoa" supports version 1.1 of the protocol, specifically accelerators without local memory such as a NIC using the CXL.io and CXL.cache protocols, and memory expanders using the CXL.io and CXL.memory protocols. One accelerator per interface can be attached with a 1x16 or 1x8 link, or up to four memory expanders with 1x16, 2x8, or 4x4 links. Unused lanes are available for PCIe and configurable 1x8, 2x4, or 3x4.
The lanes on two x16 interfaces can be configured as SATA Gen 3 links, unused lanes are available for PCIe. On 1P systems up to 32 SATA ports total are available, on 2P systems 16 ports per socket as one of the interfaces is reserved for xGMI duty.
The processors integrate a controller hub with four USB 3.2 Gen 1×1 (5 Gb/s) ports (the I/O die actually implements USB 3.2 Gen 2×1[2] which may be available on future Ryzen Threadripper processors) and several low-speed interfaces listed below.
For link configuration details see Socket SP5.
Feature Summary[edit]
- 16 to 96 Zen 4 x86 CPU cores with 2-way SMT
- Op cache holding up to 6,750 Ops, 2 × 32 KiB L1, and 1 MiB L2 cache per core
- x86 extensions (new): ABM, ADX, AES, AVX, AVX2, AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL, AVX512_BF16, AVX512_BITALG, AVX512_IFMA, AVX512_VBMI, AVX512_VBMI2, AVX512_VNNI, AVX512_VPOPCNTDQ, BMI1, BMI2, CLFLUSH, CLFLUSHOPT, CLWB, CLZERO, CMOV, CMPXCHG8B, CMPXCHG16B, EMMX, F16C, FMA3, FPU, FSGSBASE, FXSR, GFNI, INVLPGB, INVPCID, LahfSahf, MCOMMIT, MMX, MONITOR, MONITORX, MOVBE, MSR, PCLMULQDQ, PKU, POPCNT, PREFETCH, RDPID, RDPRU, RDRAND, RDTSCP, RDSEED, SHA, SSE, SSE2, SSE3, SSSE3, SSE4A, SSE4.1, SSE4.2, SysCallSysRet, SysEnterSysExit, TSC, VAES, VPCLMULQDQ, WBNOINVD, XSAVE, XSAVEC, XSAVEOPT
- Security extensions: CET_SS, GMET, NX, SEV, SEV-ES, SEV-SNP, SMAP, SME/TSME, SMEP, UMIP
- Speculation control: IBPB, IBRS, PSFD, SSBD, STIBP
- 32 MiB L3 cache per Core Complex (8 CPU cores), 64 to 384 MiB total
- 12 × 80-bit DDR5 SDRAM interface up to 2400 MHz, PC5-38400 (DDR5-4800), 460.8 GB/s
- Eight 16-lane PCIe Gen 5 (32 GT/s) controllers
- Two 4-lane PCIe Gen 3 (8 GT/s) controllers
- WAFL protocol supported on two lanes, 2P systems only
- Four USB 3.2 Gen 1×1 (5 Gb/s) ports
- Low speed interfaces (some are alternative functions on shared pins):
- AMD Secure Processor, Secure Boot, Hardware root-of-trust
- TDP range 200 to 400 Watt, configurable
Naming Scheme[edit]
EPYC | 9 | 6 | 5 | 4 | P | ||||||||||||||||||
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Performance Level, higher number is better | |||||||||||||||||||||||
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Source: [3]
Genoa Processors[edit]
List of Genoa Processors | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Model | C | T | L2 | L3 | Frequ. | Turbo | Turbo 1C | Memory | cTDP↓ | TDP | cTDP↑ | Launched | Price 1k | OPN | |
Uniprocessors | |||||||||||||||
EPYC 9354P | 32 | 64 | 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 3.25 GHz 3,250 MHz 3,250,000 kHz | 3.75 GHz 3,750 MHz 3,750,000 kHz | 3.8 GHz 3,800 MHz 3,800,000 kHz | DDR5-4800 | 240 W 240,000 mW 0.322 hp 0.24 kW | 280 W 280,000 mW 0.375 hp 0.28 kW | 300 W 300,000 mW 0.402 hp 0.3 kW | 10 November 2022 | $ 2,730.00 € 2,457.00 £ 2,211.30 ¥ 282,090.90 | 100-100000805, 100-100000805WOF | |
EPYC 9454P | 48 | 96 | 48 MiB 49,152 KiB 50,331,648 B 0.0469 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 2.75 GHz 2,750 MHz 2,750,000 kHz | 3.65 GHz 3,650 MHz 3,650,000 kHz | 3.8 GHz 3,800 MHz 3,800,000 kHz | DDR5-4800 | 240 W 240,000 mW 0.322 hp 0.24 kW | 290 W 290,000 mW 0.389 hp 0.29 kW | 300 W 300,000 mW 0.402 hp 0.3 kW | 10 November 2022 | $ 4,598.00 € 4,138.20 £ 3,724.38 ¥ 475,111.34 | 100-100000873, 100-100000873WOF | |
EPYC 9554P | 64 | 128 | 64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 3.1 GHz 3,100 MHz 3,100,000 kHz | 3.75 GHz 3,750 MHz 3,750,000 kHz | 3.75 GHz 3,750 MHz 3,750,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 360 W 360,000 mW 0.483 hp 0.36 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 7,104.00 € 6,393.60 £ 5,754.24 ¥ 734,056.32 | 100-100000804, 100-100000804WOF | |
EPYC 9654P | 96 | 192 | 96 MiB 98,304 KiB 100,663,296 B 0.0938 GiB | 384 MiB 393,216 KiB 402,653,184 B 0.375 GiB | 2.4 GHz 2,400 MHz 2,400,000 kHz | 3.55 GHz 3,550 MHz 3,550,000 kHz | 3.7 GHz 3,700 MHz 3,700,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 360 W 360,000 mW 0.483 hp 0.36 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 10,625.00 € 9,562.50 £ 8,606.25 ¥ 1,097,881.25 | 100-100000803, 100-100000803WOF | |
Multiprocessors (dual-socket) | |||||||||||||||
EPYC 9124 | 16 | 32 | 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB | 64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB | 3 GHz 3,000 MHz 3,000,000 kHz | 3.6 GHz 3,600 MHz 3,600,000 kHz | 3.7 GHz 3,700 MHz 3,700,000 kHz | DDR5-4800 | 200 W 200,000 mW 0.268 hp 0.2 kW | 240 W 240,000 mW 0.322 hp 0.24 kW | 10 November 2022 | $ 1,083.00 € 974.70 £ 877.23 ¥ 111,906.39 | 100-100000802, 100-100000802WOF | ||
EPYC 9174F | 16 | 32 | 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 4.1 GHz 4,100 MHz 4,100,000 kHz | 4.15 GHz 4,150 MHz 4,150,000 kHz | 4.4 GHz 4,400 MHz 4,400,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 3,850.00 € 3,465.00 £ 3,118.50 ¥ 397,820.50 | 100-100000796, 100-100000796WOF | ||
EPYC 9224 | 24 | 48 | 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB | 64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB | 2.5 GHz 2,500 MHz 2,500,000 kHz | 3.65 GHz 3,650 MHz 3,650,000 kHz | 3.7 GHz 3,700 MHz 3,700,000 kHz | DDR5-4800 | 200 W 200,000 mW 0.268 hp 0.2 kW | 240 W 240,000 mW 0.322 hp 0.24 kW | 10 November 2022 | $ 1,825.00 € 1,642.50 £ 1,478.25 ¥ 188,577.25 | 100-100000939, 100-100000939WOF | ||
EPYC 9254 | 24 | 48 | 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB | 128 MiB 131,072 KiB 134,217,728 B 0.125 GiB | 2.9 GHz 2,900 MHz 2,900,000 kHz | 3.9 GHz 3,900 MHz 3,900,000 kHz | 4.15 GHz 4,150 MHz 4,150,000 kHz | DDR5-4800 | 200 W 200,000 mW 0.268 hp 0.2 kW | 240 W 240,000 mW 0.322 hp 0.24 kW | 10 November 2022 | $ 2,299.00 € 2,069.10 £ 1,862.19 ¥ 237,555.67 | 100-100000480, 100-100000480WOF | ||
EPYC 9274F | 24 | 48 | 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 4.05 GHz 4,050 MHz 4,050,000 kHz | 4.1 GHz 4,100 MHz 4,100,000 kHz | 4.3 GHz 4,300 MHz 4,300,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 3,060.00 € 2,754.00 £ 2,478.60 ¥ 316,189.80 | 100-100000794, 100-100000794WOF | ||
EPYC 9334 | 32 | 64 | 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB | 128 MiB 131,072 KiB 134,217,728 B 0.125 GiB | 2.7 GHz 2,700 MHz 2,700,000 kHz | 3.85 GHz 3,850 MHz 3,850,000 kHz | 3.9 GHz 3,900 MHz 3,900,000 kHz | DDR5-4800 | 200 W 200,000 mW 0.268 hp 0.2 kW | 210 W 210,000 mW 0.282 hp 0.21 kW | 240 W 240,000 mW 0.322 hp 0.24 kW | 10 November 2022 | $ 2,990.00 € 2,691.00 £ 2,421.90 ¥ 308,956.70 | 100-100000800, 100-100000800WOF | |
EPYC 9354 | 32 | 64 | 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 3.25 GHz 3,250 MHz 3,250,000 kHz | 3.75 GHz 3,750 MHz 3,750,000 kHz | 3.8 GHz 3,800 MHz 3,800,000 kHz | DDR5-4800 | 240 W 240,000 mW 0.322 hp 0.24 kW | 280 W 280,000 mW 0.375 hp 0.28 kW | 300 W 300,000 mW 0.402 hp 0.3 kW | 10 November 2022 | $ 3,420.00 € 3,078.00 £ 2,770.20 ¥ 353,388.60 | 100-100000798, 100-100000798WOF | |
EPYC 9374F | 32 | 64 | 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 3.85 GHz 3,850 MHz 3,850,000 kHz | 4.1 GHz 4,100 MHz 4,100,000 kHz | 4.3 GHz 4,300 MHz 4,300,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 4,850.00 € 4,365.00 £ 3,928.50 ¥ 501,150.50 | 100-100000792, 100-100000792WOF | ||
EPYC 9454 | 48 | 96 | 48 MiB 49,152 KiB 50,331,648 B 0.0469 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 2.75 GHz 2,750 MHz 2,750,000 kHz | 3.65 GHz 3,650 MHz 3,650,000 kHz | 3.8 GHz 3,800 MHz 3,800,000 kHz | DDR5-4800 | 240 W 240,000 mW 0.322 hp 0.24 kW | 290 W 290,000 mW 0.389 hp 0.29 kW | 300 W 300,000 mW 0.402 hp 0.3 kW | 10 November 2022 | $ 5,225.00 € 4,702.50 £ 4,232.25 ¥ 539,899.25 | 100-100000478, 100-100000478WOF | |
EPYC 9474F | 48 | 96 | 48 MiB 49,152 KiB 50,331,648 B 0.0469 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 3.6 GHz 3,600 MHz 3,600,000 kHz | 3.95 GHz 3,950 MHz 3,950,000 kHz | 4.1 GHz 4,100 MHz 4,100,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 360 W 360,000 mW 0.483 hp 0.36 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 6,780.00 € 6,102.00 £ 5,491.80 ¥ 700,577.40 | 100-100000788, 100-100000788WOF | |
EPYC 9534 | 64 | 128 | 64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 2.45 GHz 2,450 MHz 2,450,000 kHz | 3.55 GHz 3,550 MHz 3,550,000 kHz | 3.7 GHz 3,700 MHz 3,700,000 kHz | DDR5-4800 | 240 W 240,000 mW 0.322 hp 0.24 kW | 280 W 280,000 mW 0.375 hp 0.28 kW | 300 W 300,000 mW 0.402 hp 0.3 kW | 10 November 2022 | $ 8,803.00 € 7,922.70 £ 7,130.43 ¥ 909,613.99 | 100-100000799, 100-100000799WOF | |
EPYC 9554 | 64 | 128 | 64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 3.1 GHz 3,100 MHz 3,100,000 kHz | 3.75 GHz 3,750 MHz 3,750,000 kHz | 3.75 GHz 3,750 MHz 3,750,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 360 W 360,000 mW 0.483 hp 0.36 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 9,087.00 € 8,178.30 £ 7,360.47 ¥ 938,959.71 | 100-100000790, 100-100000790WOF | |
EPYC 9634 | 84 | 168 | 84 MiB 86,016 KiB 88,080,384 B 0.082 GiB | 384 MiB 393,216 KiB 402,653,184 B 0.375 GiB | 2.25 GHz 2,250 MHz 2,250,000 kHz | 3.1 GHz 3,100 MHz 3,100,000 kHz | 3.7 GHz 3,700 MHz 3,700,000 kHz | DDR5-4800 | 240 W 240,000 mW 0.322 hp 0.24 kW | 290 W 290,000 mW 0.389 hp 0.29 kW | 300 W 300,000 mW 0.402 hp 0.3 kW | 10 November 2022 | $ 10,304.00 € 9,273.60 £ 8,346.24 ¥ 1,064,712.32 | 100-100000797, 100-100000797WOF | |
EPYC 9654 | 96 | 192 | 96 MiB 98,304 KiB 100,663,296 B 0.0938 GiB | 384 MiB 393,216 KiB 402,653,184 B 0.375 GiB | 2.4 GHz 2,400 MHz 2,400,000 kHz | 3.55 GHz 3,550 MHz 3,550,000 kHz | 3.7 GHz 3,700 MHz 3,700,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 360 W 360,000 mW 0.483 hp 0.36 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 11,805.00 € 10,624.50 £ 9,562.05 ¥ 1,219,810.65 | 100-100000789, 100-100000789WOF | |
Frequency-optimized SKUs | |||||||||||||||
EPYC 9174F | 16 | 32 | 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 4.1 GHz 4,100 MHz 4,100,000 kHz | 4.15 GHz 4,150 MHz 4,150,000 kHz | 4.4 GHz 4,400 MHz 4,400,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 3,850.00 € 3,465.00 £ 3,118.50 ¥ 397,820.50 | 100-100000796, 100-100000796WOF | ||
EPYC 9274F | 24 | 48 | 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 4.05 GHz 4,050 MHz 4,050,000 kHz | 4.1 GHz 4,100 MHz 4,100,000 kHz | 4.3 GHz 4,300 MHz 4,300,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 3,060.00 € 2,754.00 £ 2,478.60 ¥ 316,189.80 | 100-100000794, 100-100000794WOF | ||
EPYC 9374F | 32 | 64 | 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 3.85 GHz 3,850 MHz 3,850,000 kHz | 4.1 GHz 4,100 MHz 4,100,000 kHz | 4.3 GHz 4,300 MHz 4,300,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 4,850.00 € 4,365.00 £ 3,928.50 ¥ 501,150.50 | 100-100000792, 100-100000792WOF | ||
EPYC 9474F | 48 | 96 | 48 MiB 49,152 KiB 50,331,648 B 0.0469 GiB | 256 MiB 262,144 KiB 268,435,456 B 0.25 GiB | 3.6 GHz 3,600 MHz 3,600,000 kHz | 3.95 GHz 3,950 MHz 3,950,000 kHz | 4.1 GHz 4,100 MHz 4,100,000 kHz | DDR5-4800 | 320 W 320,000 mW 0.429 hp 0.32 kW | 360 W 360,000 mW 0.483 hp 0.36 kW | 400 W 400,000 mW 0.536 hp 0.4 kW | 10 November 2022 | $ 6,780.00 € 6,102.00 £ 5,491.80 ¥ 700,577.40 | 100-100000788, 100-100000788WOF | |
Count: 18 |
SKU Comparison[edit]
Below are a number of SKU comparison graphs based on their specifications.
References[edit]
- ↑ "Offering Unmatched Performance, Leadership Energy Efficiency and Next-Generation Architecture, AMD Brings 4th Gen AMD EPYC™ Processors to The Modern Data Center" (Press release). AMD.com. November 10, 2022. Retrieved February 2022.
- ↑ "Processor Programming Reference (PPR) for AMD Family 19h Models 11h, Revision B1 Processors", AMD Publ. #55901, Rev. 0.25, November 10, 2022
- ↑ "AMD EPYC™ 9004 Series Architecture Overview", AMD Publ. #58015, Rev. 1.1, December 2022
See also[edit]
designer | AMD + |
first launched | November 10, 2022 + |
instance of | core + |
isa | x86-64 + |
manufacturer | TSMC + |
microarchitecture | Zen 4 + |
name | Genoa + |
package | SP5 + |
process | 5 nm (0.005 μm, 5.0e-6 mm) + and 6 nm (0.006 μm, 6.0e-6 mm) + |
socket | Socket SP5 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |