Semiconductor & Computer Engineering
| Edit Values | |
| Neoverse N2 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | September 22, 2020 |
| Process | 7 nm |
| Core Configs | 4, 8, 16, 32, 64, 96, 128 |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 13 |
| Decode | 5-way |
| Instructions | |
| ISA | ARMv9.0-A |
| Features | Perseus |
| Extensions | SVE2 |
| Cores | |
| Core Names | Neoverse (Genesis) |
| Succession | |
Neoverse N2 (codename "Perseus") is the successor to Neoverse N1 (Ares), a high-performance ARM microarchitecture designed by ARM Holdings for the server market.
This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Contents
History[edit]
Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
Release Dates[edit]
Neoverse N2 is expected to show up in products around 2020. It was officially announced by Arm on September 22, 2020.
On August 28, 2023, Arm announced the Neoverse CSS N2 (Genesis), a customizable CPU subsystem implementation by Arm to reduce the time to market for customers.
Process Technology[edit]
Neoverse N2 specifically designed takes advantage of the power and area advantages of the 7nm+ process.
- See also: Neoverse
All Neoverse N2 Processors[edit]
| List of Neoverse N2-based Processors | |||||||||
|---|---|---|---|---|---|---|---|---|---|
| Main processor | Integrated Graphics | ||||||||
| Model | Part number | Family | Arch | Cores | Frequency | Process | Launched | GPU | Frequency |
| Count: 0 | |||||||||
Architecture[edit]
The Neoverse N2 (codename "Perseus") is derived from the Cortex-A710 and implements the ARMv9.0-A instruction set.
Key changes from Neoverse N1[edit]
- ARMv9.0-A instruction set (from ARMv8.2-A)
- 7nm+ process (from 7nm)
- CMN-700 mesh interconnect (from CMN-600)
- BTB capacity: 8K entries
- Micro-op cache: 1536 entries
- Rename / Dispatch width: 5
- ROB: 160+ entry
- Pipeline depth: 10 cycles
- Execution ports: 13
- SVE2 support
This list is incomplete; you can help by expanding it.
Models[edit]
- Microsoft Azure Cobalt 100 • 128-core Neoverse N2 CPU
- Alibaba Yitian 710 • Neoverse N2 CPU
Bibliography[edit]
- Drew Henry keynote, TechCon 2018 keynote.
| codename | Neoverse N2 + |
| core count | 4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 + |
| designer | ARM Holdings + |
| first launched | September 22, 2020 + |
| full page name | arm holdings/microarchitectures/neoverse n2 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv9.0-A + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Neoverse N2 + |
| pipeline stages | 13 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |