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  • intel/microarchitectures/bonnell
    ** DTLB ...GUs). For data, there is 24 [[KiB]] [[write-back]] L1 cache with a 2-level DTLB hierarchy, hardware page walker, and an integer store-to-load forwarding su
    38 KB (5,468 words) - 20:29, 23 May 2019
  • intel/microarchitectures/airmont
    * DTLB table size doubled (128 entries -> 256 entries)
    5 KB (568 words) - 19:40, 30 November 2017
  • intel/microarchitectures/broadwell (client)
    ** DTLB
    14 KB (1,891 words) - 14:37, 6 January 2022
  • intel/microarchitectures/haswell (client)
    ** DTLB
    27 KB (3,750 words) - 06:57, 18 November 2023
  • intel/microarchitectures/sandy bridge (client)
    *** Proper support for 1 GiB pages with 4-entry 1 GiB page DTLB (from 0) ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
    84 KB (13,075 words) - 00:54, 29 December 2020
  • intel/microarchitectures/skylake (client)
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
    79 KB (11,922 words) - 06:46, 11 November 2022
  • intel/microarchitectures/kaby lake
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
    38 KB (5,431 words) - 10:41, 8 April 2024
  • intel/microarchitectures/coffee lake
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
    30 KB (4,192 words) - 13:48, 10 December 2023
  • amd/microarchitectures/k7
    ** DTLB
    6 KB (923 words) - 16:48, 3 March 2022
  • amd/microarchitectures/zen
    ** DTLB ...ode, and cache (including the µOP cache). The load queue, [[ITLB]], and [[DTLB]] (shaded in dark cyan) are also competitively shared but require SMT taggi
    79 KB (12,095 words) - 15:27, 9 June 2023
  • amd/microarchitectures/zen 2
    *** 1.33 larger L2 DTLB (2048-entry, up from 1536) * DTLB
    57 KB (8,701 words) - 22:11, 9 October 2022
  • qualcomm/microarchitectures/falkor
    ** DTLB
    6 KB (822 words) - 13:01, 19 May 2021
  • amd/microarchitectures/zen 3
    * DTLB
    15 KB (1,978 words) - 22:13, 6 April 2023
  • dec/microarchitectures/strongarm
    ** DTLB
    5 KB (738 words) - 13:49, 15 July 2018
  • dec/microarchitectures/alpha 21064
    ** DTLB
    4 KB (527 words) - 02:09, 4 August 2017
  • intel/microarchitectures/skylake (server)
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
    52 KB (7,651 words) - 00:59, 6 July 2022
  • amd/microarchitectures/zen+
    ** DTLB
    11 KB (1,613 words) - 08:39, 3 March 2024
  • intel/microarchitectures/cascade lake
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
    32 KB (4,535 words) - 05:44, 9 October 2022
  • samsung/microarchitectures/m1
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
    13 KB (1,962 words) - 14:48, 21 February 2019
  • samsung/microarchitectures/m2
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
    3 KB (456 words) - 14:50, 21 February 2019
  • samsung/microarchitectures/m3
    *** New mid-level DTLB ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB).
    20 KB (3,149 words) - 10:44, 15 February 2020
  • cavium/microarchitectures/vulcan
    *** DTLB
    17 KB (2,449 words) - 22:11, 4 October 2019
  • samsung/microarchitectures/m4
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
    5 KB (680 words) - 14:43, 16 March 2023
  • intel/microarchitectures/comet lake
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
    10 KB (1,357 words) - 18:48, 13 September 2022
  • amd/microarchitectures/zen 4
    * L1 and L2 DTLB size increased from 64 to 72 and 2,048 to 3,072 entries * DTLB
    13 KB (1,821 words) - 19:28, 13 November 2023
  • arm holdings/microarchitectures/neoverse n1
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
    7 KB (980 words) - 13:46, 18 February 2023
  • arm holdings/microarchitectures/cortex-a76
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
    14 KB (2,183 words) - 17:15, 17 October 2020
  • arm holdings/microarchitectures/cortex-a77
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
    17 KB (2,555 words) - 06:08, 16 June 2023
  • arm holdings/microarchitectures/cortex-a78
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
    21 KB (3,067 words) - 09:25, 31 March 2022
  • intel/microarchitectures/sunny cove
    *** DTLB now split for load and stores **** DTLB 4 KiB TLB competitively shared (from fixed partitioning)
    34 KB (5,187 words) - 06:27, 17 February 2023
  • arm holdings/microarchitectures/cortex-a8
    ** DTLB
    3 KB (428 words) - 14:30, 31 December 2018
  • samsung/microarchitectures/m5
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
    3 KB (333 words) - 22:10, 27 July 2021
  • intel/microarchitectures/palm cove
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
    5 KB (718 words) - 13:56, 9 May 2019
  • ibm/microarchitectures/z15
    ** DTLB
    7 KB (912 words) - 16:31, 7 May 2020
  • arm holdings/microarchitectures/neoverse v1
    ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
    5 KB (748 words) - 16:20, 4 July 2022
  • arm holdings/microarchitectures/cortex-a510
    The Cortex-A510 features an instruction TLB (ITLB) and data TLB (DTLB) which are private to each core and an L2 TLB that is private to the core c ** DTLB
    15 KB (2,282 words) - 11:20, 10 January 2023
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