• intel/core i7
  {{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|4:Features}} {{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|3:GPU|4:Features}}
  43 KB (5,739 words) - 21:30, 22 April 2024
• microprocessor
  ...may also serve as [[graphical processing unit]]s (GPUs), [[digital signal processor|signal processing units]] (DSPs), [[neural processing unit]] (NPUs), [[micr * '''[[digital signal processor]]''' ('''DSP''') - a microprocessor that specializes in the numerical manip
  8 KB (1,149 words) - 00:41, 16 September 2019
• intel/microarchitectures/goldmont
  ** Some vector instructions are faster, but like on {{\\|Airmont}}, none have throughput > * {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory
  7 KB (956 words) - 23:05, 23 March 2020
• intel/microarchitectures/haswell (client)
  ...or NOPs, CLC, some vector MOVs and some zeroing instructions (SUB, XOR and vector analogs). * {{x86|AVX2|<code>AVX2</code>}} - Advanced Vector Extensions 2; an extension that extends most integer instructions to 256 bi
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  * {{x86|AVX|<code>AVX</code>}} - Advanced Vector Extensions ...improved performance while saving power. Intel introduced a number of new vector computation ([[SIMD]]) and security instructions which improved [[floating
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  *** Incorporates an [[image signal processor]] (ISP) ...emory QoS for higher resolution displays and the integrated [[image signal processor]] (ISP)
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  ...y Lake G processors. And the introduction of the first low power quad core processor. ! colspan="5" | [[Integrated Graphics Processor]] !! colspan="9" | Standards
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/ice lake (client)
  * {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID ** {{x86|AVX512VL|<code>AVX512VL</code>}} - AVX-512 Vector Length
  23 KB (3,613 words) - 12:31, 20 June 2021
• x86/umip
  ...rupt handler code. CR0 contains flags which control operating modes of the processor. User-mode code was never able to load values into these registers. Reading
  2 KB (338 words) - 01:25, 30 December 2019
• intel/core i3
  {{comp table header|main|7:Main processor|3:GPU}} {{comp table header|main|7:Main processor|3:GPU|Features}}
  25 KB (3,397 words) - 03:12, 3 October 2022
• intel/core i5
  {{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|3:GPU|4:Features}} {{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|3:GPU|4:Features}}
  34 KB (4,663 words) - 20:38, 20 February 2023
• intrinsity/fastmath
  | arch = 32-bit vector/matrix math processor + RISC cpu '''FastMATH''' was a family of matrix and vector math processors with an on-die [[RISC]] [[CPU]]s introduced by [[Intrinsity
  4 KB (464 words) - 17:41, 3 July 2016
• intrinsity/fastmath/fastmath-1.5
  ...orporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. == Matrix and Vector Unit ==
  3 KB (317 words) - 16:30, 13 December 2017
• intrinsity/fastmath/fastmath-2
  ...orporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. == Matrix and Vector Unit ==
  3 KB (318 words) - 16:30, 13 December 2017
• intrinsity/fastmath/fastmath-lp
  ...r math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed. == Matrix and Vector Unit ==
  3 KB (334 words) - 16:31, 13 December 2017
• intrinsity/fastmath/fastmath-3
  ...orporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. == Matrix and Vector Unit ==
  3 KB (306 words) - 16:31, 13 December 2017
• intel/microarchitectures/coffee lake
  ...cture by introducing two additional [[physical cores]] into its mainstream processor die. Those two cores also come with up to 2 MiB of LLC slice per core (for ...[[2011]]. In [[2006]] Intel introduced the first mainstream [[quad-core]] processor, the [[Core 2 Extreme QX6700]] which was based on the {{intel|Kentsfield|l=
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/microarchitectures/zen
  ! colspan="11" | AMD Zen-based processor brands ...c logo.png|75px|link=amd/epyc]] || {{amd|EPYC}} || High-performance Server Processor || [[8 cores|8]]-[[32 cores|32]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|y
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ! colspan="11" | AMD Zen-based processor brands ...c logo.png|75px|link=amd/epyc]] || {{amd|EPYC}} || High-performance Server Processor || [[8 cores|8]]-[[64 cores|64]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|y
  57 KB (8,701 words) - 22:11, 9 October 2022
• mediatek/helio/mt6795
  * OpenVG 1.1 vector graphics accelerator * Integrated image signal processor supports 20 MP
  5 KB (669 words) - 14:35, 5 August 2020
• mediatek/helio/mt6795m
  * OpenVG 1.1 vector graphics accelerator * Integrated image signal processor supports 20 MP
  6 KB (647 words) - 09:57, 12 January 2018
• mediatek/helio/mt6795t
  * OpenVG 1.1 vector graphics accelerator * Integrated image signal processor supports 20 MP
  6 KB (670 words) - 09:36, 22 August 2018
• intel/cores/kaby lake y
  <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="5">Major Feature Diff</th></tr> |?has advanced vector extensions 2
  4 KB (594 words) - 06:30, 6 April 2019
• intel/cores/kaby lake s
  <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr> |?has advanced vector extensions 2
  5 KB (687 words) - 03:02, 11 October 2017
• intel/cores/kaby lake u
  <tr class="comptable-header"><th>&nbsp;</th><th colspan="11">Main processor</th><th colspan="3">IGP</th><th colspan="6">Major Feature Diff</th></tr> |?has advanced vector extensions 2
  6 KB (820 words) - 14:10, 29 February 2020
• intel/cores/kaby lake h
  <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="6">Major Feature Diff</th></tr> |?has advanced vector extensions 2
  5 KB (699 words) - 13:43, 8 April 2018
• intel/hd graphics 610
  '''HD Graphics 610''' is a family of {{intel|Gen 9.5}} [[integrated graphics processor]] designed by [[Intel]] for their {{intel|Kaby Lake|l=arch}}-based micropro <tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="3">IGP</th><th colspan="5">Major Feature Diff</th></tr>
  5 KB (618 words) - 09:27, 27 May 2018
• intel/hd graphics 615
  '''HD Graphics 615''' is a family of {{intel|Gen 9.5}} [[integrated graphics processor]] designed by [[Intel]] for their {{intel|Kaby Lake|l=arch}}-based micropro <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="5">Major Feature Diff</th></tr>
  5 KB (581 words) - 23:45, 22 September 2019
• intel/hd graphics 620
  '''HD Graphics 620''' is a family of {{intel|Gen 9.5}} [[integrated graphics processor]] designed by [[Intel]] for their {{intel|Kaby Lake|l=arch}}-based micropro <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="5">Major Feature Diff</th></tr>
  4 KB (561 words) - 12:23, 27 August 2017
• intel/hd graphics 630
  '''HD Graphics 630''' is a family of {{intel|Gen 9.5}} [[integrated graphics processor]] designed by [[Intel]] for their {{intel|Kaby Lake|l=arch}}-based micropro <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr>
  5 KB (615 words) - 01:11, 7 January 2018
• ibm/microarchitectures/power9
  ...ot offered this iteration). These modules allow IBM to address the various processor models with support for the different configurations such as bandwidth/line ...s including [[integer]] and [[floating point]] supporting [[scalar]] and [[vector]] operations. IBM claims this setup allows for higher utilization of resour
  14 KB (1,905 words) - 23:38, 22 May 2020
• acorn/microarchitectures/arm1
  ...he form of evaluation systems. At that time the ARM1 was the simplest RISC processor produced. ...cessor sets the [[PC]] to a specific memory address within the [[interrupt vector table]].
  12 KB (1,886 words) - 12:56, 14 January 2021
• amd/microarchitectures/zen 3
  ! Processor Series !! Cores/Threads !! Market * {{x86|VAES}} - 256-bit Vector AES instructions
  15 KB (1,978 words) - 22:13, 6 April 2023
• loongson/godson 2/2g
  '''Godson-2G''' ('''龙芯2G''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of ...iwu Hu, Yunji Chen. "GS464V: A High-Performance Low-Power XPU with 512-Bit Vector Extension". HotChips 22 (2010).
  4 KB (455 words) - 16:31, 13 December 2017
• intel/cores/skylake s
  <tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="4">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">I |?has advanced vector extensions 2
  4 KB (619 words) - 04:05, 21 March 2019
• amd/cores/rome
  ...way multiprocessing with up to a maximum of 64 cores (and 128 threads) per processor for a total of up to 128 cores (and 256 threads) for a 2-way MP system. Tho |theme=vector
  6 KB (828 words) - 16:47, 15 April 2020
• amd/cores/milan
  ...MD EPYC™ 7003 Series CPUs Set New Standard as Highest Performance Server Processor"] (Press release). AMD.com. March 15, 2021. Retrieved April 2021.</ref> ...ng as well as 2-way multithreading with up to 64 cores and 128 threads per processor. AMD claims up to 15% better performance per cost and 25% more performance
  19 KB (2,734 words) - 01:26, 31 May 2021
• intel/cores/skylake y
  <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="6">Major Feature Diff</th></tr> |?has advanced vector extensions 2
  4 KB (571 words) - 06:30, 6 April 2019
• intel/cores/skylake h
  '''Skylake H''' ('''SKL-H''') is the processor core for [[Intel]]'s line of performance mobile processors based on the {{i <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="4">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">I
  5 KB (630 words) - 02:08, 16 January 2019
• acorn/microarchitectures/arm2
  ...file]]). This was increased from 25 in the {{\\|ARM1}} for the purpose of processor status. As with the {{\\|ARM1}}, Register 15 ({{arm|R15}}) is still the [[P ...cessor sets the [[PC]] to a specific memory address within the [[interrupt vector table]].
  14 KB (2,093 words) - 04:42, 10 July 2018
• intel/cores/skylake u
  <tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="2">{{intel|Turbo Boost}}</th><th>Memory</th><th colspan="3 |?has advanced vector extensions 2
  5 KB (743 words) - 08:07, 21 August 2017
• x86/avx-512
  {{x86 title|Advanced Vector Extensions 512 (AVX-512)}}{{x86 isa main}} '''Advanced Vector Extensions 512''' ('''AVX-512''') is collective name for a number of {{arch
  83 KB (13,667 words) - 15:45, 16 March 2023
• intel/frequency behavior
  ...'''LFM''') and is the lowest frequency-voltage operating point for a given processor. The upper bound is called the '''High Frequency mode''' ('''HFM''') and is ...drop into a lower [[P-State]] when not under any demanding workloads. The processor will switch around between the various P-States as needed and as dictated b
  5 KB (797 words) - 01:10, 1 June 2020
• ibm/microarchitectures/z14
  * Central Processor Assist for Cryptographic Function (CPACF) ** Dedicated co-processor for each core
  8 KB (1,204 words) - 14:02, 23 September 2019
• intel/microarchitectures/skylake (server)
  * {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory * {{x86|XSAVES|<code>XSAVES</code>}} - Save processor supervisor-mode extended states to memory.
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/microarchitectures/goldmont plus
  *** Vector divisions and square roots are faster * {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID
  9 KB (1,128 words) - 13:28, 17 July 2023
• intel/cores/sandy bridge m
  {{comp table header|main|10:Main processor|3:IGP|6:Major Feature Diff}} |?has advanced vector extensions
  3 KB (489 words) - 15:57, 4 September 2017
• nudt/matrix-2000
  '''Matrix-2000''' ('''MT-2000''') is a {{arch|64}} [[128-core]] [[many-core processor]] designed by [[NUDT]] and introduced in [[2017]]. This chip was designed e ...ended 256-bit vector instruction set architecture along with two 256-bit [[vector processing units]] (VPU). Each core is capable of performing 16 double-prec
  6 KB (894 words) - 07:26, 19 July 2019
• accelerator card
  ...or card featuring 8 cores each capable of 307 GFLOPS/core for accelerating vector processing.]] ...[hardware acceleration|acceleration]] of domain-specific workloads such as vector operations, [[artificial neural network|ANNs]], cryptography, and graphics.
  3 KB (352 words) - 05:41, 30 November 2019
• hardware acceleration
  ...ng those intense computations to be done by specialized hardware, the main processor's utilization goes down, freeing up resources for other workloads. * Vector Manipulation
  1 KB (171 words) - 20:29, 19 November 2017

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