Page title matches

• 128-bit architecture
  ...chitecture that has a [[datapath]] width or a highest [[operand]] width of 128 bits or 16 [[octet]]s. These architectures typically have a matching [[regi ...number of microarchitectures that introduced various extensions to handle 128-bit arithmetic in a more specialized way.
  593 bytes (81 words) - 09:51, 20 July 2018

Page text matches

• mirc/hash tables
  var %hash $calc(($xor(%hash,$calc(%hash /128)) * 9) % 4294967296)
  30 KB (5,149 words) - 01:46, 30 November 2018
• mirc/commands/bread
  * '''-a''' - Modifier for -t switch, codepoints 128-255 are not encoded to UTF8 if no codepoint above 255 is found
  2 KB (366 words) - 22:53, 16 August 2022
• mirc/commands/bset
  ...these last 2 methods do not strictly conform to -ta because they add ASCII 128-255 as single bytes even when codepoint 256+ is present. Also, the last met
  9 KB (1,432 words) - 18:47, 2 May 2023
• mirc/commands/color
  ;Change the color of 1 in the color palette to purple (128, 0, 128). //color 1 $rgb(128,0,128)
  2 KB (255 words) - 22:38, 3 May 2023
• mirc/component object model
  |i1 || single byte signed integer || -128 to 127 |decimal || Holds signed 128-bit (16-byte) values representing 96-bit (12-byte) integer numbers. || +/-7
  27 KB (3,608 words) - 11:41, 25 October 2018
• mirc/commands/colour
  ;Change the color of 1 in the color palette to purple (128, 0, 128). //colour 1 $rgb(128,0,128)
  2 KB (255 words) - 19:13, 15 June 2017
• amd/epyc/9174f
  |pcie lanes=128
  4 KB (693 words) - 01:48, 2 April 2023
• amd/epyc/9224
  |pcie lanes=128
  4 KB (666 words) - 01:48, 2 April 2023
• mirc/identifiers/$decode
  ...-greater that's a multiple of 64, whose UTF8 encoding ends with byte value 128. In these cases, $decode matches the final byte of the message as if it is ...could end with 0x00, or with text strings which could end with byte value 128.
  12 KB (1,991 words) - 09:37, 14 November 2022
• mirc/identifiers/$encode
  ...Parameter#4. Salt is interpreted in ANSI mode without encoding codepoints 128-255 to 2 bytes, and codepoint >255 is an invalid parameter. Warning: $encod ...length 8 if shorter. Parameter#4 is interpreted in ANSI mode, where ASCII 128-255 are not UTF-8 encoded into byte-pairs and codepoint > 255 are invalid.
  33 KB (5,484 words) - 04:32, 16 April 2023
• population count
  ...|| VPOPCNTB/VPOPCNTW || Parallel population count on 8/16-bit operands in 128/256/512-bit vector ...|| VPOPCNTD/VPOPCNTQ || Parallel population count on 32/64-bit operands in 128/256/512-bit vector
  3 KB (447 words) - 01:55, 14 March 2023
• mirc/unicode
  ...: 8 bits can be used to represent 256 values. Code pages all use the first 128 values for ASCII, and then each code page adds the required characters for * 128 - SHIFTJIS_CHARSET
  10 KB (1,506 words) - 10:13, 17 February 2024
• mirc/identifiers/$input
  * '''128''' - show the question icon ('q')
  6 KB (1,062 words) - 07:12, 1 February 2024
• Lists of microprocessors
  ...tecture|60-bit]] - [[64-bit architecture|64-bit]] - [[128-bit architecture|128-bit]] - [[256-bit architecture|256-bit]] - [[512-bit architecture|512-bit]]
  2 KB (248 words) - 23:48, 28 October 2015
• hitachi/hmcs40
  ...arithmetic. 512 to 2,048 Words (10-bit ea) of program [[ROM]]. Additional 128 Words (10-bit ea) of pattern ROM. 32 to 160 digits (4-bit ea) of data [[RAM
  4 KB (400 words) - 19:05, 24 May 2016
• national semiconductor/cops ii
  | {{\|COP310C}} || 512 B || 128 b || 4.098 kHz - 62.5 kHz || DIP24 || CMOS, extended temperature version of | {{\|COP311C}} || 512 B || 128 b || 4.098 kHz - 62.5 kHz || DIP16 || CMOS, extended temperature version of
  6 KB (685 words) - 22:49, 5 February 2016
• epson/s1c63
  | package 5 = QFP15-128 | package 8 = TQFP15-128
  5 KB (620 words) - 21:04, 7 February 2016
• number system
  &= 128 + 32 + 8 + 4 + 2 + 0.25 + 0.125 \\
  7 KB (935 words) - 07:08, 2 December 2015
• intel/core i7/i7-4950hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  4 KB (404 words) - 16:22, 13 December 2017
• intel/core i7/i7-4960hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (401 words) - 14:24, 12 February 2019
• intel/core i7/i7-4980hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (400 words) - 16:22, 13 December 2017
• intel/core i7/i7-4860hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4870hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (386 words) - 09:14, 26 December 2017
• intel/core i7/i7-4750hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (401 words) - 16:22, 13 December 2017
• intel/core i7/i7-4760hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (397 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770hq
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  3 KB (398 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770r
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  4 KB (406 words) - 16:22, 13 December 2017
• intel/core i5/i5-4670r
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  4 KB (404 words) - 16:19, 13 December 2017
• intel/core i5/i5-4570r
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  3 KB (401 words) - 16:19, 13 December 2017
• intel/core i7/i7-4860eq
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  3 KB (396 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850eq
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  3 KB (391 words) - 16:22, 13 December 2017
• intel/xeon e3/e3-1284l v3
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  3 KB (399 words) - 16:27, 13 December 2017
• intel/celeron/3855u
  |l1 cache=128 KiB
  4 KB (596 words) - 16:15, 13 December 2017
• intel/celeron/3955u
  |l1 cache=128 KiB
  4 KB (596 words) - 16:15, 13 December 2017
• intel/core i3/i3-6098p
  |l1 cache=128 KiB
  4 KB (627 words) - 16:17, 13 December 2017
• intel/core i5/i5-6402p
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (627 words) - 16:20, 13 December 2017
• intel/core i7/i7-6498du
  |l1 cache=128 KiB
  4 KB (640 words) - 02:21, 16 January 2019
• intel/core i5/i5-6198du
  |l1 cache=128 KiB
  4 KB (650 words) - 02:21, 16 January 2019
• intel/iris pro graphics 5200
  ...tegrated graphic processors with an additional L4$ of {{intel|crystal well|128 MB eDRAM}}.
  2 KB (300 words) - 19:39, 3 January 2016
• intel/core i7/i7-5950hq
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (407 words) - 16:22, 13 December 2017
• intel/core i7/i7-5850hq
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (401 words) - 16:22, 13 December 2017
• intel/core i7/i7-5850eq
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (395 words) - 16:22, 13 December 2017
• intel/core i7/i7-5750hq
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (424 words) - 16:22, 13 December 2017
• intel/core i7/i7-5775r
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (405 words) - 16:22, 13 December 2017
• intel/core i7/i7-5775c
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (460 words) - 15:03, 24 March 2019
• intel/core i5/i5-5675r
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (409 words) - 16:19, 13 December 2017
• intel/core i5/i5-5675c
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (454 words) - 18:17, 2 November 2019
• intel/core i5/i5-5575r
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (409 words) - 16:19, 13 December 2017
• intel/core i5/i5-5350h
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (415 words) - 16:19, 13 December 2017
• intel/core i3/i3-6167u
  |l1 cache=128 KiB
  4 KB (631 words) - 16:18, 13 December 2017
• intel/core i5/i5-6287u
  |l1 cache=128 KiB
  4 KB (649 words) - 16:20, 13 December 2017
• baikal/baikal-t1
  |l1 cache=128 KiB
  3 KB (323 words) - 16:10, 13 December 2017
• mirc/commands/parseline
  * '''-a''' - modifier for -t and -b, codepoints 128-255 are not encoded to UTF8 if no codepoint above 255 is found
  3 KB (435 words) - 13:00, 11 May 2023
• mitsubishi/m350xx
  | {{\|M35011}} || 24x10 || 240 || 4x4 || 128x64 || 128 || background composition | {{\|M35013}} || 24x10 || 240 || 4x4 || 62x64 || 128 || background composition
  4 KB (438 words) - 01:00, 19 May 2016
• motorola/mc14154x
  | {{\|MC141540}} || 320 ([[CGA]]) || 10x24 || 10x16 || 128 || 4 selectable colors per row ...1543}} || 320 ([[CGA]]), 480 ([[EGA]]), 640 ([[VGA]]) || 15x30 || 10x16 || 128 || char-by-char coloring
  2 KB (200 words) - 01:00, 19 May 2016
• myson technology/osd
  | {{\|MTV004}} || || 10x24 || 12x16 || 128 || | {{\|MTV016}} || up to 1524 || 10x24 || 12x18 || 128 ||
  1 KB (101 words) - 13:01, 12 February 2016
• intel/atom
  ...capabilities. Models support up to dual-channel DDR4 ECC memory and either 128 GiB or 256 GiB of memory. All models support everything up to SSE4.2 (SMM,
  17 KB (2,292 words) - 09:32, 16 July 2019
• 14 nm lithography process
  | Metal 3 || 128 nm * Song, Taejoong, et al. "A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications." IEEE
  17 KB (2,243 words) - 19:32, 25 May 2023
• intel/atom x7/z8750
  |l1i cache=128 KiB
  4 KB (462 words) - 16:15, 13 December 2017
• intel/atom x7/z8700
  |l1i cache=128 KiB
  4 KB (472 words) - 16:15, 13 December 2017
• intel/atom x5/x5-e8000
  |l1i cache=128 KiB
  4 KB (475 words) - 17:42, 27 March 2018
• intel/atom x5/x5-z8500
  |l1i cache=128 KiB
  5 KB (573 words) - 16:15, 13 December 2017
• intel/atom x5/x5-z8550
  |l1i cache=128 KiB
  5 KB (572 words) - 16:15, 13 December 2017
• intel/atom x5/x5-z8300
  |l1i cache=128 KiB
  6 KB (744 words) - 18:35, 14 January 2019
• intel/atom x5/x5-z8350
  |l1i cache=128 KiB
  5 KB (736 words) - 03:44, 19 August 2023
• intel/atom x5/x5-z8330
  |l1i cache=128 KiB
  5 KB (558 words) - 16:15, 13 December 2017
• intel/microarchitectures/bonnell
  *** Shrinkable from 512 KiB to 128 KiB (2-way) ...is [[competitively shared]] between threads. The branch buffer target has 128 entries (4-way by 32 sets). While [[unconditional jumps]] are not recorded
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/saltwell
  *** Shrinkable from 512 KiB to 128 KiB (2-way) * Branch buffer target has 128 entries (4-way, 32 sets)
  7 KB (872 words) - 19:42, 30 November 2017
• intel/microarchitectures/airmont
  * DTLB table size doubled (128 entries -> 256 entries)
  5 KB (568 words) - 19:40, 30 November 2017
• intel/microarchitectures/goldmont
  ** DIV is more than twice as fast as Airmont, 13 cycles for most divides, 128-bit/64-bit are ~42 cycles.
  7 KB (956 words) - 23:05, 23 March 2020
• intel/pentium (2009)/j3710
  |l1i cache=128 KiB
  4 KB (529 words) - 17:41, 27 March 2018
• intel/pentium (2009)/n3710
  |l1i cache=128 KiB
  5 KB (701 words) - 17:40, 27 March 2018
• intel/pentium (2009)/n3700
  |l1i cache=128 KiB
  4 KB (540 words) - 17:40, 27 March 2018
• intel/celeron/n3150
  |l1i cache=128 KiB
  5 KB (724 words) - 06:10, 2 December 2018
• intel/celeron/n3160
  |l1i cache=128 KiB
  4 KB (535 words) - 17:39, 27 March 2018
• intel/celeron/j3160
  |l1i cache=128 KiB
  4 KB (533 words) - 17:41, 27 March 2018
• intel/xeon d
  * '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM) * '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM)
  13 KB (1,784 words) - 08:04, 6 April 2019
• intel/xeon d/d-1540
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (593 words) - 02:17, 1 April 2019
• intel/xeon d/d-1520
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (593 words) - 02:18, 1 April 2019
• intel/xeon d/d-1518
  |max memory=128 GiB ...nm process]]. It operates at 2.2 GHz with a TDP of 35 W and supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (582 words) - 02:21, 1 April 2019
• intel/xeon d/d-1521
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (596 words) - 02:18, 1 April 2019
• intel/xeon d/d-1527
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (595 words) - 02:16, 1 April 2019
• intel/xeon d/d-1528
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.5 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (595 words) - 02:16, 1 April 2019
• intel/xeon d/d-1531
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (593 words) - 02:17, 1 April 2019
• intel/xeon d/d-1537
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.3 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (595 words) - 02:16, 1 April 2019
• intel/xeon d/d-1541
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.
  4 KB (596 words) - 02:17, 1 April 2019
• intel/xeon d/d-1548
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.
  4 KB (595 words) - 09:36, 14 May 2021
• intel/xeon d/d-1577
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.
  4 KB (595 words) - 02:16, 1 April 2019
• intel/xeon d/d-1567
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (595 words) - 02:18, 1 April 2019
• intel/xeon d/d-1571
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.
  4 KB (595 words) - 02:16, 1 April 2019
• intel/xeon d/d-1557
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (595 words) - 02:17, 1 April 2019
• intel/microarchitectures/broadwell (client)
  |l4=128 MiB *** 128 MiB
  14 KB (1,891 words) - 14:37, 6 January 2022
• intel/microarchitectures/haswell (client)
  |l4=128 MB *** 128 MB
  27 KB (3,750 words) - 06:57, 18 November 2023
• 16 nm lithography process
  ...rocess 16 nm which reflects those relaxed pitches. TSMC demonstrated their 128 Mebibit [[SRAM]] wafer from their 16 nm HKMG FinFET process at the 2014 IEE ! colspan="2" | TSMC 128 Mib SRAM demo 16 nm wafer
  4 KB (580 words) - 17:00, 26 March 2019
• intel/core i7ee/i7-920xm
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (522 words) - 20:46, 4 October 2018
• intel/core i7ee/i7-940xm
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (537 words) - 15:01, 13 December 2019
• intel/microarchitectures/sandy bridge (client)
  **** Increased to 168 entries (from 128) ***** 256-bit operations (from 128-bit)
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  |side cache=128 MiB *** 64 MiB & 128 MiB [[eDRAM]]
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  *** 64 MiB & 128 MiB [[eDRAM]] **** 128 entries; 8-way set associative
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/core i7ee/i7-975
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (415 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-965
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (415 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-6950x
  |max memory=128 GiB | max memory = 128 GiB
  4 KB (564 words) - 14:29, 24 March 2019
• intel/core i7ee/i7-2920xm
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (710 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-2960xm
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (710 words) - 03:49, 26 June 2018
• intel/core i7ee/i7-3940xm
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (573 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-3920xm
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (558 words) - 23:13, 12 March 2019
• intel/core i7ee/i7-4930mx
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (544 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-4940mx
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (542 words) - 16:24, 13 December 2017
• intel/core i7/i7-6650u
  |l1 cache=128 KiB
  4 KB (649 words) - 16:22, 13 December 2017
• intel/core i7/i7-6660u
  |l1 cache=128 KiB
  4 KB (649 words) - 16:22, 13 December 2017
• intel/core i7/i7-6600u
  |l1 cache=128 KiB
  4 KB (654 words) - 17:22, 26 March 2018
• 10 nm lithography process
  Samsung demonstrated their 128 Megabit [[SRAM]] wafer from their 10nm FinFET process. Samsung, which unlik ! colspan="2" | Samsung 128 Mib SRAM demo 10 nm wafer
  14 KB (1,903 words) - 06:52, 17 February 2023
• 150 nm lithography process
  ...Hwasung-gun, Kyonggi Province. Line 10 was dedicated for the production of 128 MiB, 256 MiB and [[Rambus]] [[DRAM]]s on a 150 nm process. Line 10 opened i
  2 KB (238 words) - 02:56, 27 September 2020
• intel/xeon e3/e3-1280 v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (485 words) - 00:29, 7 April 2018
• intel/xeon e3/e3-1275 v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (620 words) - 00:27, 7 April 2018
• intel/xeon e3/e3-1270 v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (490 words) - 00:29, 7 April 2018
• intel/xeon e3/e3-1260l v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (489 words) - 16:26, 13 December 2017
• intel/xeon e3/e3-1245 v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (609 words) - 00:29, 7 April 2018
• intel/xeon e3/e3-1240l v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (484 words) - 16:26, 13 December 2017
• intel/xeon e3/e3-1240 v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (490 words) - 00:29, 7 April 2018
• intel/xeon e3/e3-1235l v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (608 words) - 16:26, 13 December 2017
• intel/xeon e3/e3-1230 v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (506 words) - 00:29, 7 April 2018
• intel/xeon e3/e3-1225 v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (620 words) - 00:24, 7 April 2018
• intel/xeon e3/e3-1220 v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (490 words) - 00:29, 7 April 2018
• intel/xeon e3/e3-1268l v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (624 words) - 00:27, 7 April 2018
• intel/xeon e3/e3-1535m v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (648 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1505m v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (646 words) - 05:24, 14 July 2018
• intel/xeon e3/e3-1575m v5
  ...] operating at 350 MHz with a turbo frequency of 1.1 GHz and incorporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR |l1i cache=128 KiB
  4 KB (654 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1545m v5
  ...operating at 350 MHz with a turbo frequency of 1.05 GHz and incorporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR |l1i cache=128 KiB
  4 KB (654 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1515m v5
  ...s]] operating at 350 MHz with a turbo frequency of 1 GHz and incorporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR |l1i cache=128 KiB
  4 KB (663 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1505l v5
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (640 words) - 16:27, 13 December 2017
• intel/iris graphics/pro p580
  ...ake's highest tier GPU incorporating 72 execution units as well as a large 128 MiB [[eDRAM]] of cache. The P580 GPU is found in high-end mobile workstatio
  4 KB (489 words) - 13:38, 9 July 2017
• intel/pentium (2009)/g4520
  |l1 cache=128 KiB
  4 KB (607 words) - 16:25, 13 December 2017
• intel/pentium (2009)/g4500t
  |l1 cache=128 KiB
  4 KB (610 words) - 16:25, 13 December 2017
• intel/pentium (2009)/g4500
  |l1 cache=128 KiB
  4 KB (616 words) - 16:25, 13 December 2017
• intel/pentium (2009)/g4400
  |l1 cache=128 KiB
  4 KB (623 words) - 06:18, 5 November 2020
• intel/pentium (2009)/g4400t
  |l1 cache=128 KiB
  4 KB (610 words) - 16:25, 13 December 2017
• intel/pentium (2009)/g4400te
  |l1 cache=128 KiB
  4 KB (606 words) - 16:25, 13 December 2017
• intel/pentium (2009)/4405y
  |l1 cache=128 KiB
  4 KB (581 words) - 17:57, 28 August 2018
• intel/pentium (2009)/4405u
  |l1 cache=128 KiB
  4 KB (597 words) - 16:25, 13 December 2017
• nvidia
  * {{\|Riva 128}}
  3 KB (261 words) - 16:48, 20 March 2024
• intel/xeon d/d-1529
  |max memory=128 GiB ...4 nm process]]. It operates at 1.3 GHz with a TDP of 20 W supporting up to 128 GiB of dual-channel DDR4-1600 memory.
  4 KB (613 words) - 02:20, 1 April 2019
• intel/xeon d/d-1539
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.2 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (596 words) - 02:16, 1 April 2019
• intel/xeon d/d-1559
  |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  4 KB (596 words) - 02:16, 1 April 2019
• intel/core m/m7-6y75
  |l1 cache=128 KiB
  4 KB (613 words) - 17:58, 28 August 2018
• intel/core m/m5-6y54
  |l1 cache=128 KiB
  4 KB (613 words) - 17:58, 28 August 2018
• intel/core m/m5-6y57
  |l1 cache=128 KiB
  4 KB (613 words) - 17:58, 28 August 2018
• intel/core m/m3-6y30
  |l1 cache=128 KiB
  4 KB (613 words) - 17:58, 28 August 2018
• intel/core i3/i3-6100u
  |l1 cache=128 KiB
  4 KB (616 words) - 16:17, 13 December 2017
• intel/core i3/i3-6300
  |l1 cache=128 KiB
  4 KB (609 words) - 16:18, 13 December 2017
• intel/core i3/i3-6300t
  |l1 cache=128 KiB
  4 KB (618 words) - 16:18, 13 December 2017
• intel/core i3/i3-6100te
  |l1 cache=128 KiB
  4 KB (612 words) - 16:17, 13 December 2017
• intel/core i3/i3-6320
  |l1 cache=128 KiB
  4 KB (611 words) - 16:18, 13 December 2017
• intel/core i3/i3-6100
  |l1 cache=128 KiB
  4 KB (615 words) - 16:17, 13 December 2017
• intel/core i3/i3-6100t
  |l1 cache=128 KiB
  4 KB (615 words) - 16:17, 13 December 2017
• intel/core i3/i3-6102e
  |l1 cache=128 KiB
  4 KB (613 words) - 16:17, 13 December 2017
• intel/core i3/i3-6100h
  |l1 cache=128 KiB
  4 KB (613 words) - 02:11, 16 January 2019
• intel/core i3/i3-6100e
  |l1 cache=128 KiB
  4 KB (613 words) - 16:17, 13 December 2017
• intel/core i3/6320t
  |l1 cache=128 KiB
  4 KB (609 words) - 16:16, 13 December 2017
• intel/core i3/6120t
  |l1 cache=128 KiB
  4 KB (606 words) - 16:16, 13 December 2017
• intel/core i5
  * '''Mem:''' Up to 128 GiB; DDR4 up to 3200 MT/s or DDR5 up to 5600 MT/s
  34 KB (4,663 words) - 20:38, 20 February 2023
• 128-bit architecture
  ...chitecture that has a [[datapath]] width or a highest [[operand]] width of 128 bits or 16 [[octet]]s. These architectures typically have a matching [[regi ...number of microarchitectures that introduced various extensions to handle 128-bit arithmetic in a more specialized way.
  593 bytes (81 words) - 09:51, 20 July 2018
• mathstar/arrix
  ** 128 Byte, dualport RAM or FIFO
  4 KB (492 words) - 00:37, 28 June 2016
• intel/microarchitectures/coffee lake
  |l4=128 MiB *** 64 MiB & 128 MiB [[eDRAM]]
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/ryzen 3/pro 4450u
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (745 words) - 00:23, 26 March 2023
• phytium/feiteng/ft-1500a-4
  |l1i cache=128 KiB |l1d cache=128 KiB
  2 KB (286 words) - 14:52, 26 March 2019
• intel/core i3/i3-7100u
  |l1 cache=128 KiB
  4 KB (626 words) - 16:18, 13 December 2017
• intel/core m/m3-7y30
  |l1 cache=128 KiB
  4 KB (654 words) - 17:58, 28 August 2018
• intel/core i7/i7-7y75
  |l1 cache=128 KiB
  4 KB (660 words) - 18:04, 28 August 2018
• intel/core i7/i7-7500u
  |l1 cache=128 KiB
  4 KB (650 words) - 17:50, 13 January 2021
• intel/core i5/i5-7y54
  |l1 cache=128 KiB
  4 KB (652 words) - 18:04, 28 August 2018
• intel/core i5/i5-7200u
  |l1 cache=128 KiB
  5 KB (799 words) - 17:27, 17 February 2023
• amd/microarchitectures/k6
  ** 128 entry TLB
  4 KB (578 words) - 18:57, 22 May 2019
• amd/microarchitectures/zen
  ** Larger Retire Queue (192, up from 128) .... On the floating point side, there is a different scheduler to handle the 128-bit FP operations. Zen support all modern {{x86|extensions|x86 extensions}}
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  | {{amd|Rome|l=core}} || Up to 64/128 || High-end server [[multiprocessors]] | {{amd|Castle Peak|l=core}} || Up to 64/128 || Workstation & enthusiasts market processors
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/pentium (2009)/j4205
  |l1i cache=128 KiB
  6 KB (633 words) - 16:25, 13 December 2017
• intel/celeron/j3455
  |l1i cache=128 KiB
  5 KB (584 words) - 18:02, 9 February 2019
• intel/pentium (2009)/n4200
  |l1i cache=128 KiB
  6 KB (642 words) - 16:25, 13 December 2017
• intel/celeron/n3450
  |l1i cache=128 KiB
  7 KB (837 words) - 23:15, 25 August 2019
• pezy/pezy-1
  |l1 cache=128 KiB
  2 KB (343 words) - 03:48, 20 October 2018
• pezy/pezy-scx/pezy-sc3
  ...SC2|the previous}} PCIe interface with a custom optics interface featuring 128 lanes supporting a bandwidth of 256 GB/s.
  3 KB (349 words) - 12:41, 28 September 2019
• amd/k6-2+
  ...h was also released at the same time, the K6-2+ only had half the [[L2$]] (128 KB), but still operated at full core speed. Due to the processor shrink, th
  2 KB (341 words) - 04:25, 26 October 2018
• amd/k6-2+/k6-2e+-500acr
  |l2 cache=128 KiB
  2 KB (299 words) - 06:06, 24 March 2023
• intel/core i7/i7-7700
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (674 words) - 19:57, 22 October 2019
• intel/core i7/i7-7700t
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (694 words) - 23:04, 15 April 2019
• intel/core i7/i7-7700k
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (699 words) - 11:45, 15 April 2019
• intel/core i5/i5-7600k
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (665 words) - 12:47, 4 June 2018
• intel/core i5/i5-7600
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (658 words) - 16:20, 13 December 2017
• intel/core i5/i5-7600t
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (677 words) - 16:20, 13 December 2017
• intel/core i5/i5-7500
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (665 words) - 21:59, 13 September 2018
• intel/core i5/i5-7500t
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (684 words) - 16:20, 13 December 2017
• intel/core i5/i5-7400
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (659 words) - 16:20, 13 December 2017
• intel/core i5/i5-7400t
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (677 words) - 16:20, 13 December 2017
• intel/xeon e5/e5-2637 v4
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (493 words) - 16:27, 13 December 2017
• intel/xeon e5/e5-2623 v4
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (493 words) - 16:27, 13 December 2017
• intel/xeon e5/e5-1630 v4
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (637 words) - 01:04, 24 December 2017
• intel/xeon e5/e5-1620 v4
  |l1i cache=128 KiB |l1d cache=128 KiB
  5 KB (637 words) - 01:04, 24 December 2017
• intel/xeon e5/e5-1607 v4
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (485 words) - 16:27, 13 December 2017
• intel/xeon e5/e5-1603 v4
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (477 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1205 v6
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (605 words) - 16:26, 13 December 2017
• intel/xeon e3/e3-1280 v6
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (489 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1275 v6
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (625 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1270 v6
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (489 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1245 v6
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (616 words) - 16:26, 13 December 2017
• intel/xeon e3/e3-1240 v6
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (489 words) - 16:26, 13 December 2017
• intel/xeon e3/e3-1230 v6
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (492 words) - 16:26, 13 December 2017
• intel/xeon e3/e3-1225 v6
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (667 words) - 16:26, 13 December 2017
• intel/xeon e3/e3-1220 v6
  |l1i cache=128 KiB |l1d cache=128 KiB
  3 KB (540 words) - 10:01, 1 November 2018
• intel/core i3/i3-7300
  |l1 cache=128 KiB
  5 KB (663 words) - 13:08, 28 March 2021
• intel/core i3/i3-7310t
  |l1 cache=128 KiB
  4 KB (621 words) - 16:18, 13 December 2017
• intel/pentium gold/g4620
  |l1 cache=128 KiB
  4 KB (651 words) - 15:08, 24 December 2017
• amd/athlon mp
  ...den, Germany]]. The core implements an exclusive 256 [[KiB]] [[L2$]] and a 128 KiB [[L1$]]. As with all [[Socket A]] processors ({{decc|EV6}} system bus),
  11 KB (1,571 words) - 18:57, 17 November 2016
• intel/core i3/i3-6006u
  |l1 cache=128 KiB
  5 KB (687 words) - 02:21, 16 January 2019
• intel/core i3/i3-7350k
  |l1 cache=128 KiB
  4 KB (644 words) - 14:59, 24 December 2017
• intel/core i3/i3-7320
  |l1 cache=128 KiB
  5 KB (661 words) - 16:18, 13 December 2017
• intel/core i3/i3-7100
  |l1 cache=128 KiB
  5 KB (662 words) - 06:02, 27 October 2018
• intel/pentium gold/g4600
  |l1 cache=128 KiB
  4 KB (655 words) - 16:26, 13 December 2017
• intel/pentium gold/g4560
  |l1 cache=128 KiB
  4 KB (655 words) - 15:07, 24 December 2017
• intel/celeron/g3930
  |l1 cache=128 KiB
  4 KB (638 words) - 13:29, 7 April 2018
• intel/celeron/g3950
  |l1 cache=128 KiB
  4 KB (636 words) - 13:30, 7 April 2018
• intel/celeron/g3930t
  |l1 cache=128 KiB
  4 KB (655 words) - 13:30, 7 April 2018
• intel/core i3/i3-7100t
  |l1 cache=128 KiB
  5 KB (685 words) - 16:18, 13 December 2017
• amd/athlon mp/ahx1000ams3c
  | die area = 128 mm² |l1 cache=128 KiB
  4 KB (542 words) - 15:20, 13 December 2017
• amd/athlon mp/ahx1200ans3b
  | die area = 128 mm² |l1 cache=128 KiB
  4 KB (538 words) - 15:20, 13 December 2017
• amd/athlon mp/ahx1200ams3c
  | die area = 128 mm² |l1 cache=128 KiB
  4 KB (542 words) - 15:20, 13 December 2017
• amd/athlon mp/ahx1200dhs3c
  | die area = 128 mm² |l1 cache=128 KiB
  4 KB (500 words) - 15:20, 13 December 2017
• amd/athlon mp/amp1500dms3c
  | die area = 128 mm² |l1 cache=128 KiB
  4 KB (508 words) - 15:20, 13 December 2017
• amd/athlon mp/amp2000dms3c
  | die area = 128 mm² |l1 cache=128 KiB
  4 KB (508 words) - 15:20, 13 December 2017
• amd/athlon mp/amp1600dms3c
  | die area = 128 mm² |l1 cache=128 KiB
  4 KB (508 words) - 15:20, 13 December 2017
• amd/athlon mp/amp1800dms3c
  | die area = 128 mm² |l1 cache=128 KiB
  4 KB (508 words) - 15:20, 13 December 2017
• amd/athlon mp/amp1900dms3c
  | die area = 128 mm² |l1 cache=128 KiB
  4 KB (508 words) - 15:20, 13 December 2017
• amd/athlon mp/amp2100dms3c
  | die area = 128 mm² |l1 cache=128 KiB
  4 KB (508 words) - 15:20, 13 December 2017
• amd/athlon mp/amsn2000dut3c
  |l1 cache=128 KiB
  4 KB (494 words) - 15:20, 13 December 2017
• amd/athlon mp/amsn2000dkt3c
  |l1 cache=128 KiB
  4 KB (492 words) - 15:20, 13 December 2017
• amd/athlon mp/amsn2200dkt3c
  |l1 cache=128 KiB
  4 KB (493 words) - 15:20, 13 December 2017
• amd/athlon mp/amsn2400dkt3c
  |l1 cache=128 KiB
  4 KB (494 words) - 15:20, 13 December 2017
• amd/athlon mp/amsn2400dut3c
  |l1 cache=128 KiB
  4 KB (492 words) - 15:20, 13 December 2017
• amd/athlon mp/amsn2600dkt3c
  |l1 cache=128 KiB
  4 KB (494 words) - 15:20, 13 December 2017
• amd/athlon mp/amsn2800dut4c
  |l1 cache=128 KiB
  4 KB (488 words) - 15:20, 13 December 2017
• amd/athlon mp/amsn2600dut4c
  |l1 cache=128 KiB
  4 KB (488 words) - 15:20, 13 December 2017
• intel/core i7/i7-820qm
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (493 words) - 16:15, 11 February 2018
• intel/core i7/i7-840qm
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (498 words) - 16:23, 13 December 2017
• intel/core i7/i7-720qm
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (498 words) - 16:23, 13 December 2017
• intel/core i7/i7-740qm
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (498 words) - 08:12, 20 June 2023
• intel/core i7/i7-610e
  |l1 cache=128 KiB
  5 KB (563 words) - 16:22, 13 December 2017
• intel/core i7/i7-620lm
  |l1 cache=128 KiB
  4 KB (558 words) - 16:22, 13 December 2017
• intel/core i7/i7-620m
  |l1 cache=128 KiB
  5 KB (580 words) - 12:03, 26 March 2020
• intel/core i7/i7-620um
  |l1 cache=128 KiB
  5 KB (571 words) - 16:22, 13 December 2017
• intel/core i7/i7-640lm
  |l1 cache=128 KiB
  5 KB (560 words) - 16:22, 13 December 2017

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