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- ...', a complete offerings of their products including [[microprocessors]], [[ROM]]s, [[RAM]]s, [[memory]] peripherals, and various other [[ICs]].4 KB (448 words) - 15:02, 3 October 2019
- |PSP_ROM_CS_L<br/>SPI_TPM_CS_L||O-IO18-S||SPI Chip Select for {{abbr|PSP}} ROM or {{abbr|TPM}}86 KB (17,313 words) - 02:48, 13 March 2023
- |PSP_ROM_CS_L<br/>SPI_TPM_CS_L||O-IO18-S||SPI Chip Select for {{abbr|PSP}} ROM or {{abbr|TPM}} |LPC||ROM,||1=SPI ROM (default)110 KB (21,122 words) - 02:46, 13 March 2023
- ...ur µOPs, the instruction detours through the [[microcode sequencer]] (MS) ROM. When that happens, up to 4 µOPs/cycle are emitted until the microcode seq34 KB (5,187 words) - 06:27, 17 February 2023
- *** Instruction ROM ...simultaneously controls all the compute slices and memory. The instruction ROM is used for executing validation code as well as commonly-used functions. T24 KB (3,792 words) - 04:37, 30 September 2022
- |24406||||AMD Mobile Thermal Kit Documentation and Software CD–ROM||||Family 6 {{amd publ|an|key=AMD-Au1000-BootROM|rev=1.2|title=Mapping a Boot ROM on Alchemy™ Au1000™ Processor from AMD|url=https://web.archive.org/web/181 KB (24,894 words) - 16:24, 12 June 2024
- * 8 KiB ROM3 KB (460 words) - 02:24, 12 February 2020
- |SPI_CS(1-3)_L||Chip Select for SPI ROM or other devices |SPI_ROM_REQ||SPI ROM Request20 KB (3,273 words) - 17:47, 10 May 2023
- ...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,6 KB (862 words) - 01:16, 19 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (607 words) - 00:41, 16 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (614 words) - 00:45, 16 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (594 words) - 00:47, 16 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (594 words) - 00:50, 16 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (562 words) - 01:07, 16 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (559 words) - 01:10, 16 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (566 words) - 01:12, 16 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (573 words) - 01:15, 16 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (553 words) - 01:17, 16 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (546 words) - 01:20, 16 March 2022
- ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su4 KB (553 words) - 01:25, 16 March 2022