• intel/microarchitectures/gen9
  ** Shared Virtual Memory (SVM) improvements ** Floating point atomics (min/max/cmpexch)
  33 KB (4,255 words) - 17:41, 1 November 2018
• ibm/microarchitectures/power9
  |stages max=16 ! SoC Codename || SoC Description || Module || Memory Channels || PCIe || {{ibm|XBUS}} || [[OpenCAPI]]
  14 KB (1,905 words) - 23:38, 22 May 2020
• qualcomm/microarchitectures/falkor
  |stages max=15 === Memory Hierarchy ===
  6 KB (822 words) - 13:01, 19 May 2021
• acorn/microarchitectures/arm1
  * {{arm|26-bit|26-bit address space}} ...simplify system design, these clocks may be stretched to work in-sync with memory access times.
  12 KB (1,886 words) - 12:56, 14 January 2021
• intel/microarchitectures/merced
  | stages max = ** Early zero bubble predictor using Target Address Registers controlled by the compiler
  7 KB (978 words) - 21:16, 20 January 2021
• marvell/armada/610
  | max cpus = 1 | max memory = 2 GiB
  6 KB (683 words) - 16:31, 13 December 2017
• marvell/armada/618
  | max cpus = 1 | max memory = 2 GiB
  6 KB (666 words) - 16:31, 13 December 2017
• marvell/armada/628
  | max cpus = 1 | max memory =
  6 KB (681 words) - 17:03, 24 January 2018
• dec/microarchitectures/alpha 21064
  |stages max=12 ** Separate data & address buses
  4 KB (527 words) - 02:09, 4 August 2017
• acorn/microarchitectures/arm2
  ...ements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory with an average of around 6 MIPS. Unlike the ARM1 which was predominantly a * > 2x MIPS when not bottlenecked by memory
  14 KB (2,093 words) - 04:42, 10 July 2018
• acorn/microarchitectures/arm3
  '''Memory:''' * <code>SWP</code> - Swap word memory-register, Atomic (uninterruptible)
  7 KB (1,035 words) - 06:24, 21 November 2023
• arm holdings/microarchitectures/arm6
  |stages max=1w * 32-bit address space (from {{arm|26-bit}})
  11 KB (1,679 words) - 21:00, 15 May 2024
• x86/avx-512
  : Enables vectorization of loops with possible address conflict. ...g at the least significant byte of the register, and vectors are stored in memory LSB to MSB regardless of vector size and element type. Some instructions gr
  83 KB (13,667 words) - 15:45, 16 March 2023
• intel/microarchitectures/skylake (server)
  |stages max=19 **** Limits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset
  52 KB (7,651 words) - 00:59, 6 July 2022
• microsoft/scorpio engine
  |max cpus=1 |max memory=24 GiB
  15 KB (2,390 words) - 02:54, 17 May 2023
• intel/microarchitectures/cascade lake
  |stages max=19 * "''L''" suffix indicates the SKU is a large memory (4.5 TiB) tier SKU
  32 KB (4,535 words) - 05:44, 9 October 2022
• nvidia/tegra/xavier
  |max cpus=4 ...vative of their {{nvidia|Volta|l=arch}} GPU with a set of finer changes to address the machine learning market, particularly improving inference performance o
  8 KB (1,263 words) - 03:08, 9 December 2019
• cavium/microarchitectures/vulcan
  |stages max=15 ** Memory Subsystem
  17 KB (2,449 words) - 22:11, 4 October 2019
• amd/microarchitectures/zen 4
  ...es attached with full-duplex serial point-to-point links. The IOD contains memory controllers, I/O controllers, microcontrollers for security purposes and po ...four integer/address and two floating point instruction schedulers, 3-way address generation, 5-way integer execution. 4-way 256-bit wide floating point exec
  13 KB (1,821 words) - 19:28, 13 November 2023
• amd/packages/socket tr4
  ...r RDIMMs, while TR4 and sTRX4 processors support only UDIMMs on up to four memory channels. TR4 and sTRX4 omit four of eight PCIe interfaces present on Socke It supports four channels of 72-bit [[DDR4]] memory with up to two DIMMs per channel, four 16-lane PCIe Gen 3 I/O interfaces, e
  86 KB (17,313 words) - 02:48, 13 March 2023

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