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Cortex-X4 (Hunter-ELP) µarch
General Info
Arch Type	CPU
Designer	ARM Holdings
Manufacturer	TSMC
Introduction	2023
Process	10 nm, 7 nm, 5 nm
Core Configs	1, 2, 4, 6, 8, 10, 12, 14
Pipeline
Type	Superscalar, Pipelined
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Stages	384
Decode	10-way
Instructions
ISA	ARMv9.2-A
Extensions	FPU, NEON
Cache
L1I Cache	64 KiB/core 4-way set associative
L1D Cache	64 KiB/core 4-way set associative
L2 Cache	2 MiB/core 8-way set associative
L3 Cache	32 MiB/cluster 16-way set associative
Cores
Core Names	Cortex-X4
Succession
Cortex-X3 (Makalu-ELP) Cortex-X5 (Chaberton-ELP)
Contemporary
Cortex-A720 (Hunter) Cortex-A520 (Hayes)

Cortex-X4 (Hunter-ELP) is the successor to the Cortex-X3 (Makalu-ELP), a performance-enhanced version of the
Cortex-A720 (Hunter), low-power high-performance ARM microarchitecture designed by Arm for the mobile market.

Cortex-X

ARM • Cortex

Year	Cortex-X Core	Cortex-A Core
2020	Cortex-X1 (Hera) Cortex-X1C (Hera-C)	Cortex-A78 (Hercules) Cortex-A78C (Hera Prime)
2021	Cortex-X2 (Matterhorn-ELP)	Cortex-A710 (Matterhorn) Cortex-A510 (Klein)
2022	Cortex-X3 (Makalu-ELP)	Cortex-A715 (Makalu)
2023	Cortex-X4 (Hunter-ELP)	Cortex-A720 (Hunter) Cortex-A520 (Hayes)
2024	Cortex-X5 (Chaberton-ELP) Cortex-X925 (Blackhawk)	Cortex-A720AE (Hunter-AE) Cortex-A725 (Chaberton)
2025	Cortex-X930 (Travis)	Cortex-A730 (Gelas) Cortex-A530 (Nevis)

Architecture

Key changes from Cortex-X3

The processor implements the following changes:

• Instruction set ARMv9.2-A
• Decode width: 10
• Rename / Dispatch width: 10 (increased from 8)
• Reorder buffer (ROB): 384 entries (increased from 320)
• Execution ports: 21 (increased from 15)
• Pipeline length: 10 (increased from 9)
• Up to 2 MiB of private L2 cache (increased from 1 MiB)
• Micro-operation (MOP) cache removed (previously 1.5k entries)
• DSU-120
  • Up to 14 cores (up from 12 cores)
  • Up to 32 MiB of shared L3 cache (increased from 16 MiB)

Performance claims:

• 15% peak performance improvement over the Cortex-X3 in smartphones

(3.4GHz, 2MB L2, 8MB L3).

• 13% IPC uplift over the Cortex-X3, when based on the same process, clock speed,

and L3 cache (but 2 MiB L2 vs 1 MiB L2) setup (also known as ISO-process).

Comparison

"Prime" core

Architecture	Cortex-A78	Cortex-X1	Cortex-X2	Cortex-X3	Cortex-X4	Cortex-X925	Cortex-X930
Code name	Hercules	Hera	Matterhorn-ELP	Makalu-ELP	Hunter-ELP	Blackhawk	Travis
ISA	ARMv8.2-A		ARMv9.0-A		ARMv9.2-A
Peak clock speed	~3.0 GHz			~3.3 GHz	~3.4 GHz	~3.8 GHz	~4.2 GHz
Max in-flight	2x 160	2x 224	2x 288	2x 320	2x 384	2x 768
L0 (Mops entries)	1536	3072		1536	0
L1-I + L1-D	32+32 KiB	64+64 KiB		64+64 KiB		64+64 KiB
L2	128–512 KiB	0.25–1 MiB			0.5–2 MiB	2–3 MiB
L3	0–8 MiB		0–16 MiB		0–32 MiB
Decode width	4	5		6	10	10
Dispatch	6/cycle	8/cycle			10/cycle

Processors

• Snapdragon 7+ Gen 3 (SM7675-AB) • 4nm (TSMC N4P)

1× 2.8 GHz Kryo Prime (Cortex-X4) +

4× 2.6 GHz Kryo Gold (Cortex-A720) +

3× 1.9 GHz Kryo Silver (Cortex-A520)

• Snapdragon 8 Gen 3 (SM8650-AB) • 4 nm (TSMC N4P)

1× @3.3GHz Kryo Prime (Cortex-X4) +

3× @3.15GHz Kryo Gold (Cortex-A720) +

2× @2.96GHz Kryo Gold (Cortex-A720) +

2× @2.27GHz Kryo Silver (Cortex-A520)

• Snapdragon 8 Gen 3 (SM8650-AA) • Q4 2024

1× @3.05GHz Kryo Prime (Cortex-X4) +

5× @2.96GHz Kryo Gold (Cortex-A720) +

2× @2.04GHz Kryo Silver (Cortex-A520)

• Snapdragon 8 Gen 3 for Galaxy (SM8650-AC)

1× @3.4GHz Kryo Prime (Cortex-X4) +

3× @3.15GHz Kryo Gold (Cortex-A720) +

2× @2.96GHz Kryo Gold (Cortex-A720) +

2× @2.27GHz Kryo Silver (Cortex-A520)

• Snapdragon 8s Gen 3 (SM8635)

1× @3.0GHz Kryo Prime (Cortex-X4) +

4× @2.8GHz Kryo Gold (Cortex-A720) +

3× @2.0GHz Kryo Silver (Cortex-A520)