From WikiChip
Difference between revisions of "intel/microarchitectures/cannon lake"
< intel‎ | microarchitectures

(→‎All Cannon Lake Chips)
Line 196: Line 196:
 
           created and tagged accordingly.
 
           created and tagged accordingly.
  
−
           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
+
           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 
-->
 
-->
 
{{comp table start}}
 
{{comp table start}}
−
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
+
<table class="comptable sortable tc4 tc5 tc6">
−
<tr class="comptable-header"><th>&nbsp;</th><th colspan="23">Cannon Lake Chips</th></tr>
+
{{comp table header|main|7:List of Cannon Lake-based Processors}}
−
<tr class="comptable-header"><th>&nbsp;</th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr>
+
{{comp table header|cols|Price|Launched|Cores|Threads|TDP|%Frequency|%Turbo}}
−
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th>Price</th><th>Family</th><th>Platform</th><th>Core</th><th>C</th><th>T</th><th>L3$</th><th>L4$</th><th>TDP</th><th>Freq</th><th>Turbo</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
+
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]
−
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cannon Lake]]
 
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
 +
|?release price
 
  |?first launched
 
  |?first launched
−
|?release price
 
−
|?microprocessor family
 
−
|?platform
 
−
|?core name
 
 
  |?core count
 
  |?core count
 
  |?thread count
 
  |?thread count
−
|?l3$ size
 
−
|?l4$ size
 
 
  |?tdp
 
  |?tdp
 
  |?base frequency#GHz
 
  |?base frequency#GHz
 
  |?turbo frequency (1 core)#GHz
 
  |?turbo frequency (1 core)#GHz
−
|?max memory#GiB
 
−
|?integrated gpu
 
−
|?integrated gpu base frequency
 
−
|?integrated gpu max frequency
 
−
|?has intel turbo boost technology 2_0
 
−
|?has simultaneous multithreading
 
−
|?has advanced vector extensions 2
 
−
|?has intel trusted execution technology
 
−
|?has transactional synchronization extensions
 
−
|?has intel vpro technology
 
−
|?has_intel_vt-d_technology
 
 
  |format=template
 
  |format=template
 
  |template=proc table 3
 
  |template=proc table 3
−
|searchlabel=
+
  |userparam=9
−
|sort=microprocessor family, model number
 
−
|order=asc,asc
 
−
  |userparam=25:19
 
 
  |mainlabel=-
 
  |mainlabel=-
−
|limit=100
 
 
}}
 
}}
−
{{comp table count|ask=[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Cannon Lake]]}}
+
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}

Revision as of 23:50, 29 January 2019

Edit Values
Cannon Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionMay 15, 2018
Process10 nm
Core Configs2
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way?
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512, AVX-512F, AVX-512CD, AVX-512BW, AVX-512DQ, AVX-512VL, AVX-512IFMA, AVX-512VBMI, SHA, UMIP
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
Cores
Core NamesCannon Lake Y,
Cannon Lake U
Succession
Contemporary
Coffee Lake

Cannon Lake (CNL) (formerly Skymont) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannon Lake is expected to be fabricated using a 10 nm process and is set to be introduced in the second half of 2018. Cannon Lake is the "Process" microarchitecture as part of Intel's PAO model.

For mobile, Cannon Lake is expected to be branded as 8th Generation Intel Core i3, Core i5. and Core i7 processors.

Codenames

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Core Abbrev Description Graphics Target
Cannon Lake Y CNL-Y Extremely low power GT2 2-in-1s detachable, tablets, and computer sticks
Cannon Lake U CNL-U Ultra-low Power GT2/GT3 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Cannon Lake H CNL-H High-performance Graphics GT2/GT3 Ultimate mobile performance, mobile workstations
Cannon Lake S CNL-S Performance-optimized lifestyle GT2/GT3 Desktop performance to value, AiOs, and minis
Cannon Lake DT CNL-DT Workstation GT2 Workstations & entry-level servers

Release Dates

Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year.

Process Technology

Cannon Lake is manufactured on Intel's 10 nm process (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ Self-Aligned Quad Patterning (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² SRAM bit cell.

Scaling:

Broadwell Cannon
Lake 		Δ intel 10nm fin.png
14 nm 10 nm
Fin Pitch  42 nm  34 nm 0.81x
Fin Width​   8 nm   7 nm 0.88x
Fin Height​  42 nm  53 nm 1.24x
Gate Pitch  70 nm  54 nm 0.77x
Interconnect Pitch  52 nm  36 nm 0.69x
Cell Height 399 nm 272 nm 0.68x

Compiler support

Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=cannonlake -mtune=cannonlake
GCC -march=cannonlake -mtune=cannonlake
LLVM -march=cannonlake -mtune=cannonlake
Visual Studio ? ?

CPUID

Core Extended
Family 		Family Extended
Model 		Model
Y, U 0 0x6 0x6 0x6
Family 6 Model 102

Architecture

New text document.svg This section is empty; you can help add the missing info by editing this page.

Key changes from Skylake

  • Mobile Processors
    • LPDDR4/LPDDR4X memory support (from LPDDR3)
      • Rates up to 2400 MT/s
  • Gen9.5 → Gen10 graphics
  • Gen10 GPUs
    • HD Graphics 6xx (GT1) → UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from Skylake)
    • HD Graphics 6xx (GT2) → UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from Skylake)

New instructions

Cannon Lake introduced a number of new instructions. See Palm Cove § New Instructions for details.

Block Diagram

Entire SoC Overview

800px

Individual Core

See Palm Cove § Block Diagram.

Gen11 Graphics

See Gen10 Graphics § Block Diagram.

Die

Dual-core

All Cannon Lake Chips

 List of Cannon Lake-based Processors
ModelPriceLaunchedCoresThreadsTDPFrequencyTurbo
i3-8121U15 May 20182415 W
15,000 mW
0.0201 hp
0.015 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
M3-8114Y241.5 GHz
1,500 MHz
1,500,000 kHz
Count: 2

References

  • Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cannon_lake&oldid=86417"
Facts about "Cannon Lake - Microarchitectures - Intel"
RDF feed
codenameCannon Lake +
core count2 +
designerIntel +
first launchedMay 15, 2018 +
full page nameintel/microarchitectures/cannon lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCannon Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +