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Difference between revisions of "intel/microarchitectures/ice lake (client)"
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{{main|intel/microarchitectures/cannonlake#Process_Technology|l1=Cannonlake § Process Technology}} | {{main|intel/microarchitectures/cannonlake#Process_Technology|l1=Cannonlake § Process Technology}} | ||
Tigerlake is set to use the same [[10 nm process]] that was designed for Cannonlake. | Tigerlake is set to use the same [[10 nm process]] that was designed for Cannonlake. | ||
| + | |||
| + | == Architecture == | ||
| + | Not much is known about Ice Lake's architecture. | ||
| + | |||
| + | === Key changes from {{\\|Cannonlake}}=== | ||
| + | {{future information}} | ||
| + | |||
| + | * {{intel|Gen10|l=arch}} → {{intel|Gen11|l=arch}} graphics | ||
Revision as of 16:44, 14 July 2017
| Edit Values | |
| Icelake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2018 |
| Process | 10 nm |
| Succession | |
Icelake (ICL) is a planned microarchitecture by Intel as a successor to Cannonlake. Icelake is expected to be fabricated using a 10 nm process. Icelake is the "Architecture" microarchitecture as part of Intel's PAO model.
Process Technology
- Main article: Cannonlake § Process Technology
Tigerlake is set to use the same 10 nm process that was designed for Cannonlake.
Architecture
Not much is known about Ice Lake's architecture.
Key changes from Cannonlake
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Facts about "Ice Lake (client) - Microarchitectures - Intel"
| codename | Icelake + |
| designer | Intel + |
| first launched | 2018 + |
| full page name | intel/microarchitectures/ice lake (client) + |
| instance of | microarchitecture + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Icelake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |