Revision as of 00:44, 28 January 2017

Kaby Lake is Intel's 7th Generation Core i7 MPUs.

Kaby Lake (KBL) is Intel's successor to Skylake, an enhanced 14 nm process microarchitecture for mainstream desktops, servers, and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's PAO model. The microarchitecture was developed by Intel's R&D center in Haifa, Israel. Cannonlake was originally set to replace Skylake as the next microarchitecture using a 10 nm process, however Intel later revised their roadmap to include Kaby Lake (with Cannonlake being pushed back to 2017).

For desktop and mobile, Kaby Lake is branded as 7th Generation Intel Core i3, Core i5. and Core i7 processors. For server class processors, Intel branded it as Xeon E3 v6, Xeon E5 v6, and Xeon E7 v6.

Codenames

Brands

Intel released Kaby Lake under 6 main brand families:

Release Dates

Kaby Lake is set to be released in two phases. The first phase was announced in August of 2016 and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by Kaby Lake Y and Kaby Lake U CPUs. Intel released mainstream Kaby Lake S and Kaby Lake H processors on January 3, 2017 in time for CES 2017. Additionally, Kaby Lake X are expecting to be released in late August during Gamescom 2017.

Process Technology

Main article: Broadwell § Process Technology

Kaby Lake uses a modified and improved 14 nm process used for the Broadwell microarchitecture (And Skylake). Intel calls the process "14nm+". Intel claims the new process has improved transistor channel strain. These changes allowed Intel to increase the maximum frequencies of all models by around 100 to 300 megahertz which gives many single-thread applications a modest performance increase. Note that beyond that not much else is known about the changes that were done to the actual transistor shape and size.

Compatibility

There are no official drivers by Intel for Windows 7 or Windows 8. Microsoft announced that only Windows 10 will have support for Kaby Lake. Linux added initial support for Kaby Lake starting with Linux Kernel 4.5.

Compiler support

Architecture

See also: Skylake § Key changes from Broadwell

Kaby Lake silicon wafer with 7th generation core processor dice.

While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake.

Key changes from Skylake

• Same IPC as Skylake (i.e. performance/MHz is unchanged)
• Enhanced "14nm+" process results in ~15% higher frequency (100 to 300 MHz increase across the board)
• 10x performance/Watt over Nehalem (Up from 8x)
• Socket 1151 now uses Union Point (200-series chipset) (See § Sockets)
• SkyLake's Speed Shift implementation is significantly improved, cutting responsiveness by as much as 66% (down to just ~10-15ms to peak frequency).
• Support for Optane Technology

• Interfaces
  • Embedded DisplayPort (eDP) now supports eDP Standard 1.4 (From 1.3 in Skylake)

• Gen 9.5 GPUs
  • New native hardware support for 4K HEVC/VP9 (See § Graphics)
  • HD Graphics 510 → HD Graphics 610 (12 Execution Units, no change)
  • HD Graphics 515 → HD Graphics 615 (24 Execution Units, no change)
  • HD Graphics 520 → HD Graphics 620 (24 Execution Units, no change)
  • HD Graphics 530 → HD Graphics 630 (24 Execution Units, no change)
  • HD Graphics P530 → HD Graphics P630 (24 Execution Units, no change)
  • Iris Graphics 540 → Iris Plus Graphics 640 (48 Execution Units, no change)
  • Iris Graphics 550 → Iris Plus Graphics 650 (48 Execution Units, no change)

• Families
  • Core i3 processors dropped support for ECC memory
  • Pentium desktop processors now have Hyper-Threading support (note that Mobile Pentium already had that feature.)

Block Diagram

Entire SoC Overview

Individual Core

Gen9.5

See Gen9.5#Gen9.5.

Memory Hierarchy

The overall memory structure is identical to Skylake.

• Cache
  • L1I Cache:
    • 32 KiB 8-way set associative
      • 64 B line size
      • shared by the two threads, per core
  • L1D Cache:
    • 32 KiB 8-way set associative
    • 64 B line size
    • shared by the two threads, per core
    • 4 cycles for fastest load-to-use
    • 64 Bytes/cycle load bandwidth
    • 32 Bytes/cycle store bandwidth
    • Write-back policy
  • L2 Cache:
    • unified, 256 KiB 4-way set associative
    • 12 cycles for fastest load-to-use
    • 64B/cycle bandwidth to L1$
    • Write-back policy
  • L3 Cache:
    • Up to 2 MiB Per core, shared across all cores.
    • Up to 16-way set associative
    • Write-back policy
    • Per each core:
      • Read: 32 B/cycle (@ ring clock)
      • Write: 32 B/cycle (@ ring clock)
  • Side Cache:
    • 64 MiB eDRAM
    • Per package
    • Only on the Iris Plus GPUs
    • Read: 32B/cycle (@ eDRAM clock)
    • Write: 32B/cycle (@ EDRAM clock)
  • System DRAM:
    • 2 Channels
    • 8B/cycle/channel (@ memory clock)

Kaby Lake TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB.

• TLBs:
  • ITLB
    • 4 KiB page translations:
      • 128 entries; 8-way set associative
      • dynamic partition; divided between the two threads
    • 2 MiB / 4 MiB page translations:
      • 8 entries; fully associative
      • Duplicated for each thread
  • DTLB
    • 4 KiB page translations:
      • 64 entries; 4-way set associative
      • fixed partition; divided between the two threads
    • 2 MiB / 4 MiB page translations:
      • 32 entries; 4-way set associative
      • fixed partition
    • 1G page translations:
      • 4 entries; 4-way set associative
      • fixed partition
  • STLB
    • 4 KiB + 2 MiB page translations:
      • 1536 entries; 12-way set associative
      • fixed partition
    • 1 GiB page translations:
      • 16 entries; 4-way set associative
      • fixed partition

Pipeline

Main article: Skylake §Pipeline

Kaby Lake's pipeline is identical to Skylake's.

Execution engine

Kaby Lake execution engine should be very similar to Skylake. No big changes are known to have taken place.

Execution Units

Graphics

Main article: Gen9.5

Support for three displays via HDMI 1.4^{[graphics 1]}, DisplayPort (DP) 1.2, an Embedded DisplayPort (eDP) 1.4 interfaces. Kaby Lake's biggest enhancement is the addition of native fixed function HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as fixed function HEVC/VP9 encoding for 4K (8-bit).

1. ↑ Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an LSPCON (Level Shifter/Protocol Converter) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.

Hardware Accelerated Video

Sockets/Platform

Kaby Lake Y and U are single-chip solutions. Y chips utilize a 2-die multi-chip package (MCP) whereas the Kaby Lake U's are either 2 or 3-die MCP configuration. The 3 dice chip configuration are for the Iris IGPs which incorporate an on-package cache (OPC) in addition to the hub. Communication from the CPU to the hub on those chips are done via a lightweight On-Package Interconnect (OPI) interface. Kaby Lake S and H are a two-chip solution linked together via Intel's standard DMI 3.0 bus interface which utilizes 4 of the CPU's 20 PCIe 3.0 lanes (having a transfer rate of 8 GT/s per lane). Only Kaby Lake S (used on mainstream desktop processors) are not soldered onto the motherboard and can be interchanged/replaced.

	Core	Socket	Permanent	Platform	Chipset	Bus
	Kaby Lake Y	BGA-1515	Yes	1-chip	N/A	OPI
	Kaby Lake U	BGA-1356	Yes	1-chip
	Kaby Lake H	BGA-1440	Yes	2-chip	Sunrise Point[c 1] Union Point	DMI 3.0
	Kaby Lake S	LGA-1151	No	2-chip
	Kaby Lake X	LGA-2066	No	2-chip	Lewisburg
	Kaby Lake W

1. ↑ Requires a firmware update in order to work with Kaby Lake chips

Die

One of the most noticeable changes on die is the amount of die space allocated to the GPU.

Dual-Core

Dual Core Kaby Lake Processor:

Quad-Core

Quad Core Kaby Lake Processor:

All Kaby Lake Chips