Semiconductor & Computer Engineering
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Difference between revisions of "chip multiprocessor"
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* {{\\|2|2 (dual-core)}} | * {{\\|2|2 (dual-core)}} | ||
| − | * {{\\|3|3 (tri- | + | * {{\\|3|3 (tri-core)}} |
| − | * | + | * [[quad-core|4 (quad-core)]] • [[4-core]] |
| − | * | + | * [[penta-core|5 (penta-core)]] |
| − | * | + | * [[hexa-core|6 (hexa-core)]] |
| − | * | + | * [[hepta-core|7 (hepta-core)]] |
| − | * | + | * [[octa-core|8 (octa-core)]] • [[8-core]] |
| − | * | + | * [[nona-core|9 (nona-core)]] |
| − | * | + | * [[deca-core|10 (deca-core)]] |
* {{\\|11|11 (undeca-core)}} | * {{\\|11|11 (undeca-core)}} | ||
| − | * | + | * [[dodeca-core|12 (dodeca-core)]] |
* {{\\|13|13 (trideca-core)}} | * {{\\|13|13 (trideca-core)}} | ||
| − | * | + | * [[tetradeca-core|14 (tetradeca-core)]] |
* {{\\|15|15 (pentadeca-core)}} | * {{\\|15|15 (pentadeca-core)}} | ||
| − | * | + | * [[hexadeca-core|16 (hexadeca-core)]] • [[16-core]] |
* {{\\|17|17 (heptadeca-core)}} | * {{\\|17|17 (heptadeca-core)}} | ||
| − | * | + | * [[octadeca-core|18 (octadeca-core)]] |
* {{\\|19|19 (nonadeca-core)}} | * {{\\|19|19 (nonadeca-core)}} | ||
| − | * | + | * [[icosa-core|20 (icosa-core)]] |
* {{\\|21|21 (henicosa-core)}} | * {{\\|21|21 (henicosa-core)}} | ||
| − | * | + | * [[docosa-core|22 (docosa-core)]] |
* {{\\|23|23 (tricosa-core)}} | * {{\\|23|23 (tricosa-core)}} | ||
| − | * | + | * [[tetracosa-core|24 (tetracosa-core)]] |
* {{\\|25|25 (pentacosa-core)}} | * {{\\|25|25 (pentacosa-core)}} | ||
| − | * | + | * [[hexacosa-core|26 (hexacosa-core)]] |
* {{\\|27|27 (heptacosa-core)}} | * {{\\|27|27 (heptacosa-core)}} | ||
| − | * | + | * [[octacosa-core|28 (octacosa-core)]] <!-- [[28 cores]] --> |
* {{\\|29|29 (nonacosa-core)}} | * {{\\|29|29 (nonacosa-core)}} | ||
| − | * | + | * [[triaconta-core|30 (triaconta-core)]] <!-- [[30 cores]] --> |
| − | * | + | * [[32-core|32 (dotriaconta-core)]] |
| − | * | + | * [[40-core|40 (tetraconta-core)]] |
| − | * | + | * [[46-core|46 (hexatetraconta-core)]] |
| − | * | + | * [[48-core|48 (octatetraconta-core)]] |
| − | * | + | * [[56-core|56 (hexapentaconta-core)]] |
| − | * | + | * [[64-core|64 (tetrahexaconta-core)]] |
| − | * | + | * [[68-core|68 (octahexaconta-core)]] |
| + | * [[72-core|72 (doheptaconta-core)]] <!-- [[72 cores]] --> | ||
| + | * [[96-core|96 (hexanonaconta-core)]] | ||
| + | * [[100-core|100 (hecta-core)]] • [[hecta-core]] | ||
* {{\\|128|128 (octacosahecta-core)}} | * {{\\|128|128 (octacosahecta-core)}} | ||
* {{\\|256|256 (hexapentacontadicta-core)}} | * {{\\|256|256 (hexapentacontadicta-core)}} | ||
| Line 74: | Line 77: | ||
* [[Cavium]] {{cavium|ThunderX2 CN9975}} <small>(2018)</small> | * [[Cavium]] {{cavium|ThunderX2 CN9975}} <small>(2018)</small> | ||
</td></tr> | </td></tr> | ||
| − | <tr><th>'''[[30 cores]]'''</th><td> | + | <tr><th>'''[[triaconta-core|30 cores]]'''</th><td> |
* [[Cavium]] {{cavium|ThunderX2 CN9978}} <small>(2018)</small> | * [[Cavium]] {{cavium|ThunderX2 CN9978}} <small>(2018)</small> | ||
</td></tr> | </td></tr> | ||
Latest revision as of 13:36, 13 December 2024
| Multi-Core CPUs | |
| Many-Core | |
| Multi-Core | |
A chip multiprocessor (CMP) or multi-core architecture is a logic design architecture whereby multiple processing units (e.g., CPU cores) are integrated onto a single monolithic integrated circuit or onto multiple dies in a single package.
Contents
History[edit]
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This section is empty; you can help add the missing info by editing this page. |
Overview[edit]
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This section is empty; you can help add the missing info by editing this page. |
Heterogeneous multi-core architectures[edit]
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This section is empty; you can help add the missing info by editing this page. |
Single and Multi-ISA designs[edit]
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This section is empty; you can help add the missing info by editing this page. |
Manycore[edit]
- Main article: Manycore Microprocessor
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This section is empty; you can help add the missing info by editing this page. |
Multi-core chips[edit]
- 2 (dual-core)
- 3 (tri-core)
- 4 (quad-core) • 4-core
- 5 (penta-core)
- 6 (hexa-core)
- 7 (hepta-core)
- 8 (octa-core) • 8-core
- 9 (nona-core)
- 10 (deca-core)
- 11 (undeca-core)
- 12 (dodeca-core)
- 13 (trideca-core)
- 14 (tetradeca-core)
- 15 (pentadeca-core)
- 16 (hexadeca-core) • 16-core
- 17 (heptadeca-core)
- 18 (octadeca-core)
- 19 (nonadeca-core)
- 20 (icosa-core)
- 21 (henicosa-core)
- 22 (docosa-core)
- 23 (tricosa-core)
- 24 (tetracosa-core)
- 25 (pentacosa-core)
- 26 (hexacosa-core)
- 27 (heptacosa-core)
- 28 (octacosa-core)
- 29 (nonacosa-core)
- 30 (triaconta-core)
- 32 (dotriaconta-core)
- 40 (tetraconta-core)
- 46 (hexatetraconta-core)
- 48 (octatetraconta-core)
- 56 (hexapentaconta-core)
- 64 (tetrahexaconta-core)
- 68 (octahexaconta-core)
- 72 (doheptaconta-core)
- 96 (hexanonaconta-core)
- 100 (hecta-core) • hecta-core
- 128 (octacosahecta-core)
- 256 (hexapentacontadicta-core)
- 512 (dodecapentacta-core)
- 1000 (kilo-core)
- 1024 (tetracosakilia-core)
- 2048 (octatetracontadilia-core)
Recent high core-core chips[edit]
The following is a select list of recent (2019) high core-count commercial chips:
| 28 cores |
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|---|---|
| 30 cores |
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| 32 cores |
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| 40 cores |
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| 46 cores |
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| 48 cores |
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| 56 cores |
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| 64 cores | |
| 68 cores |
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| 72 cores |
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| 100 cores |
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| 128 cores |
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| 1024 cores | |
| 2048 cores |
See also[edit]
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This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |