Revision as of 23:50, 29 January 2019

Cannon Lake (CNL) (formerly Skymont) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannon Lake is expected to be fabricated using a 10 nm process and is set to be introduced in the second half of 2018. Cannon Lake is the "Process" microarchitecture as part of Intel's PAO model.

For mobile, Cannon Lake is expected to be branded as 8th Generation Intel Core i3, Core i5. and Core i7 processors.

Codenames

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Release Dates

Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year.

Process Technology

Cannon Lake is manufactured on Intel's 10 nm process (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ Self-Aligned Quad Patterning (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² SRAM bit cell.

Scaling:

	Broadwell	Cannon Lake	Δ
	14 nm	10 nm
Fin Pitch	42 nm	34 nm	0.81x
Fin Width​	8 nm	7 nm	0.88x
Fin Height​	42 nm	53 nm	1.24x
Gate Pitch	70 nm	54 nm	0.77x
Interconnect Pitch	52 nm	36 nm	0.69x
Cell Height	399 nm	272 nm	0.68x

Compiler support

Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0.

CPUID

Architecture

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Key changes from Skylake

• 10 nm process (from 14 nm)
• Mainstream chipset
  • 200 Series chipset → 300 Series chipset

• Mobile Processors
  • LPDDR4/LPDDR4X memory support (from LPDDR3)
    • Rates up to 2400 MT/s

• Gen9.5 → Gen10 graphics
• Gen10 GPUs
  • HD Graphics 6xx (GT1) → UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from Skylake)
  • HD Graphics 6xx (GT2) → UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from Skylake)

New instructions

Cannon Lake introduced a number of new instructions. See Palm Cove § New Instructions for details.

Block Diagram

Entire SoC Overview

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Individual Core

See Palm Cove § Block Diagram.

Gen11 Graphics

See Gen10 Graphics § Block Diagram.

Die

Dual-core

• 10 nm process
• 13 metal layers
• ~8.2 mm x ~8.6 mm
• ~70.52 mm² die size
• 2 CPU cores + 40 GPU EUs

All Cannon Lake Chips

References

• Some information was obtained directly from Intel.
• Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.

See also

• AMD's Zen