Revision as of 00:58, 3 January 2019 (edit) 218.39.97.100 (talk) (→‎Codenames) ← Older edit		Revision as of 08:38, 11 February 2019 (edit) (undo) 222.82.254.190 (talk) (add stepping) Newer edit →
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	=== CPUID ===		=== CPUID ===
−	{| class="wikitable tc1 tc2 tc3 tc4"	+	{| class="wikitable tc1 tc2 tc3 tc4 tc5"
−	! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model	+	! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
	|-		|-
−	| rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || 0x9 || 0xE	+	| rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || 0x9 || 0xE || 0xA
	|-		|-
−	| colspan="4" | Family 6 Model 158	+	| colspan="5" | Family 6 Model 158 Stepping 10
	|-		|-
−	| rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || 0 || 0x6 || 0x? || 0x?	+	| rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xE || 0xA
	|-		|-
−	| colspan="4" | Family 6 Model ???	+	| colspan="5" | Family 6 Model 142 Stepping 10
	|}		|}

---

Revision as of 08:38, 11 February 2019

Edit Values
Coffee Lake µarch
General Info
Arch Type	CPU
Designer	Intel
Manufacturer	Intel
Introduction	October 5, 2017
Process	14 nm
Core Configs	2, 4, 6, 8
Pipeline
Type	Superscalar, Superpipeline
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Stages	14-19
Decode	5-way
Instructions
ISA	x86-64
Extensions	MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX
Cache
L1I Cache	32 KiB/core 8-way set associative
L1D Cache	32 KiB/core 8-way set associative
L2 Cache	256 KiB/core 4-way set associative
L3 Cache	2 MiB/core Up to 16-way set associative
L4 Cache	128 MiB/package on Iris Pro GPUs only
Cores
Core Names	Coffee Lake U, Coffee Lake H, Coffee Lake S, Coffee Lake R, Coffee Lake E
Succession
Kaby Lake Ice Lake
Contemporary
Whiskey Lake Cannon Lake

Coffee Lake (CFL) is a microarchitecture designed by Intel as a successor to Kaby Lake for desktops and high-performance mobile devices. Coffee Lake was introduced in the third quarter of 2017 and is manufactured on Intel's mature 14 nm process. Coffee Lake features the first series of mainstream hexa-core processors from Intel. In 2018, Intel refreshed the Coffee Lake lineup to incorporate their first series of mainstream octa-core processors.

Codenames

Core	Abbrev	Description	Graphics	Target
Coffee Lake U	CFL-U	Ultra-low power	GT3e	Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Coffee Lake H	CFL-H	High-performance graphics	GT2	Ultimate mobile performance, mobile workstations
Coffee Lake S	CFL-S	Mainstream performance	GT2	Desktop performance to value, AiOs, and minis
Coffee Lake R	CFL-R	Mainstream performance (Refresh)	GT2	Desktop performance to value, AiOs, and minis
Coffee Lake E	CFL-E	Workstation	GT2	Workstations and entry-level servers

Brands

Intel released Coffee Lake under 3 main brand families:

Logo	Family	General Description	Differentiating Features
			Cores	HT	AVX	AVX2	TBT	ECC
	Core i3	Low-end Performance	Quad	✘	✔	✔	✘	✔
	Core i5	Mid-range Performance	Hexa	✘	✔	✔	✔	✘
	Core i7	High-end Performance	Hexa	✔	✔	✔	✔	✘

Release Dates

Early roadmaps indicated Coffee Lake was to be introduced around the second quarter of 2018. In early 2017 Intel announced that 8th generation processors will be available starting from the 3rd quarter of 2017. While the exact reason for the early release is unknown, it seems likely to attribute the move to various market forces, particularly AMD's introduction of Zen and the Ryzen family.

Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017.

In October 2018, Intel introduced a refresh of Coffee Lake, adding more cores and increasing their clock frequencies.

Technology

See also: Broadwell § Process Technology and 14 nm lithography process

Coffee Lake is manufactured on Intel's 3rd generation 14 nm process called "14nm++". The process is the second enhanced version of the first which was used for the Broadwell microarchitecture (first enhanced version was first used for Kaby Lake). The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). 14nm++ allows for +23-24% higher drive current. Intel claims their 14nm++ process provides up to 26% more performance at the same power or 52% less power at the same performance.

Note that while both "14nm" and "14nm+" used the same transistor geometry, the "14nm++" actually uses a more relaxed contacted poly pitch of 84 nm (from previously 70nm). There is no real density change despite this change likely due to various design techniques such as reduced fins where unnecessary.

	Kaby Lake	Coffee Lake	Δ
	14 nm	14 nm
Gate Pitch	70 nm	84 nm	1.20x
Interconnect Pitch	52 nm	52 nm	1.00x

Compatibility

Compiler support

Compiler	Arch-Specific	Arch-Favorable
ICC	-march=skylake	-mtune=skylake
GCC	-march=skylake	-mtune=skylake
LLVM	-march=skylake	-mtune=skylake
Visual Studio	/arch:AVX2	/tune:skylake

CPUID

Core	Extended Family	Family	Extended Model	Model	Stepping
S/H	0	0x6	0x9	0xE	0xA
	Family 6 Model 158 Stepping 10
U	0	0x6	0x8	0xE	0xA
	Family 6 Model 142 Stepping 10

Architecture

While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in binning as a result of the enhanced process, Coffee Lake also increased the number of cores by 50% (later by 100%), enabling much higher multi-threaded performance. The enhanced manufacturing process should allow Coffee Lake chips to be highly overclockable.

Key changes from Kaby Lake

• Enhanced "14nm++" process results in higher turbo frequencies
• IPC improvement from larger cache for various workloads, but actual core is unchanged

• System Architecture
  • 50% more cores (6, from 4)
  • 50% larger last level cache (up to 12 MiB, from 8 MiB)
  • Coffee Lake Refresh
    • 100% more cores 8, from 4)
    • 100% larger last level cache (up to 16 MiB, from 8 MiB)

• Core
  • LSD has been re-enabled (Previously disabled)

• Chipset
  • 200 Series chipset → 300 Series chipset
    • Integrated USB 3.1 (10 Gib/s)
      • Up to 6 ports
    • Integrated Intel wireless controller (IEEE 802.11ac)
    • Integrated SDXC 3.0 controller

• Memory
  • Faster memory for mainstream desktops (i.e., Coffee Lake S) DDR4-2666 (from DDR4-2400)

• Graphics
  • Gen 9.5 GPUs (No Change)
  • HD Graphics 6x0 → UHD Graphics 6x0 (Branding change only)
    • HD Graphics 610 → UHD Graphics 610 (No change)
    • HD Graphics 630 → UHD Graphics 630 (No change)

• Families
  • Celeron
    • G3900 → G4900
    • 2133 MT/s → 2400 MT/s
    • Features removed: MPX, OS Guard
  • Pentium Gold
    • G4500 → G5500
    • 2133 MT/s → 2400 MT/s
    • 3 MiB L3 → 4 MiB L3
    • Features removed: MPX, OS Guard
  • Core i3
    • i3-7000 → i3-8000
    • dual-core → quad-core
    • 3/4 MiB L3 → 6/8 MiB L3
    • Features removed: hyper-threading
  • Core i5
    • i5-7000 → i5-8000
    • 2666 MT/s → 2666 MT/s
    • quad-core → hexa-core
    • 6 MiB L3 → 9 MiB L3
  • Core i7
    • i7-7000 → i7-8000
    • 2400 MT/s → 2666 MT/s
    • quad-core → hexa-core
    • 8 MiB L3 → 12 MiB L3

Block Diagram

Entire SoC Overview (quad)

Entire SoC Overview (hexa)

Entire SoC Overview (octa)

Individual Core

(Core identical to Skylake (client))

Gen9.5

See Gen9.5#Gen9.5.

Memory Hierarchy

The overall memory structure is identical to Skylake.

• Cache
  • L0 µOP cache:
    • 1,536 µOPs, 8-way set associative
      • 32 sets, 6-µOP line size
      • statically divided between threads, per core, inclusive with L1I
  • L1I Cache:
    • 32 KiB, 8-way set associative
      • 64 sets, 64 B line size
      • shared by the two threads, per core
  • L1D Cache:
    • 32 KiB, 8-way set associative
    • 64 sets, 64 B line size
    • shared by the two threads, per core
    • 4 cycles for fastest load-to-use (simple pointer accesses)
      • 5 cycles for complex addresses
    • 64 B/cycle load bandwidth
    • 32 B/cycle store bandwidth
    • Write-back policy
  • L2 Cache:
    • Unified, 256 KiB, 4-way set associative
    • Non-inclusive
    • 1024 sets, 64 B line size
    • 12 cycles for fastest load-to-use
    • 64 B/cycle bandwidth to L1$
    • Write-back policy
  • L3 Cache/LLC:
    • Up to 2 MiB Per core, shared across all cores
    • Up to 16-way set associative
    • Inclusive
    • 64 B line size
    • Write-back policy
    • Per each core:
      • Read: 32 B/cycle (@ ring clock)
      • Write: 32 B/cycle (@ ring clock)
    • 42 cycles for fastest load-to-use
  • Side Cache:
    • 64 MiB & 128 MiB eDRAM
    • Per package
    • Only on the Iris Pro GPUs
    • Read: 32 B/cycle (@ eDRAM clock)
    • Write: 32 B/cycle (@ eDRAM clock)
  • System DRAM:
    • 2 Channels
    • 8 B/cycle/channel (@ memory clock)
    • 42 cycles + 51 ns latency

Coffee Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

• TLBs:
  • ITLB
    • 4 KiB page translations:
      • 128 entries; 8-way set associative
      • dynamic partitioning
    • 2 MiB / 4 MiB page translations:
      • 8 entries per thread; fully associative
      • Duplicated for each thread
  • DTLB
    • 4 KiB page translations:
      • 64 entries; 4-way set associative
      • fixed partition
    • 2 MiB / 4 MiB page translations:
      • 32 entries; 4-way set associative
      • fixed partition
    • 1G page translations:
      • 4 entries; fully associative
      • fixed partition
  • STLB
    • 4 KiB + 2 MiB page translations:
      • 1536 entries; 12-way set associative
      • fixed partition
    • 1 GiB page translations:
      • 16 entries; 4-way set associative
      • fixed partition

• Note: STLB is incorrectly reported as "6-way" by CPUID leaf 2 (EAX=02H). Coffee Lake erratum CFL084 recommends software to simply ignore that value.

Overview

The Coffee Lake system on a chip consists of a five major components: CPU cores, LLC, Ring interconnect, System Agent, and the integrated graphics. The core architecture in Coffee Lake, like in Kaby Lake, as not changed from Skylake. This is also true for the integrated graphics which is identical to the one incorporated in Kaby Lake and from a platform point of view, the I/O has not changed (supporting up to 3 displays and providing 16 PCIe Gen 3 lanes). Coffee Lake, however, has brought a relatively large change to the overall system architecture by introducing two additional physical cores into its mainstream processor die. Those two cores also come with up to 2 MiB of LLC slice per core (for up to 4 MiB of additional last level cache).

In addition to improving multi-thread performance considerably by introducing 50% or two more cores as well as up to four additional threads, the added addition of up to 4 MiB of cache should have a positive impact on most single-thread performance.

Historical Trend

Coffee Lake presents the largest change in the system architecture of Intel's mainstream microarchitecture since the introduction of Sandy Bridge in 2011. In 2006 Intel introduced the first mainstream quad-core processor, the Core 2 Extreme QX6700 which was based on the Kentsfield core. Those initial quad-cores comprised of two separate dies interconnected in a multi-chip package. A coherent communication link was lacking and the aging front-side bus was used for as the die-to-die link. This configuration did not change through Penryn up until the introduction of the Core i7 based on the Nehalem microarchitecture in 2008. Nehalem leveraged Moore's Law and Intel's 45 nm process to incorporate all four cores onto a single die along with a large number of changes, particularly enhancing the uncore (now known as the System Agent). The Core i7-980X was also the first hexa-core consumer chip, although it was part of the enthusiast market segment and used a larger die.

With the introduction of Sandy Bridge in 2011, the entire system architecture was reworked. A particular goal of Sandy Bridge was its configurability. Intel wanted to be able to use a single design across multiple market segments without having to spend extra resources on multiple physical designs. A large part of its modularity came from the ring interconnect Sandy Bridge implemented. It's worth pointing out that the ring implementation in Sandy Bridge is an enhanced version largely based on an implementation first incorporated into the Nehalem-EX server parts. The ring allowed Intel to integrate the System Agent and the integrated graphics on-die in Sandy Bridge.

Each of those components had its own ring agent (in addition to the individual core), allowing for efficient transfer of data between the GPU, the SA, and the individual cores and caches. The final result was a complete system on a chip (SoC) with four cores and a 12 EU GPU on a single die measuring consisting of 1.16 billion transistors on a 216 mm² die.

From Sandy Bridge through 22 nm Haswell and through 14 nm Skylake, the die shrunk considerably, even after large amount of enhancements (and thus transistors) were done to the microarchitecture. With the aid of Moore's Law, the quad-core die in Coffee Lake's predecessor, Kaby Lake, has reached 126 mm² - 42% smaller than the quad-core Sandy Bridge while packing over 3 times as much transistors.

Since Coffee Lake utilizes Intel's 3rd generation enhanced 14nm++ process which has reached maturity and healthy yield, Intel can afford to increase the amount of cores by 50% from 4 to 6 cores. This is also possible thanks to the existing ring interconnect that was designed specifically to be able to support this configuration. In addition to the two added cores, there are two addition LLC slices - each consisting of 2 MiB in size.

Intel's rather faithful process shrink which has resulted in over 2.4x cell-level density improvement had a significant impact on the die size of their mainstream platform which enabled the addition of two more cores and their associated cache slices without sacrificing yield due to a bigger die. In fact, the hexa-core at 149 mm² is still considerably smaller than even the quad-core Haswell-based chips. The pair of cores with their associated cache slices and the ring interconnect agent contributed an extra ~25mm².

In late 2018 Intel introduced a refresh of Coffee Lake which further bumped the core count to eight. The 8-core refresh still yielded a smaller die than Haswell's quad-core, at around 174 mm². It's worth noting that Coffee Lake is released concurrently with Cannon Lake which is a 10 nm-based microarchitecture for low-power mobile devices. Due to Intel's faithful die shrink of roughly x2.7 in density, an identical hexa-core Coffee Lake die on 10nm would result in a smaller die than any of the 14 nm quad-core dies, possibly even the dual-core dies as well.

Core

Pipeline

Main article: Skylake § Pipeline

Coffee Lake's pipeline is identical to Skylake's.

Front-end

Note that a bug associated with the Loop Stream Detector (LSD) has been fixed with Coffee Lake. See Skylake (server) § Front-end.

Scheduler Ports & Execution Units

Scheduler Ports Designation
Port 0	Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops
	FP Add, Multiply, FMA
	Integer/FP Division and Square Root
	AES Encryption
	Branch2
Port 1	Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning
	FP Add, Multiply, FMA
Port 5	Integer/Vector Arithmetic, Logic
	Vector Permute
	x87 FP Add, Composite Int, CLMUL
Port 6	Integer Arithmetic, Logic, Shift
	Branch
Port 2	Load, AGU
Port 3	Load, AGU
Port 4	Store, AGU
Port 7	AGU

Execution Units
Execution Unit	# of Units	Instructions
ALU	4	add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup*
DIV	1	divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv
Shift	2	sal, shl, rol, adc, sarx, adcx, adox, etc...
Shuffle	1	(v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw
Slow Int	1	mul, imul, bsr, rcl, shld, mulx, pdep, etc...
Bit Manipulation	2	andn, bextr, blsi, blsmsk, bzhi, etc
FP Mov	1	(v)movsd/ss, (v)movd gpr
SIMD Misc	1	STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm
Vec ALU	3	(v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd
Vec Shift	2	(v)psllv*, (v)psrlv*, vector shift count in imm8
Vec Add	2	(v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si
Vec Mul	2	(v)mul*, (v)pmul*, (v)pmadd*
This table was taken verbatim from the Intel manual. Execution unit mapping to MMX instructions are not included.

Configurability

Coffee Lake builds upon the Skylake platform, with the addition of the first hexa core die followed by the first octa-core die. Currently, the Coffee Lake family consists of four dies, aimed towards the high-performance market.

• Physical Layout Breakdown
• 

  Dual-core die, GT2 GPU, High Power

• 

  Quad-core die, GT2 GPU, High Power

• 

  Hexa-core die, GT2 GPU, High Power

Graphics

Main article: Gen9.5

Support for three displays via HDMI 1.4^{[graphics 1]}, DisplayPort (DP) 1.2, and Embedded DisplayPort (eDP) 1.4 interfaces. Coffee Lake's graphics are identical to Kaby Lake and have native fixed function HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as fixed function HEVC/VP9 encoding for 4K (8-bit).

Integrated Graphics Processor					Standards
Name	Execution Units	Tier	Series	eDRAM	Vulkan		Direct3D			OpenGL		OpenCL
					Windows	Linux	Windows	Linux	HLSL	Windows	Linux	Windows	Linux
UHD Graphics 630	23/24	GT2	S	-	1.0		12	N/A	5.1	4.5	4.5	2.1	2.0

1. ↑ Note that while there is no native HDMI 2.0 support, Intel did provide a somewhat awkward solution using an LSPCON (Level Shifter/Protocol Converter) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.

Hardware Accelerated Video

[Edit] Coffee Lake (Gen9.5) Hardware Accelerated Video Capabilities
Codec	Encode			Decode
	Profiles	Levels	Max Resolution	Profiles	Levels	Max Resolution
MPEG-2 (H.262)	Main	High	1080p (FHD)	Main	Main, High	1080p (FHD)
MPEG-4 AVC (H.264)	High, Main	5.1	2160p (4K)	Main, High, MVC, Stereo	5.1	2160p (4K)
JPEG/MJPEG	Baseline	-	16k x 16k	Baseline	Unified	16k x 16k
HEVC (H.265)	Main	5.1	2160p (4K)	Main, Main 10	5.1	2160p (4K)
VC-1	✘			Advanced, Main, Simple	3, High, Simple	3840x3840
VP8	Unified	Unified	N/A	0	Unified	1080p
VP9	0		2160p (4K)	0, 2	Unified	2160p (4K)

Power delivery

Despite using the same socket (FCLGA-1151) Coffee Lake breaks compatibility with Skylake and Kaby Lake due to various enhancements to the power delivery of the processor in order to better handle the additional cores.

In order to improve the power delivery of the chip and support the higher package-level current delivered for the additional cores, Intel needed to increase the number of pins that go to the power rails of the die. Since there is a practical limit as to how much current each pin is capable of delivering, a large number of additional pins that were previously unused/reserved have also been allocated for this purpose. The new hexa-core parts have 38 higher amperage rating.

Pin Changes
	Skylake/Kaby Lake	Coffee Lake
Socket	FCLGA-1151 v1	FCLGA-1151 v2
Contacts	1151	1151
Reserved Pins	46	25 (-21)
VSS (Ground)	377	391 (+14)
VCC (Power)	128	146 (+18)
Core Icc		138 A (Hexa; 95 W)
		133 A (Hexa; 65 W)
	100 A (Quad; 91 W)	100 A (Quad; 95 W)
	79 A (Quad; 65 W)	79 A (Quad; 65 W)
	66 A (Quad; 35 W)
	58 A (Dual; 54 W)
	45 A (Dual; 51 W)
	40 A (Dual; 35 W)
Pinout

Die

Coffee Lake desktop and mobile come in 4, 6, and 8 cores. Each variant has its own die. The major components of the die are:

• System Agent
• CPU Core
• Ring bus interconnect
• Memory Interface

System Agent

The System Agent (SA) contains the Display Engine (DE) and the I/O bus.

Integrated Graphics

The integrated graphics makes up a large portion of the die. The normal dual-core and quad-core dies come with 24 EU Gen9.5 GPU (with 12 units disabled on the low end models).

Quad-Core

• 14 nm++ process
• 11 metal layers
• 126 mm² die size
• 4 CPU cores + 24 GPU EUs

Hexa-Core

• 14 nm++ process
• 11 metal layers
• ~9.19 mm x ~16.28 mm
• ~149.6 mm² die size
• 6 CPU cores + 24 GPU EUs

Octa-Core

• 14 nm++ process
• 11 metal layers
• ~174 mm² die size
• 8 CPU cores + 24 GPU EUs

Additional Shots

Additional die and wafer shots provided by Intel:

• 

  Coffee Lake silicon wafer with 8th generation core 6-core processor dies.

• 

  Coffee Lake Refresh silicon wafer with 9th generation core 8-core processor dies.

All Coffee Lake Chips

Documents

8th Gen

• 8th generation Core family product overview
• 8th generation Core product overview
• 8th generation core product brief
• 8th generation core lineup

9th Gen

• 9th generation core product brief

References

• Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
• Intel 8th Generation Core announcement, Sept 25, 2017.