Revision as of 14:55, 19 November 2018

Cascade Lake (CSL/CLX) is Intel's successor to Skylake, a 14 nm microarchitecture for enthusiasts and servers. Cascade Lake is the "Optimization" phase as part of Intel's PAO model.

For desktop enthusiasts, Cascade Lake is branded Core i7, and Core i9 processors (under the Core X series). For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.

Codenames

Brands

Cascade Lake is sold under eight different families.

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Logo	Family	General Description	Differentiating Features
			Cores	HT	AVX	AVX2	AVX-512	TBT	ECC
	Core i7	Enthusiasts/High Performance (X)	?-?	✔	✔	✔	✔	✔	✘
	Core i9	Enthusiasts/High Performance	?-?	✔	✔	✔	✔	✔	✘
Logo	Family	General Description	Differentiating Features
			Cores	HT	TBT	AVX-512	AVX-512 Units	UPI links	Scalability
	Xeon D	Dense servers / edge computing	?-?	✔	✔	✔	1	✘
	Xeon W	Business workstations	?-?	✔	✔	✔	2	✘
	Xeon Bronze	Entry-level performance / Cost-sensitive	?-?	✘	✘	✔	1	2	Up to 2
	Xeon Silver	Mid-range performance / Efficient lower power	?-?	✔	✔	✔	1	2	Up to 2
	Xeon Gold 5000	High performance	?-?	✔	✔	✔	1	2	Up to 4
	Xeon Gold 6000	Higher performance	?-?	✔	✔	✔	2	3	Up to 4
	Xeon Platinum	Highest performance / flexibility	?-?	✔	✔	✔	2	3	Up to 8

Release Dates

Cascade Lake is expected to be released in late 2018.

Process Technology

Cascade Lake is fabricated on Intel's enhanced 14 nm process.

Architecture

As with Skylake, Cascade Lake is also based on the Purley platform and is designed as a drop-in upgrade.

Key changes from Skylake

• Core
  • Security
    • Fix for CVE-2017-5715 (Spectre, Variant 2)
    • Fix for CVE-2017-5754 (Meltdown, Variant 3)
• Package
  • Selected SKUs with Arria 10 FPGAs in a MCP
• Memory
  • Support for up to 3 TiB per socket (up from 1.5 TiB)
  • Support for DDR-T / Optane DIMMs

This list is incomplete; you can help by expanding it.

New instructions

Cascade Lake introduced a number of new instructions:

• AVX-512 VNNI - AVX-512 Vector Neural Network Instructions

Block Diagram

This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy

The memory hierarchy of Cascade Lake is identical to that of Skylake's.

• Cache
  • L0 µOP cache:
    • 1,536 µOPs/core, 8-way set associative
      • 32 sets, 6-µOP line size
      • statically divided between threads, inclusive with L1I
  • L1I Cache:
    • 32 KiB/core, 8-way set associative
      • 64 sets, 64 B line size
      • competitively shared by the threads/core
  • L1D Cache:
    • 32 KiB/core, 8-way set associative
    • 64 sets, 64 B line size
    • competitively shared by threads/core
    • 4 cycles for fastest load-to-use (simple pointer accesses)
      • 5 cycles for complex addresses
    • 128 B/cycle load bandwidth
    • 64 B/cycle store bandwidth
    • Write-back policy
  • L2 Cache:
    • 1 MiB/core, 16-way set associative
    • 64 B line size
    • Inclusive
    • 64 B/cycle bandwidth to L1$
    • Write-back policy
    • 14 cycles latency
  • L3 Cache:
    • 1.375 MiB/core, 11-way set associative, shared across all cores
      • Note that a few models have non-default cache sizes due to disabled cores
    • 2,048 sets, 64 B line size
    • Non-inclusive victim cache
    • Write-back policy
    • 50-70 cycles latency
  • Snoop Filter (SF):
    • 2,048 sets, 12-way set associative
• DRAM
  • 6 channels of DDR4, up to 2666 MT/s
    • RDIMM and LRDIMM
    • bandwidth of 21.33 GB/s
    • aggregated bandwidth of 128 GB/s

Cascade Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

• TLBs:
  • ITLB
    • 4 KiB page translations:
      • 128 entries; 8-way set associative
      • dynamic partitioning
    • 2 MiB / 4 MiB page translations:
      • 8 entries per thread; fully associative
      • Duplicated for each thread
  • DTLB
    • 4 KiB page translations:
      • 64 entries; 4-way set associative
      • fixed partition
    • 2 MiB / 4 MiB page translations:
      • 32 entries; 4-way set associative
      • fixed partition
    • 1G page translations:
      • 4 entries; fully associative
      • fixed partition
  • STLB
    • 4 KiB + 2 MiB page translations:
      • 1536 entries; 12-way set associative
      • fixed partition
    • 1 GiB page translations:
      • 16 entries; 4-way set associative
      • fixed partition

Overview

Cascade Lake is Intel's direct successor to the Skylake server microarchitecture. It is designed to be compatible with the Skylake parts (LGA-3647) and utilize the Purley platform. To that end, Cascade Lake shares the same socket and pinout as well as the same core count, cache size, and I/O capabilities.

Cascade Lake introduces initial in-hardware Spectre and Meltdown mitigation, including Variant 2, 3, and L1TF. Chips are fabricated on an enhanced 14 nm process which allows Intel to extract an additional power efficiency, allowing them to clock those processors higher. Intel noted that targeted performance improvements were applied to some of the critical paths to make this possible. Although the core architecture is largely identical to that of Skylake, Cascade Lake introduces support for AVX512VNNI which is designed to improve the performance of Artificial Intelligence workloads by improving the throughput of tight inner convolutional loop operations.

The chief modification to Cascade Lake is the overhauling over the integrated memory controller in order to introduce support for persistent memory. The IMC on Cascade Lake is capable of interfacing with both DDR4 DIMMs and Intel's Optane DC DIMMs. Memory channels can be shared between DDR4 and Optane DC modules. For example, a single channel can have one regular DDR4 DIMM while the other DIMM can be an Optane DC DIMM. All in all, Optane DC DIMMs allow for greater than 3 TiB of system memory per socket.

A superset model is shown on the right. Cascade Lake-based servers make use of Intel's mesh interconnect architecture. In this configuration, the cores, caches, and the memory controllers are organized in rows and columns - each with dedicated connections going through each of the rows and columns allowing for the shortest path between any tile, reducing latency, and improving the bandwidth. Those processors are offered from 4 cores up to 28 cores with 8 to 56 threads.

All models incorporate 6 channels of DDR4 supporting up to 12 DIMMS for a total of 1.5 TiB (with extended models support 3 TiB). For I/O all models incorporate 48x (3x16) lanes of PCIe 3.0. There is an additional x4 lanes PCIe 3.0 reserved exclusively for DMI for the the Lewisburg (LBG) chipset. For a selected number of models, specifically those with F suffix, they have an Omni-Path Host Fabric Interface (HFI) on-package (see Integrated Omni-Path).

Cascade Lake processors are designed for scalability, supporting 2-way, 4-way, and 8-way multiprocessing through Intel's Ultra Path Interconnect (UPI) interconnect links, with two to three links being offered (see § Scalability). High-end models have node controller support allowing for even higher way configuration (e.g., 32-way multiprocessing).

New Technologies

AVX-512 Vector Neural Network Instructions

Main article: AVX-512 Vector Neural Network Instructions

Cascade Lake added support for AVX-512 Vector Neural Network Instructions (AVX512 VNNI). This extension introduces new instructions for accelerating inner convolutional neural network loops. Operations on both 8-bits and 16-bit pairs are supported. The new extension reduces the memory bandwidth required to perform a scalar-pair multiply followed by the summation of horizontal pairs and accumulate. For 16-bit operations, two common operations were fused into a single instruction while for 8-bit operations, the three common operations were fused into one.

All Cascade Lake Chips