Revision as of 12:59, 2 October 2018

Ice Lake (ICL) Client Configuration is Intel's successor to Cannon Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.

Codenames

Process Technology

See also: Cannon Lake § Process Technology

Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

Compiler support

Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.

CPUID

Architecture

Not much is known about Ice Lake's architecture.

Key changes from Cannon Lake

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

• Enhanced "10nm+" (from "10nm", 2nd gen)
• Gen10 → Gen11 graphics
• Gen11 GPUs
  • UHD Graphics 710 → UHD Graphics 810 (32 Execution Units, 1.3x EUs from Cannon Lake)
  • UHD Graphics 715 → UHD Graphics 815 (64 Execution Units, 1.6x EUs from Cannon Lake)
  • UHD Graphics 720 → UHD Graphics 820 (64 Execution Units, 1.6x EUs from Cannon Lake)
  • UHD Graphics 730 → UHD Graphics 830 (64 Execution Units, 1.6x EUs from Cannon Lake)
  • UHD Graphics P730 → UHD Graphics P830 (64 Execution Units, 1.6x EUs from Cannon Lake)
• Display
  • DisplayPort 1.4a with Display Stream Compression(DSC) (from 1.2)

New instructions

Ice Lake introduced a number of new instructions:

• CLWB - Force cache line write-back without flush
• RDPID - Read Processor ID
• Additional AVX-512 extensions:
  • AVX512VPOPCNTDQ - AVX-512 Vector Population Count Doubleword and Quadword
  • AVX512VNNI - AVX-512 Vector Neural Network Instructions
  • AVX512GFNI - AVX-512 Galois Field New Instructions
  • AVX512VAES - AVX-512 Vector AES
  • AVX512VBMI2 - AVX-512 Vector Bit Manipulation, Version 2
  • AVX512BITALG - AVX-512 Bit Algorithms
  • AVX512VPCLMULQDQ - AVX-512 Vector Vector Carry-less Multiply
• SSE_GFNI - SSE-based Galois Field New Instructions
• AVX_GFNI - AVX-based Galois Field New Instructions
• Split Lock Detection - detection and cause an exception for split locks
• Fast Short REP MOV

All Ice Lake Chips

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.