From WikiChip
Difference between revisions of "intel/microarchitectures/cannon lake"
< intel‎ | microarchitectures

(→‎CPUID)
(→‎Key changes from {{\\|Kaby Lake}})
Line 151: Line 151:
 
== Architecture ==
 
== Architecture ==
 
{{empty section}}
 
{{empty section}}
−
=== Key changes from {{\\|Kaby Lake}} ===
+
=== Key changes from {{\\|Skylake}}/{{\\|Kaby Lake|KBL}}/{{\\|Coffee Lake|CFL}} ===
 
* [[10 nm process]] (from [[14 nm]])
 
* [[10 nm process]] (from [[14 nm]])
 
* Mainstream chipset
 
* Mainstream chipset

Revision as of 08:54, 16 May 2018

Edit Values
Cannon Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionMay 15, 2018
Process10 nm
Core Configs2
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way?
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512, AVX-512F, AVX-512CD, AVX-512BW, AVX-512DQ, AVX-512VL, AVX-512IFMA, AVX-512VBMI, SHA, UMIP
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
Cores
Core NamesCannon Lake Y,
Cannon Lake U
Succession
Contemporary
Coffee Lake

Cannon Lake (CNL) (formerly Skymont) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannon Lake is expected to be fabricated using a 10 nm process and is set to be introduced in the second half of 2018. Cannon Lake is the "Process" microarchitecture as part of Intel's PAO model.

For mobile, Cannon Lake is expected to be branded as 8th Generation Intel Core i3, Core i5. and Core i7 processors.

Process Technology

Cannon Lake is manufactured on Intel's 10 nm process (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ Self-Aligned Quad Patterning (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² SRAM bit cell.

Scaling:

Broadwell Cannon Lake Δ intel 10nm fin.png
14 nm 10 nm
Fin Pitch 42 nm 34 0.81x
Fin Width​ 8 nm 7 nm 0.88x
Fin Height​ 42 nm 53 nm 1.24x
Gate Pitch 70 nm 54 nm 0.77x
Interconnect Pitch 52 nm 36 nm 0.69x
Cell Height 399 nm 272 nm 0.68x

Compiler support

Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=cannonlake -mtune=cannonlake
GCC -march=cannonlake -mtune=cannonlake
LLVM -march=cannonlake -mtune=cannonlake
Visual Studio ? ?

CPUID

Core Extended
Family 		Family Extended
Model 		Model
Y, U 0 0x6 0x6 0x6
Family 6 Model 102

Codenames

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Core Abbrev Description Graphics Target
Cannon Lake Y CNL-Y Extremely low power GT2 2-in-1s detachable, tablets, and computer sticks
Cannon Lake U CNL-U Ultra-low Power GT2/GT3 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Cannon Lake H CNL-H High-performance Graphics GT2/GT3 Ultimate mobile performance, mobile workstations
Cannon Lake S CNL-S Performance-optimized lifestyle GT2/GT3 Desktop performance to value, AiOs, and minis
Cannon Lake DT CNL-DT Workstation GT2 Workstations & entry-level servers

Architecture

New text document.svg This section is empty; you can help add the missing info by editing this page.

Key changes from Skylake/KBL/CFL

  • 10 nm process (from 14 nm)
  • Mainstream chipset
    • 200 Series chipset → 300 Series chipset
      • Integrated Programmable (Open FW SDK) Quad-Core Audio DSP
      • Soundwire Digital Audio Interface
      • Integrated USB 3.1 (10 Gib/s)
        • Up to 6 ports
      • Integrated Intel wireless controller (IEEE 802.11ac)
      • Integrated SDXC 3.0 controller
      • Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support
      • C10 & S0ix Support for Modern Standby
  • Mobile Processors
    • LPDDR4/LPDDR4X memory support (from LPDDR3)
      • Rates up to 2400 MT/s

New instructions

Cannon Lake introduced a number of new instructions:

All Cannon Lake Chips

 Cannon Lake Chips
 Main processorIGPMajor Feature Diff
ModelLaunchedPriceFamilyPlatformCoreCTL3$L4$TDPFreqTurboMax MemNameFreqTurboTBTHTAVX2TXTTSXvProVT-d
 Uniprocessors
M3-8114YCore M3Cannon Lake Y241.5 GHz
1,500 MHz
1,500,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
UHD Graphics ?300 MHz
0.3 GHz
300,000 KHz
✔✔✔✘✘✘✔
i3-8121U15 May 2018Core i3Cannon Lake U244 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
✔✔✔✘✘✘✔
Count: 2

References

  • Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cannon_lake&oldid=77888"
Facts about "Cannon Lake - Microarchitectures - Intel"
RDF feed
codenameCannon Lake +
core count2 +
designerIntel +
first launchedMay 15, 2018 +
full page nameintel/microarchitectures/cannon lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCannon Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +