Revision as of 02:53, 29 June 2017

Kaby Lake is Intel's 7th Generation Core i7 MPUs.

Kaby Lake (KBL) is Intel's successor to Skylake, an enhanced 14 nm process microarchitecture for mainstream desktops, servers, and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's PAO model. The microarchitecture was developed by Intel's R&D center in Haifa, Israel. Cannonlake was originally set to replace Skylake as the next microarchitecture using a 10 nm process, however Intel later revised their roadmap to include Kaby Lake (with Cannonlake being pushed back to 2017).

For desktop and mobile, Kaby Lake is branded as 7th Generation Intel Core i3, Core i5. and Core i7 processors. For server class processors, Intel branded it as Xeon E3 v6, Xeon E5 v6, and Xeon E7 v6.

Codenames

Brands

Intel released Kaby Lake under 6 main brand families:

Logo	Family	General Description	Differentiating Features
			Cores	HT	AVX	AVX2	TBT	ECC
	Celeron	Entry-level Budget	dual	✘	✘	✘	✘	✘
	Pentium	Budget (Mobile)	dual	✔	✘	✘	✘	✘
		Budget (Desktop)		✔	✘	✘	✘	✔
	Core i3	Low-end Performance	dual	✔	✔	✔	✘	✘
		Low-end Performance (E Series)		✔	✔	✔	✘	✔
	Core i5	Mid-range Performance	dual	✔	✔	✔	✔	✘
			quad	✘	✔	✔	✔	✘
	Core i7	High-end Performance	dual	✔	✔	✔	✔	✘
			quad	✔	✔	✔	✔	✘
	Xeon E3	Workstation high-performance/dense servers	quad	✔	✔	✔	✔	✔

Release Dates

Kaby Lake is set to be released in two phases. The first phase was announced in August of 2016 and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by Kaby Lake Y and Kaby Lake U CPUs. Intel released mainstream Kaby Lake S and Kaby Lake H processors on January 3, 2017 in time for CES 2017. Additionally, Kaby Lake X are expecting to be released in late August during Gamescom 2017.

Process Technology

See also: Broadwell § Process Technology and 14 nm lithography process

Kaby Lake uses a modified and improved 14 nm process used for the Broadwell microarchitecture (And Skylake). Intel calls the modified process "14nm+". The new process has improved transistor channel strain. The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). These changes allowed Intel to increase the maximum frequencies of all models by around 100 to 300 megahertz which gives many single-thread applications a modest performance increase. Overall transistors improvement allowed for +12% drive current.

Compatibility

There are no official drivers by Intel for Windows 7 or Windows 8. Microsoft announced that only Windows 10 will have support for Kaby Lake. Linux added initial support for Kaby Lake starting with Linux Kernel 4.5.

Compiler support

CPUID

Architecture

See also: Skylake § Key changes from Broadwell

Kaby Lake silicon wafer with 7th generation core processor dies.

While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake. Note that because of the improvements done to the process and the uplift in binning, it is the mostly the ultra-low power (i.e. mobile) processors that will see the most substantial gain. Likewise, the high-end models will see very little gain. The enhanced manufacturing process allowed Kaby Lake chips to be highly overclockable with models such as the Core i7-7700K capable of comfortably reaching 5 GHz for many people with a reasonable cooling setup.

Key changes from Skylake

• Enhanced "14nm+" process results in ~15% higher frequency (100 to 300 MHz increase across the board, same price)
• Same IPC as Skylake (i.e. performance/MHz is unchanged)
• 10x performance/Watt over Nehalem (Up from 8x)
• SkyLake's Speed Shift implementation is significantly improved, cutting responsiveness by as much as 66% (down to just ~10-15ms to peak frequency).

• Mainstream chipset (See § Sockets)
  • Sunrise Point (100 series) → Union Point (200 Series)
    • Sunrise Point is still compatible (may need firmware update)
  • Added support for Optane Technology

• Interfaces
  • Embedded DisplayPort (eDP) now supports eDP Standard 1.4 (From 1.3 in Skylake)

• Gen 9.5 GPUs
  • New native hardware support for 4K HEVC/VP9 (See § Graphics)
  • HD Graphics 510 → HD Graphics 610 (12 Execution Units, no change)
  • HD Graphics 515 → HD Graphics 615 (24 Execution Units, no change)
  • HD Graphics 520 → HD Graphics 620 (24 Execution Units, no change)
  • HD Graphics 530 → HD Graphics 630 (24 Execution Units, no change)
  • HD Graphics P530 → HD Graphics P630 (24 Execution Units, no change)
  • Iris Graphics 540 → Iris Plus Graphics 640 (48 Execution Units, no change)
  • Iris Graphics 550 → Iris Plus Graphics 650 (48 Execution Units, no change)

• Families
  • Core i3 processors dropped support for ECC memory (except for Embedded models)
  • Pentium desktop processors now have Hyper-Threading support (note that Mobile Pentium already had that feature.)
  • Pentium desktop & mobile processors now have Memory Protection (MPX) and OS Guard support

Block Diagram

Entire SoC Overview (dual)

Entire SoC Overview (quad)

Individual Core

(Core identical to Skylake)

Gen9.5

See Gen9.5#Gen9.5.

Memory Hierarchy

The overall memory structure is identical to Skylake.

• Cache
  • L0 µOP cache:
    • 1,536 µOPs, 8-way set associative
      • 32 sets, 6-µOP line size
      • statically divided between threads, per core, inclusive with L1I
  • L1I Cache:
    • 32 KiB, 8-way set associative
      • 64 sets, 64 B line size
      • shared by the two threads, per core
  • L1D Cache:
    • 32 KiB, 8-way set associative
    • 64 sets, 64 B line size
    • shared by the two threads, per core
    • 4 cycles for fastest load-to-use (simple pointer accesses)
      • 5 cycles for complex addresses
    • 64 B/cycle load bandwidth
    • 32 B/cycle store bandwidth
    • Write-back policy
  • L2 Cache:
    • Unified, 256 KiB, 4-way set associative
    • Non-inclusive
    • 1024 sets, 64 B line size
    • 12 cycles for fastest load-to-use
    • 64 B/cycle bandwidth to L1$
    • Write-back policy
  • L3 Cache/LLC:
    • Up to 2 MiB Per core, shared across all cores
    • Up to 16-way set associative
    • Inclusive
    • 64 B line size
    • Write-back policy
    • Per each core:
      • Read: 32 B/cycle (@ ring clock)
      • Write: 32 B/cycle (@ ring clock)
    • 42 cycles for fastest load-to-use
  • Side Cache:
    • 64 MiB & 128 MiB eDRAM
    • Per package
    • Only on the Iris Pro GPUs
    • Read: 32 B/cycle (@ eDRAM clock)
    • Write: 32 B/cycle (@ eDRAM clock)
  • System DRAM:
    • 2 Channels
    • 8 B/cycle/channel (@ memory clock)
    • 42 cycles + 51 ns latency

Kaby Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

• TLBs:
  • ITLB
    • 4 KiB page translations:
      • 128 entries; 8-way set associative
      • dynamic partitioning
    • 2 MiB / 4 MiB page translations:
      • 8 entries per thread; fully associative
      • Duplicated for each thread
  • DTLB
    • 4 KiB page translations:
      • 64 entries; 4-way set associative
      • fixed partition
    • 2 MiB / 4 MiB page translations:
      • 32 entries; 4-way set associative
      • fixed partition
    • 1G page translations:
      • 4 entries; fully associative
      • fixed partition
  • STLB
    • 4 KiB + 2 MiB page translations:
      • 1536 entries; 12-way set associative
      • fixed partition
    • 1 GiB page translations:
      • 16 entries; 4-way set associative
      • fixed partition

Core

Pipeline

Main article: Skylake § Pipeline

Kaby Lake's pipeline is identical to Skylake's.

Scheduler Ports & Execution Units

Graphics

Main article: Gen9.5

Support for three displays via HDMI 1.4^{[graphics 1]}, DisplayPort (DP) 1.2, an Embedded DisplayPort (eDP) 1.4 interfaces. Kaby Lake's biggest enhancement is the addition of native fixed function HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as fixed function HEVC/VP9 encoding for 4K (8-bit).

1. ↑ Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an LSPCON (Level Shifter/Protocol Converter) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.

Hardware Accelerated Video

Sockets/Platform

Kaby Lake Y and U are single-chip solutions. Y chips utilize a 2-die multi-chip package (MCP) whereas the Kaby Lake U's are either 2 or 3-die MCP configuration. The 3 die chip configuration are for the Iris IGPs which incorporate an on-package cache (OPC) in addition to the hub. Communication from the CPU to the hub on those chips are done via a lightweight On-Package Interconnect (OPI) interface. Kaby Lake S and H are a two-chip solution linked together via Intel's standard DMI 3.0 bus interface which utilizes 4 of the CPU's 20 PCIe 3.0 lanes (having a transfer rate of 8 GT/s per lane). Only Kaby Lake S (used on mainstream desktop processors) are not soldered onto the motherboard and can be interchanged/replaced.

	Core	Socket	Permanent	Platform	Chipset	Bus
	Kaby Lake Y	BGA-1515	Yes	1-chip	N/A	OPI
	Kaby Lake U	BGA-1356	Yes	1-chip
	Kaby Lake H	BGA-1440	Yes	2-chip	Sunrise Point[c 1] Union Point	DMI 3.0
	Kaby Lake S	LGA-1151	No	2-chip
	Kaby Lake DT	LGA-1151	No	2-chip	Xeon Sunrise Point Xeon Union Point
	Kaby Lake X	LGA-2066	No	2-chip	Lewisburg

1. ↑ Requires a firmware update in order to work with Kaby Lake chips

Clock domains

Kaby Lake is divided into a number of clock domains, each controlling the clock frequency of their respective unit in the processor. All clock domains are some multiple of the [virtual] bus clock (BCLK).

• BCLK - Bus/Base Clock - The system bus interface frequency (once upon a time referred to the actual FSB speed, it now serves as only a base clock reference for all other clock domains). The base clock is 100 MHz.
• Core Clock - The frequency at which the core and the L1/L2 caches operate at. (Frequency depends on the model and is represented as a multiple of BCLK).
• Ring Clock - The frequency at which the ring interconnect and LLC operate at. Data from/to the individual cores are read/written into the L3 at a rate of 32B/cycle operating at Ring Clock frequency.
• IGP Clock - The frequency at which the integrated graphics (Gen9 GPU) operates at. Data from/to the GPU are read/written into the LLC at a rate of 64B/cycle operating at this frequency as well.
• eDRAM Clock - The frequency at which the embedded DRAM operates at (only available for certain models). Data is read/written from/to the LLC at a rate of 32B/cycle operating at this frequency as well.
• MemClk - Memory Clock - The frequency at which the system DRAM operates at. DRAM data is transfered at a rate of 8B/cycle operating at MemClk frequency.

Overclocking

See Skylake §Overclocking.

Die

Kaby Lake desktop and mobile come and 2 and 4 cores. Each variant has its own die. One of the most noticeable changes on die is the amount of die space allocated to the GPU. The major components of the die are:

• System Agent
• CPU Core
• Ring bus interconnect
• Memory Controller

System Agent

The System Agent (SA) contains the Image Processing Unit (IPU), the Display Engine (DE), and the I/O bus. Note that the mainstream desktop (i.e., quad-core die) does not have an IPU (The memory controller actually occupies a portion of where it would otherwise be).

Dual-Core Die

Quad-Core Die

Integrated Graphics

The integrated graphics takes up the largest portion of the die. The normal dual-core and quad-core dies come with 24 EU Gen9.5 GPU (with 12 units disabled on the low end models).

Layout Difference from Skylake

The majority of the enhancements to Kaby Lake comes from the Unslice portion of the Gen9.5 integrated GPU. The shaded region marked in green indicates new/modified physical layout changes. The rest of the die, shaded in red, is unchanged from Skylake.

Dual-Core

Die shot of the dual-core GT2 Kaby Lake processors. Those are found in mobile models, and entry-level/budget processors:

• 14 nm+ process
• 11 metal layers
• 2 CPU cores + 24 GPU EUs

Quad-Core

Die shot of the quad-core GT2 Kaby Lake processors. Those are found in almost all mainstream desktop processors.

• 14 nm+ process
• 11 metal layers
• 4 CPU cores + 24 GPU EUs

All Kaby Lake Chips