Difference between revisions of "intel/process"

Revision as of 05:24, 11 May 2017

This article details details Intel's Semiconductor Process Technology history. The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. SRAM bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used.

Timeline

1 µm vs 500 nm yield

Ramps from 1 µm to 65 nm

SRAM test chips from 130 nm to 45 nm

Year	Process	Node	MLayers	µarchs
	CHMOS I	3 µm	1		T_ox	70 nm	Gate Dielectric
					V_dd	5 V	SRAM	1120 µm²
					L_g	3.0 µm
					CPP	7 µm	MMP	11 µm
	CHMOS II	2 µm	1		T_ox	40 nm	Gate Dielectric
					V_dd	5 V	SRAM	1740 µm²
					L_g	2.0 µm
					CPP	5.6 µm	MMP	8 µm
1982	P646 (CHMOS III)	1.5 µm	1	80286, 80386	T_ox	25 nm	Gate Dielectric	Si₂N₂O
					V_dd	5 V	SRAM	951.7 µm²
					L_g	1.5 µm
					CPP	4.0 µm	MMP	6.4 µm
1987	P648	1.0 µm	2	80486	L_g	1,000 nm
					T_ox	? nm	Gate Dielectric
					V_dd	? V
1989	P650	0.8 µm	3	80486	L_g	800 nm
					T_ox	? nm	Gate Dielectric
					V_dd	? V
1993	P852	0.5 µm	4	P5	L_g	500 nm
					T_ox	8.0 nm	Gate Dielectric
					V_dd	3.3 V
1995	P854	0.35 µm	4	P6	L_g	350 nm
					T_ox	5.2 nm	Gate Dielectric
					V_dd	2.5 V
1997	P856 P856.5	0.25 µm	5	P6	L_g	200 nm
					T_ox	3.1 nm	Gate Dielectric	SiO₂
					V_dd	1.8 V
1999	P858	0.18 µm	6	NetBurst	T_ox	2.0 nm	Gate Dielectric	SiO₂
					V_dd	1.6 V	SRAM	5.59 µm²
					L_g	130 nm
					CPP	480 nm	MMP	500 nm
2001	P860	0.13 µm	6	Pentium M	T_ox	1.4 nm	Gate Dielectric	SiO₂
					V_dd	1.4 V	SRAM	2.45 µm²
					L_g	70 nm
					CPP	336 nm	MMP	345 nm
2003	P1262	90 nm	7	Pentium M	T_ox	1.2 nm	Gate Dielectric	SiO₂
					V_dd	1.2 V	SRAM	1.00 µm²
					L_g	50 nm
					CPP	260 nm	MMP	220 nm
2005	P1264	65 nm	8	Core, Modified Pentium M	T_ox		Gate Dielectric	SiO₂
					V_dd		SRAM	0.570 µm²
					L_g	35 nm
					CPP	220 nm	MMP	210 nm
2007	P1266	45 nm	9	Penryn, Nehalem	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.346 µm²
					L_g	25 nm
					CPP	160 nm	MMP	180 nm
2009	P1268	32 nm	10	Westmere, Sandy Bridge	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.148 µm²
					L_g	30 nm
					CPP	112.5 nm	MMP	112.5 nm
2011	P1270	22 nm	11	Ivy Bridge, Haswell	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.092 µm²
					L_g	26 nm
					CPP	90 nm	MMP	80 nm
2014	P1272	14 nm	11	Broadwell, Skylake, Kaby Lake, Coffee Lake	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.0499 µm²
					L_g	20 nm
					CPP	70 nm	MMP	52 nm
2017	P1274	10 nm		Cannonlake, Icelake, Tigerlake	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.0312 µm²
					L_g	18 nm ?
					CPP	54 nm	MMP	36 nm
2019	P1276	7 nm
2022	P1278	5 nm

@@ Line 1: / Line 1: @@
 {{intel title|Process Technology}}
-This article details [[Intel]]'s [[Semiconductor Process Technology]].
+This article details details '''[[Intel]]'s [[Semiconductor Process Technology]]''' history. The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. [[SRAM]] bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used.
 == Timeline ==
@@ Line 14: / Line 14: @@
    |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22= 1120 µm²
    |a3=L<sub>g</sub>  |d3=3.0 µm
-   |a4=CPP            |d4=7 µm    |a42=MMP             |d42=11 µm
+   |a4=CPP            |d4=7 µm      |a42=MMP             |d42=11 µm
 }}
 {{intel proc tech |year= |name=CHMOS II |mlayers=1 |node=2 µm
    |archs=
    |a1=T<sub>ox</sub> |d1=40 nm     |a12=Gate Dielectric |d12=
-   |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM (HD)       |d22=1740 µm²
+   |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22=1740 µm²
    |a3=L<sub>g</sub>  |d3=2.0 µm
    |a4=CPP            |d4=5.6 µm    |a42=MMP             |d42=8 µm
 }}
-{{intel proc tech |year=1982 |name=P646 (CHMOS III) |mlayers=1 |node=1.5 µm
+{{intel proc tech |year=1982 |name=P646<br>(CHMOS III) |mlayers=1 |node=1.5 µm
    |archs=80286, 80386
    |a1=T<sub>ox</sub> |d1=25 nm     |a12=Gate Dielectric |d12=Si<sub>2</sub>N<sub>2</sub>O
-   |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM (HD)       |d22=951.7 µm²
+   |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22=951.7 µm²
    |a3=L<sub>g</sub>  |d3=1.5 µm
    |a4=CPP            |d4=4.0 µm    |a42=MMP             |d42=6.4 µm
@@ Line 62: / Line 62: @@
 {{intel proc tech |year=1999 |name=P858 |mlayers=6 |node=0.18 µm
    |archs=NetBurst
-   |a1=L<sub>g</sub>  |d1=130 nm
+   |a1=T<sub>ox</sub> |d1=2.0 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
-  |a2=T<sub>ox</sub> |d2=2.0 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
+   |a2=V<sub>dd</sub> |d2=1.6 V      |a22=SRAM            |d22=5.59 µm²
-   |a3=V<sub>dd</sub> |d3=1.6 V
+  |a3=L<sub>g</sub>  |d3=130 nm
+  |a4=CPP            |d4=480 nm     |a42=MMP             |d42=500 nm
 }}
 {{intel proc tech |year=2001 |name=P860 |mlayers=6 |node=0.13 µm
    |archs=Pentium M
-   |a1=L<sub>g</sub>  |d1=70 nm
+   |a1=T<sub>ox</sub> |d1=1.4 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
-   |a2=T<sub>ox</sub> |d2=1.4 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
+   |a2=V<sub>dd</sub> |d2=1.4 V      |a22=SRAM            |d22=2.45 µm²
-   |a3=V<sub>dd</sub> |d3=1.4 V
+   |a3=L<sub>g</sub>  |d3=70 nm
-   |a4=SRAM (HD)      |d4=2.45 µm²
+   |a4=CPP            |d4=336 nm     |a42=MMP             |d42=345 nm
 }}
 {{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm
    |xtor img=intel 90nm gate.png
    |archs=Pentium M
-   |a1=L<sub>g</sub>  |d1=50 nm
+   |a1=T<sub>ox</sub> |d1=1.2 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
-   |a2=T<sub>ox</sub> |d2=1.2 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
+   |a2=V<sub>dd</sub> |d2=1.2 V      |a22=SRAM            |d22=1.00 µm²
-   |a3=V<sub>dd</sub> |d3=1.2 V
+   |a3=L<sub>g</sub>  |d3=50 nm
-   |a4=SRAM (HD)      |d4=1.00 µm²
+   |a4=CPP            |d4=260 nm     |a42=MMP             |d42=220 nm
 }}
 {{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm

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Revision as of 05:24, 11 May 2017

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