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Difference between revisions of "chip multiprocessor"

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{{title|Chip Multiprocessor}}
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{{title|Chip Multiprocessor}}{{multi-core processors info}}
 
A '''chip multiprocessor''' ('''CMP''') or '''multi-core''' [[microprocessor architecture|architecture]] is a [[logic]] design architecture whereby multiple processing units (e.g., CPU cores) are integrated onto a single monolithic integrated circuit or onto multiple [[dies]] in a single [[package]].
 
A '''chip multiprocessor''' ('''CMP''') or '''multi-core''' [[microprocessor architecture|architecture]] is a [[logic]] design architecture whereby multiple processing units (e.g., CPU cores) are integrated onto a single monolithic integrated circuit or onto multiple [[dies]] in a single [[package]].
  
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=== Heterogeneous multi-core architectures ===
 
=== Heterogeneous multi-core architectures ===
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{{empty section}}
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{{empty section}}<!-- big/small cores-->
  
 
==== Single and Multi-ISA designs ====
 
==== Single and Multi-ISA designs ====
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== Multi-core chips ==
 
== Multi-core chips ==
 
{{collist
 
{{collist
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| count = 4
+
| count = 3
 
|
 
|
 
* {{\\|2|2 (dual-core)}}
 
* {{\\|2|2 (dual-core)}}
−
* {{\\|3|3 (tri-Core)}}
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* {{\\|3|3 (tri-core)}}
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* {{\\|4|4 (quad-core)}}
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* [[quad-core|4 (quad-core)]] • [[4-core]]
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* {{\\|5|5 (penta-core)}}
+
* [[penta-core|5 (penta-core)]]
−
* {{\\|6|6 (hexa-core)}}
+
* [[hexa-core|6 (hexa-core)]]
−
* {{\\|7|7 (hepta-core)}}
+
* [[hepta-core|7 (hepta-core)]]
−
* {{\\|8|8 (octa-core)}}
+
* [[octa-core|8 (octa-core)]] • [[8-core]]
−
* {{\\|9|9 (nona-core)}}
+
* [[nona-core|9 (nona-core)]]
−
* {{\\|10|10 (deca-core)}}
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* [[deca-core|10 (deca-core)]]
 
* {{\\|11|11 (undeca-core)}}
 
* {{\\|11|11 (undeca-core)}}
−
* {{\\|12|12 (dodeca-core)}}
+
* [[dodeca-core|12 (dodeca-core)]]
 
* {{\\|13|13 (trideca-core)}}
 
* {{\\|13|13 (trideca-core)}}
−
* {{\\|14|14 (tetradeca-core)}}
+
* [[tetradeca-core|14 (tetradeca-core)]]
 
* {{\\|15|15 (pentadeca-core)}}
 
* {{\\|15|15 (pentadeca-core)}}
−
* {{\\|16|16 (hexadeca-core)}}
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* [[hexadeca-core|16 (hexadeca-core)]] • [[16-core]]
 
* {{\\|17|17 (heptadeca-core)}}
 
* {{\\|17|17 (heptadeca-core)}}
−
* {{\\|18|18 (octadeca-core)}}
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* [[octadeca-core|18 (octadeca-core)]]
 
* {{\\|19|19 (nonadeca-core)}}
 
* {{\\|19|19 (nonadeca-core)}}
−
* {{\\|20|20 (icosa-core)}}
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* [[icosa-core|20 (icosa-core)]]
 
* {{\\|21|21 (henicosa-core)}}
 
* {{\\|21|21 (henicosa-core)}}
−
* {{\\|22|22 (docosa-core)}}
+
* [[docosa-core|22 (docosa-core)]]
 
* {{\\|23|23 (tricosa-core)}}
 
* {{\\|23|23 (tricosa-core)}}
−
* {{\\|24|24 (tetracosa-core)}}
+
* [[tetracosa-core|24 (tetracosa-core)]]
 
* {{\\|25|25 (pentacosa-core)}}
 
* {{\\|25|25 (pentacosa-core)}}
−
* {{\\|26|26 (hexacosa-core)}}
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* [[hexacosa-core|26 (hexacosa-core)]]
 
* {{\\|27|27 (heptacosa-core)}}
 
* {{\\|27|27 (heptacosa-core)}}
−
* {{\\|28|28 (octacosa-core)}}
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* [[octacosa-core|28 (octacosa-core)]] <!-- [[28 cores]] -->
 
* {{\\|29|29 (nonacosa-core)}}
 
* {{\\|29|29 (nonacosa-core)}}
−
* {{\\|30|30 (triaconta-core)}}
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* [[triaconta-core|30 (triaconta-core)]] <!-- [[30 cores]] -->
−
* {{\\|32|32 (dotriaconta-core)}}
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* [[32-core|32 (dotriaconta-core)]]
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* {{\\|40|40 (tetraconta-core)}}
+
* [[40-core|40 (tetraconta-core)]]
−
* {{\\|46|46 (hexatetraconta-core)}}
+
* [[46-core|46 (hexatetraconta-core)]]
−
* {{\\|48|48 (octatetraconta-core)}}
+
* [[48-core|48 (octatetraconta-core)]]
−
* {{\\|56|56 (hexapentaconta-core)}}
+
* [[56-core|56 (hexapentaconta-core)]]
−
* {{\\|64|64 (tetrahexaconta-core)}}
+
* [[64-core|64 (tetrahexaconta-core)]]
 +
* [[68-core|68 (octahexaconta-core)]]
 +
* [[72-core|72 (doheptaconta-core)]] <!-- [[72 cores]] -->
 +
* [[96-core|96 (hexanonaconta-core)]]
 +
* [[100-core|100 (hecta-core)]] • [[hecta-core]]
 
* {{\\|128|128 (octacosahecta-core)}}
 
* {{\\|128|128 (octacosahecta-core)}}
 
* {{\\|256|256 (hexapentacontadicta-core)}}
 
* {{\\|256|256 (hexapentacontadicta-core)}}
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* [[Cavium]] {{cavium|ThunderX2 CN9975}} <small>(2018)</small>
 
* [[Cavium]] {{cavium|ThunderX2 CN9975}} <small>(2018)</small>
 
</td></tr>
 
</td></tr>
−
<tr><th>'''[[30 cores]]'''</th><td>
+
<tr><th>'''[[triaconta-core|30 cores]]'''</th><td>
 
* [[Cavium]] {{cavium|ThunderX2 CN9978}} <small>(2018)</small>
 
* [[Cavium]] {{cavium|ThunderX2 CN9978}} <small>(2018)</small>
 
</td></tr>
 
</td></tr>
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* [[Cavium]] {{cavium|ThunderX2 CN9980}} <small>(2018)</small>
 
* [[Cavium]] {{cavium|ThunderX2 CN9980}} <small>(2018)</small>
 
* [[Ampere Computing|Ampere]] {{ampere|eMAG 8180}} <small>(2018)</small>
 
* [[Ampere Computing|Ampere]] {{ampere|eMAG 8180}} <small>(2018)</small>
 +
* [[Intel]] {{intel|Xeon Platinum 9222}} <small>(2019)</small>
 
</td></tr>
 
</td></tr>
 
<tr><th>'''[[40 cores]]'''</th><td>
 
<tr><th>'''[[40 cores]]'''</th><td>
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<tr><th>'''[[48 cores]]'''</th><td>
 
<tr><th>'''[[48 cores]]'''</th><td>
 
* [[Qualcomm]] {{qualcomm|Centriq 2460}} <small>(2017)</small>
 
* [[Qualcomm]] {{qualcomm|Centriq 2460}} <small>(2017)</small>
 +
* [[Intel]] {{intel|Xeon Platinum 9242}} <small>(2019)</small>
 +
</td></tr>
 +
<tr><th>'''[[56 cores]]'''</th><td>
 +
* [[Intel]] {{intel|Xeon Platinum 9282}} <small>(2019)</small>
 
</td></tr>
 
</td></tr>
 
<tr><th>'''[[64 cores]]'''</th><td>
 
<tr><th>'''[[64 cores]]'''</th><td>
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* [[Phytium]] {{phytium|FT-2000}} <small>(2017)</small>
 
* [[Phytium]] {{phytium|FT-2000}} <small>(2017)</small>
 
* Phytium {{phytium|FT-2000+}} <small>(2019)</small>
 
* Phytium {{phytium|FT-2000+}} <small>(2019)</small>
−
</td></tr>
+
* [[AMD]] {{amd|EPYC 7742}} <small>(2019)</small></td>
 
<tr><th>'''[[68 cores]]'''</th><td>
 
<tr><th>'''[[68 cores]]'''</th><td>
 
* [[Intel]] {{intel|Xeon Phi 7250}} <small>(2016)</small>
 
* [[Intel]] {{intel|Xeon Phi 7250}} <small>(2016)</small>
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<tr><th>'''[[72 cores]]'''</th><td>
 
<tr><th>'''[[72 cores]]'''</th><td>
 
* [[Intel]] {{intel|Xeon Phi 7290}} <small>(2016)</small>
 
* [[Intel]] {{intel|Xeon Phi 7290}} <small>(2016)</small>
 +
</td></tr>
 +
<tr><th>'''[[100 cores]]'''</th><td>
 +
* [[EZchip]] [[TILE-Mx100]] <small>(2015)</small>
 
</td></tr>
 
</td></tr>
 
<tr><th>'''[[128 cores]]'''</th><td>
 
<tr><th>'''[[128 cores]]'''</th><td>
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</td></tr>
 
</td></tr>
 
<tr><th>'''[[1024 cores]]'''</th><td>
 
<tr><th>'''[[1024 cores]]'''</th><td>
−
* [[PEZY]] {{pezy|PEZY-SC2}} <small>(2014)</small>
+
* [[PEZY]] {{pezy|PEZY-SC}} <small>(2014)</small>
 
</td></tr>
 
</td></tr>
 
<tr><th>'''[[2048 cores]]'''</th><td>
 
<tr><th>'''[[2048 cores]]'''</th><td>

Latest revision as of 13:36, 13 December 2024

Multi-Core CPUs
Many-Core
Multi-Core

A chip multiprocessor (CMP) or multi-core architecture is a logic design architecture whereby multiple processing units (e.g., CPU cores) are integrated onto a single monolithic integrated circuit or onto multiple dies in a single package.

History[edit]

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Overview[edit]

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Heterogeneous multi-core architectures[edit]

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Single and Multi-ISA designs[edit]

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Manycore[edit]

Main article: Manycore Microprocessor
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Multi-core chips[edit]

Recent high core-core chips[edit]

The following is a select list of recent (2019) high core-count commercial chips:

28 cores
30 cores
32 cores
40 cores
46 cores
48 cores
56 cores
64 cores
68 cores
72 cores
100 cores
128 cores
1024 cores
2048 cores

See also[edit]


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