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Difference between revisions of "intel/microarchitectures/cannon lake"
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|l3 per=core
 
|l3 per=core
 
|l3 desc=Up to 16-way set associative
 
|l3 desc=Up to 16-way set associative
−
|core name=Cannon Lake Y
+
|core name 2=Cannon Lake Y
−
|core name 2=Cannon Lake U
 
 
|predecessor=Kaby Lake
 
|predecessor=Kaby Lake
 
|predecessor link=intel/microarchitectures/kaby lake
 
|predecessor link=intel/microarchitectures/kaby lake
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|-
 
|-
 
! Core !! Abbrev !! Description !! Graphics !! Target
 
! Core !! Abbrev !! Description !! Graphics !! Target
−
|-
 
−
| {{intel|Cannon Lake Y|l=core}} || CNL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks
 
 
|-
 
|-
 
| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 
| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
|-
 
|-
−
| rowspan="2" | {{intel|Cannon Lake Y|Y|l=core}}, {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6
+
| rowspan="2" | {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6
 
|-
 
|-
 
| colspan="4" | Family 6 Model 102
 
| colspan="4" | Family 6 Model 102
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== Architecture ==
 
== Architecture ==
−
{{empty section}}
+
=== Key changes from {{\\|Skylake (client)|Skylake}} ===
−
=== Key changes from {{\\|Skylake}} ===
 
 
* [[10 nm process]] (from [[14 nm]])
 
* [[10 nm process]] (from [[14 nm]])
 +
 +
* {{\\|Palm Cove|Palm Cove core}} (from {{\\|Skylake (client)|Skylake}})
 +
** ''See {{\\|Palm Cove}} for microarchitectural details and changes''
 +
 
* Mainstream chipset
 
* Mainstream chipset
 
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}
 
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}
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** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}})
 
** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}})
 
** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}})
 
** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}})
 +
 +
* New Integration
 +
** New Gaussian Neural Accelerator 1.0 (Unclear to what extent)
  
 
====New instructions ====
 
====New instructions ====

Latest revision as of 11:53, 5 August 2019

Edit Values
Cannon Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionMay 15, 2018
Process10 nm
Core Configs2
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way?
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512, AVX-512F, AVX-512CD, AVX-512BW, AVX-512DQ, AVX-512VL, AVX-512IFMA, AVX-512VBMI, SHA, UMIP
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
Succession
Contemporary
Coffee Lake

Cannon Lake (CNL) (formerly Skymont) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannon Lake is expected to be fabricated using a 10 nm process and is set to be introduced in the second half of 2018. Cannon Lake is the "Process" microarchitecture as part of Intel's PAO model.

For mobile, Cannon Lake is expected to be branded as 8th Generation Intel Core i3, Core i5. and Core i7 processors.

Codenames[edit]

Core Abbrev Description Graphics Target
Cannon Lake U CNL-U Ultra-low Power GT2/GT3 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

Release Dates[edit]

Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year.

Process Technology[edit]

Cannon Lake is manufactured on Intel's 10 nm process (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ Self-Aligned Quad Patterning (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² SRAM bit cell.

Scaling:

Broadwell Cannon
Lake 		Δ intel 10nm fin.png
14 nm 10 nm
Fin Pitch  42 nm  34 nm 0.81x
Fin Width​   8 nm   7 nm 0.88x
Fin Height​  42 nm  53 nm 1.24x
Gate Pitch  70 nm  54 nm 0.77x
Interconnect Pitch  52 nm  36 nm 0.69x
Cell Height 399 nm 272 nm 0.68x

Compiler support[edit]

Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=cannonlake -mtune=cannonlake
GCC -march=cannonlake -mtune=cannonlake
LLVM -march=cannonlake -mtune=cannonlake
Visual Studio ? ?

CPUID[edit]

Core Extended
Family 		Family Extended
Model 		Model
U 0 0x6 0x6 0x6
Family 6 Model 102

Architecture[edit]

Key changes from Skylake[edit]

  • Mobile Processors
    • LPDDR4/LPDDR4X memory support (from LPDDR3)
      • Rates up to 2400 MT/s
  • Gen9.5 → Gen10 graphics
  • Gen10 GPUs
    • HD Graphics 6xx (GT1) → UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from Skylake)
    • HD Graphics 6xx (GT2) → UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from Skylake)
  • New Integration
    • New Gaussian Neural Accelerator 1.0 (Unclear to what extent)

New instructions[edit]

Cannon Lake introduced a number of new instructions. See Palm Cove § New Instructions for details.

Block Diagram[edit]

Entire SoC Overview[edit]

800px

Individual Core[edit]

See Palm Cove § Block Diagram.

Gen11 Graphics[edit]

See Gen10 Graphics § Block Diagram.

Die[edit]

Dual-core[edit]

All Cannon Lake Chips[edit]

 List of Cannon Lake-based Processors
ModelPriceLaunchedCoresThreadsTDPFrequencyTurbo
i3-8121U15 May 20182415 W
15,000 mW
0.0201 hp
0.015 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
M3-8114Y241.5 GHz
1,500 MHz
1,500,000 kHz
Count: 2

References[edit]

  • Some information was obtained directly from Intel.
  • Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cannon_lake&oldid=92852"
Facts about "Cannon Lake - Microarchitectures - Intel"
RDF feed
codenameCannon Lake +
core count2 +
designerIntel +
first launchedMay 15, 2018 +
full page nameintel/microarchitectures/cannon lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCannon Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +