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Difference between revisions of "arm holdings/microarchitectures/poseidon"
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== Release Dates == | == Release Dates == | ||
− | + | Poseidon is expected to show up in products around 2021. | |
== Process Technology == | == Process Technology == | ||
− | + | Poseidon specifically designed takes advantage of the power and area advantages of the [[5nm process]]. | |
== Architecture == | == Architecture == |
Latest revision as of 03:38, 29 August 2019
Edit Values | |
Poseidon µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Introduction | 2021 |
Process | 5 nm |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Succession | |
Poseidon is the successor to Zeus, a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Contents
History[edit]
Poseidon was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
Release Dates[edit]
Poseidon is expected to show up in products around 2021.
Process Technology[edit]
Poseidon specifically designed takes advantage of the power and area advantages of the 5nm process.
Architecture[edit]
Key changes from Zeus[edit]
- 5 nm process (from 7nm)
This list is incomplete; you can help by expanding it.
Bibliography[edit]
- Drew Henry keynote, TechCon 2018 keynote.
Facts about "Poseidon - Microarchitectures - ARM"
codename | Poseidon + |
designer | ARM Holdings + |
first launched | 2021 + |
full page name | arm holdings/microarchitectures/poseidon + |
instance of | microarchitecture + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Poseidon + |
process | 5 nm (0.005 μm, 5.0e-6 mm) + |