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| succession      = Yes
 
| succession      = Yes
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| predecessor      = X-Gene 3
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| predecessor      = X-Gene 2
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| predecessor link = apm/x-gene 3
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| predecessor link = apm/x-gene 2
 
| successor        =  
 
| successor        =  
 
| successor link  =  
 
| successor link  =  
 
}}
 
}}
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'''eMAG''' is a family of {{arch|64}} high-performance [[ARM]]server microprocessors designed by [[Ampere Computing]] for the data center.
+
'''eMAG''' is a family of {{arch|64}} high-performance [[ARM]] server microprocessors designed by [[Ampere Computing]] for the data center.
  
 
== Overview ==
 
== Overview ==
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| September, [[2018]] || {{ampere|Skylark|l=arch}} || [[14 nm]] || [[16 cores|16]]-[[32 cores|32]]
 
| September, [[2018]] || {{ampere|Skylark|l=arch}} || [[14 nm]] || [[16 cores|16]]-[[32 cores|32]]
 
|-
 
|-
−
| September, [[2019]] || {{ampere|Quicksilver|l=arch}} || [[7 nm]] || ?-?
+
| September, [[2019]] || {{ampere|Quicksilver|l=arch}} || [[7 nm]] || 80
 +
|}
 +
 
 +
== Compiler Support ==
 +
{| class="wikitable"
 +
|-
 +
! Compiler !! Arch-Specific || Arch-Favorable || Arch-Target
 +
|-
 +
| [[GCC]] || <code>-march=armv8-a</code> || <code>-mtune=emag</code> || <code>-mcpu=emag</code>
 +
|-
 +
| [[LLVM]] || <code>-march=armv8-a</code> || <code>-mtune=emag</code> || <code>-mcpu=emag</code>
 
|}
 
|}
  
 
== Models ==
 
== Models ==
 
=== 1st Gen ===
 
=== 1st Gen ===
−
First generation eMAG processors are based on the {{ampere|Skylark|l=arch}} microarchitecture, a design that started out by [[AppliedMicro]]. Fabricated on [[TSMC]]'s [[16 nm process|16FF+ process]], those processors feature up to 32 cores operating at up to 3.3 GHz
+
{{see also|apm/microarchitectures/skylark|l1=Skylark µarch}}
 +
First generation eMAG processors are based on the {{ampere|Skylark|l=arch}} microarchitecture, a design that started out by [[AppliedMicro]]. Fabricated on [[TSMC]]'s [[16 nm process|16FF+ process]], those processors feature up to 32 cores operating at up to 3.3 GHz.
  
−
* '''Mem:''' 8x DDR4 channels, up to 2666 MT/s with ECC
+
* '''Mem:''' 8x DDR4 channels, up to 2666 MT/s with ECC; 1 TiB/socket
−
* '''I/O:''' 32 PCIe Gen 3 lanes
+
* '''I/O:''' 42 PCIe Gen 3 lanes
 
* '''TDP:''' Up to 125 W
 
* '''TDP:''' Up to 125 W
 +
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 +
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc4">
 +
{{comp table header|main|6:List of Skylark-based Processors}}
 +
{{comp table header|cols|Price|Launched|Cores|L3$|Turbo|TDP}}
 +
{{#ask: [[Category:microprocessor models by ampere computing]] [[microarchitecture::Skylark]]
 +
|?full page name
 +
|?model number
 +
|?release price
 +
|?first launched
 +
|?core count
 +
|?l3$ size
 +
|?turbo frequency#GHz
 +
|?tdp
 +
|format=template
 +
|template=proc table 3
 +
|userparam=8
 +
|mainlabel=-
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by ampere computing]] [[microarchitecture::Skylark]]}}
 +
</table>
 +
{{comp table end}}
 +
 +
== 2nd Gen ==
 +
{{see also|ampere computing/microarchitectures/quicksilver|l1=Quicksilver µarch}}
 +
Second generation eMAG processors are planned for 2019. Those chips will be based on Ampere's {{ampere|Quicksilver|l=arch}} microarchitecture and feature an array of new features and improvements.
  
 
== See also ==
 
== See also ==
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* Cavium {{cavium|ThunderX2}}
 
* Cavium {{cavium|ThunderX2}}
 
* Qualcomm {{qualcomm|Centriq}}
 
* Qualcomm {{qualcomm|Centriq}}
 +
 +
== Bibliography ==
 +
* David Schor. (February 5, 2018). "''[https://fuse.wikichip.org/news/776/x-gene-3-gets-a-second-chance-at-ampere-with-a-new-32-core-16nm-arm-processor/ X-Gene 3 gets a second chance at Ampere with a new 32-core 16nm ARM processor]''".
 +
* David Schor. (September 19, 2018). "''[https://fuse.wikichip.org/news/1663/ampere-ships-first-gen-arm-server-processors/ Ampere Ships First Gen ARM Server Processors]''".
 +
* Ampere Computing. (September 18, 2018). "''[https://amperecomputing.com/ampere-announces-availability-of-emag-for-hyperscale-cloud-computing-and-unveils-aggressive-multi-generation-roadmap Ampere Announces Availability of eMAG™ for Hyperscale Cloud Computing and Unveils Aggressive, Multi-Generation Roadmap]''".

Latest revision as of 11:59, 19 May 2021

eMAG
emag (front).jpg
eMAG 8180, front
Developer Ampere Computing, AppliedMicro
Manufacturer TSMC
Type Microprocessors
Introduction February 5, 2018 (announced)
September 8, 2018 (launch)
ISA ARMv8
µarch Skylark, Quicksilver
Word size 64 bit
8 octets
16 nibbles
Process 16 nm
0.016 μm
1.6e-5 mm
Technology CMOS
Succession
←
X-Gene 2

eMAG is a family of 64-bit high-performance ARM server microprocessors designed by Ampere Computing for the data center.

Overview[edit]

eMAG is a family of high-performance ARM server processors designed by Ampere Computing and introduced in 2018. Ampere's introduction of eMAG to the market concludes the design that started out by AppliedMicro. eMAG processors targets server workloads capable of taking advantage of a high core count with high throughput.

Codenames[edit]

Introduction Microarchitecture Process Cores
September, 2018 Skylark 14 nm 16-32
September, 2019 Quicksilver 7 nm 80

Compiler Support[edit]

Compiler Arch-Specific Arch-Favorable Arch-Target
GCC -march=armv8-a -mtune=emag -mcpu=emag
LLVM -march=armv8-a -mtune=emag -mcpu=emag

Models[edit]

1st Gen[edit]

See also: Skylark µarch

First generation eMAG processors are based on the Skylark microarchitecture, a design that started out by AppliedMicro. Fabricated on TSMC's 16FF+ process, those processors feature up to 32 cores operating at up to 3.3 GHz.

  • Mem: 8x DDR4 channels, up to 2666 MT/s with ECC; 1 TiB/socket
  • I/O: 42 PCIe Gen 3 lanes
  • TDP: Up to 125 W
 List of Skylark-based Processors
ModelPriceLaunchedCoresL3$TurboTDP
8180$ 850.00
€ 765.00
£ 688.50
¥ 87,830.50
8 September 20183232 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.3 GHz
3,300 MHz
3,300,000 kHz
125 W
125,000 mW
0.168 hp
0.125 kW
Count: 1

2nd Gen[edit]

See also: Quicksilver µarch

Second generation eMAG processors are planned for 2019. Those chips will be based on Ampere's Quicksilver microarchitecture and feature an array of new features and improvements.

See also[edit]

Bibliography[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=ampere_computing/emag&oldid=98905"
Facts about "eMAG - Ampere"
RDF feed
designerAmpere Computing + and AppliedMicro +
first announcedFebruary 5, 2018 +
first launchedSeptember 8, 2018 +
full page nameampere computing/emag +
instance ofmicroprocessor family +
instruction set architectureARMv8 +
main designerAmpere Computing +
manufacturerTSMC +
microarchitectureSkylark + and Quicksilver +
nameeMAG +
process16 nm (0.016 μm, 1.6e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +