From WikiChip
Difference between revisions of "intel/microarchitectures/cannon lake"
< intel‎ | microarchitectures

 
(15 intermediate revisions by 4 users not shown)
Line 68: Line 68:
 
|l3 per=core
 
|l3 per=core
 
|l3 desc=Up to 16-way set associative
 
|l3 desc=Up to 16-way set associative
−
|core name=Cannon Lake Y
+
|core name 2=Cannon Lake Y
−
|core name 2=Cannon Lake U
 
 
|predecessor=Kaby Lake
 
|predecessor=Kaby Lake
 
|predecessor link=intel/microarchitectures/kaby lake
 
|predecessor link=intel/microarchitectures/kaby lake
Line 84: Line 83:
  
 
== Codenames ==
 
== Codenames ==
−
{{future information}}
 
−
 
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
 
! Core !! Abbrev !! Description !! Graphics !! Target
 
! Core !! Abbrev !! Description !! Graphics !! Target
−
|-
 
−
| {{intel|Cannon Lake Y|l=core}} || CNL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks
 
 
|-
 
|-
 
| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 
| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
−
|-
 
−
| {{intel|Cannon Lake H|l=core}} || CNL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations
 
−
|-
 
−
| {{intel|Cannon Lake S|l=core}} || CNL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis
 
−
|-
 
−
| {{intel|Cannon Lake DT|l=core}} || CNL-DT || Workstation || GT2 || Workstations & entry-level servers
 
 
|}
 
|}
  
Line 111: Line 100:
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
−
! !! Broadwell !! Cannon Lake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]]
+
! !! Broadwell !! Cannon<br>Lake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]]
 
|-
 
|-
 
| || [[14 nm]] || [[10 nm]] ||
 
| || [[14 nm]] || [[10 nm]] ||
 
|-
 
|-
−
| Fin Pitch || 42 nm || 34 || 0.81x
+
| Fin Pitch || &nbsp;42 nm || &nbsp;34 nm || 0.81x
 
|-
 
|-
−
| Fin Width​ || 8 nm || 7 nm || 0.88x
+
| Fin Width​ || &nbsp;&nbsp;8 nm || &nbsp;&nbsp;7 nm || 0.88x
 
|-
 
|-
−
| Fin Height​ || 42 nm || 53 nm || 1.24x
+
| Fin Height​ || &nbsp;42 nm || &nbsp;53 nm || 1.24x
 
|-
 
|-
−
| Gate Pitch || 70 nm || 54 nm || 0.77x
+
| Gate Pitch || &nbsp;70 nm || &nbsp;54 nm || 0.77x
 
|-
 
|-
−
| Interconnect Pitch || 52 nm || 36 nm || 0.69x
+
| Interconnect Pitch || &nbsp;52 nm || &nbsp;36 nm || 0.69x
 
|-
 
|-
 
| Cell Height || 399 nm || 272 nm || 0.68x
 
| Cell Height || 399 nm || 272 nm || 0.68x
Line 147: Line 136:
 
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
|-
 
|-
−
| rowspan="2" | {{intel|Cannon Lake Y|Y|l=core}}, {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6
+
| rowspan="2" | {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6
 
|-
 
|-
 
| colspan="4" | Family 6 Model 102
 
| colspan="4" | Family 6 Model 102
Line 153: Line 142:
  
 
== Architecture ==
 
== Architecture ==
−
{{empty section}}
+
=== Key changes from {{\\|Skylake (client)|Skylake}} ===
−
=== Key changes from {{\\|Skylake}}/{{\\|Kaby Lake|KBL}}/{{\\|Coffee Lake|CFL}} ===
 
 
* [[10 nm process]] (from [[14 nm]])
 
* [[10 nm process]] (from [[14 nm]])
 +
 +
* {{\\|Palm Cove|Palm Cove core}} (from {{\\|Skylake (client)|Skylake}})
 +
** ''See {{\\|Palm Cove}} for microarchitectural details and changes''
 +
 
* Mainstream chipset
 
* Mainstream chipset
 
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}
 
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}
−
*** Integrated Programmable (Open FW SDK) Quad-Core Audio DSP
 
−
*** Soundwire Digital Audio Interface
 
−
*** Integrated USB 3.1 (10 Gib/s)
 
−
**** Up to 6 ports
 
−
*** Integrated Intel wireless controller ([[IEEE 802.11ac]])
 
−
*** Integrated SDXC 3.0 controller
 
−
*** Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support
 
−
*** C10 & S0ix Support for Modern Standby
 
  
 
* Mobile Processors
 
* Mobile Processors
Line 173: Line 157:
 
* {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics
 
* {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics
 
* {{intel|Gen10|l=arch}} GPUs
 
* {{intel|Gen10|l=arch}} GPUs
−
** {{intel|HD Graphics 610}} '''→''' {{intel|UHD Graphics 710}} (24 Execution Units, 2x EUs from {{\\|Kaby Lake}})
+
** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}})
−
** {{intel|HD Graphics 615}} '''→''' {{intel|UHD Graphics 715}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
+
** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}})
−
** {{intel|HD Graphics 620}} '''→''' {{intel|UHD Graphics 720}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
+
 
−
** {{intel|HD Graphics 630}} '''→''' {{intel|UHD Graphics 730}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
+
* New Integration
−
** {{intel|HD Graphics P630}} '''→''' {{intel|UHD Graphics P730}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
+
** New Gaussian Neural Accelerator 1.0 (Unclear to what extent)
−
** {{intel|Iris Plus Graphics 640}} '''→''' {{intel|Iris Plus Graphics 740}} (unknown change)
+
 
−
** {{intel|Iris Plus Graphics 650}} '''→''' {{intel|Iris Plus Graphics 750}} (unknown change)
+
====New instructions ====
 +
Cannon Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|palm cove#New instructions|Palm Cove § New Instructions|l=arch}} for details.
 +
 
 +
=== Block Diagram ===
 +
 
 +
==== Entire SoC Overview ====
 +
[[File:cannon lake soc block diagram.svg|800px]]
 +
 
 +
==== Individual Core ====
 +
See {{intel|Palm Cove#Block Diagram|Palm Cove § Block Diagram|l=arch}}.
  
−
==== New instructions ====
+
==== Gen11 Graphics ====
−
Cannon Lake introduced a number of {{x86|extensions|new instructions}}:
+
See {{intel|Gen10#Block Diagram|Gen10 Graphics § Block Diagram|l=arch}}.
  
−
* {{x86|AVX-512|<code>AVX-512</code>}}, specifically:
+
== Die ==
−
** {{x86|AVX512F|<code>AVX512F</code>}} - AVX-512 Foundation
+
=== Dual-core ===
−
** {{x86|AVX512CD|<code>AVX512CD</code>}} - AVX-512 Conflict Detection
+
* [[10 nm process]]
−
** {{x86|AVX512BW|<code>AVX512BW</code>}} - AVX-512 Byte and Word
+
* [[13 metal layers]]
−
** {{x86|AVX512DQ|<code>AVX512DQ</code>}} - AVX-512 Doubleword and Quadword
+
* ~8.2 mm x ~8.6 mm
−
** {{x86|AVX512VL|<code>AVX512VL</code>}} - AVX-512 Vector Length
+
* ~70.52 mm² die size
−
** {{x86|AVX512IFMA|<code>AVX512IFMA</code>}} - AVX-512 Integer Fused Multiply-Add
+
* 2 CPU cores + 40 GPU EUs
−
** {{x86|AVX512VBMI|<code>AVX512VBMI</code>}} - AVX-512 Vector Bit Manipulation
 
−
* {{x86|SHA|<code>SHA</code>}} - [[Hardware acceleration]] for SHA hashing operations
 
−
* {{x86|UMIP|<code>UMIP</code>}} - User-Mode Instruction Prevention extension
 
  
 
== All Cannon Lake Chips ==
 
== All Cannon Lake Chips ==
Line 201: Line 191:
 
           created and tagged accordingly.
 
           created and tagged accordingly.
  
−
           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
+
           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 
-->
 
-->
 
{{comp table start}}
 
{{comp table start}}
−
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
+
<table class="comptable sortable tc4 tc5 tc6">
−
<tr class="comptable-header"><th>&nbsp;</th><th colspan="23">Cannon Lake Chips</th></tr>
+
{{comp table header|main|7:List of Cannon Lake-based Processors}}
−
<tr class="comptable-header"><th>&nbsp;</th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr>
+
{{comp table header|cols|Price|Launched|Cores|Threads|TDP|%Frequency|%Turbo}}
−
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th>Price</th><th>Family</th><th>Platform</th><th>Core</th><th>C</th><th>T</th><th>L3$</th><th>L4$</th><th>TDP</th><th>Freq</th><th>Turbo</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
+
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]
−
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="23">[[Uniprocessors]]</th></tr>
 
−
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cannon Lake]] [[max cpu count::1]]
 
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
 +
|?release price
 
  |?first launched
 
  |?first launched
−
|?release price
 
−
|?microprocessor family
 
−
|?platform
 
−
|?core name
 
 
  |?core count
 
  |?core count
 
  |?thread count
 
  |?thread count
−
|?l3$ size
 
−
|?l4$ size
 
 
  |?tdp
 
  |?tdp
 
  |?base frequency#GHz
 
  |?base frequency#GHz
 
  |?turbo frequency (1 core)#GHz
 
  |?turbo frequency (1 core)#GHz
−
|?max memory#GiB
 
−
|?integrated gpu
 
−
|?integrated gpu base frequency
 
−
|?integrated gpu max frequency
 
−
|?has intel turbo boost technology 2_0
 
−
|?has simultaneous multithreading
 
−
|?has advanced vector extensions 2
 
−
|?has intel trusted execution technology
 
−
|?has transactional synchronization extensions
 
−
|?has intel vpro technology
 
−
|?has_intel_vt-d_technology
 
 
  |format=template
 
  |format=template
 
  |template=proc table 3
 
  |template=proc table 3
−
|searchlabel=
+
  |userparam=9
−
|sort=microprocessor family, model number
 
−
|order=asc,asc
 
−
  |userparam=25:19
 
 
  |mainlabel=-
 
  |mainlabel=-
−
|limit=100
 
 
}}
 
}}
−
{{comp table count|ask=[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Cannon Lake]]}}
+
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}
  
 
== References ==
 
== References ==
 +
* Some information was obtained directly from Intel.
 
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
 
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
  
 
== See also ==
 
== See also ==
 
* AMD's {{amd|Zen|l=arch}}
 
* AMD's {{amd|Zen|l=arch}}

Latest revision as of 11:53, 5 August 2019

Edit Values
Cannon Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionMay 15, 2018
Process10 nm
Core Configs2
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way?
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512, AVX-512F, AVX-512CD, AVX-512BW, AVX-512DQ, AVX-512VL, AVX-512IFMA, AVX-512VBMI, SHA, UMIP
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
Succession
Contemporary
Coffee Lake

Cannon Lake (CNL) (formerly Skymont) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannon Lake is expected to be fabricated using a 10 nm process and is set to be introduced in the second half of 2018. Cannon Lake is the "Process" microarchitecture as part of Intel's PAO model.

For mobile, Cannon Lake is expected to be branded as 8th Generation Intel Core i3, Core i5. and Core i7 processors.

Codenames[edit]

Core Abbrev Description Graphics Target
Cannon Lake U CNL-U Ultra-low Power GT2/GT3 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

Release Dates[edit]

Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year.

Process Technology[edit]

Cannon Lake is manufactured on Intel's 10 nm process (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ Self-Aligned Quad Patterning (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² SRAM bit cell.

Scaling:

Broadwell Cannon
Lake 		Δ intel 10nm fin.png
14 nm 10 nm
Fin Pitch  42 nm  34 nm 0.81x
Fin Width​   8 nm   7 nm 0.88x
Fin Height​  42 nm  53 nm 1.24x
Gate Pitch  70 nm  54 nm 0.77x
Interconnect Pitch  52 nm  36 nm 0.69x
Cell Height 399 nm 272 nm 0.68x

Compiler support[edit]

Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=cannonlake -mtune=cannonlake
GCC -march=cannonlake -mtune=cannonlake
LLVM -march=cannonlake -mtune=cannonlake
Visual Studio ? ?

CPUID[edit]

Core Extended
Family 		Family Extended
Model 		Model
U 0 0x6 0x6 0x6
Family 6 Model 102

Architecture[edit]

Key changes from Skylake[edit]

  • Mobile Processors
    • LPDDR4/LPDDR4X memory support (from LPDDR3)
      • Rates up to 2400 MT/s
  • Gen9.5 → Gen10 graphics
  • Gen10 GPUs
    • HD Graphics 6xx (GT1) → UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from Skylake)
    • HD Graphics 6xx (GT2) → UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from Skylake)
  • New Integration
    • New Gaussian Neural Accelerator 1.0 (Unclear to what extent)

New instructions[edit]

Cannon Lake introduced a number of new instructions. See Palm Cove § New Instructions for details.

Block Diagram[edit]

Entire SoC Overview[edit]

800px

Individual Core[edit]

See Palm Cove § Block Diagram.

Gen11 Graphics[edit]

See Gen10 Graphics § Block Diagram.

Die[edit]

Dual-core[edit]

All Cannon Lake Chips[edit]

 List of Cannon Lake-based Processors
ModelPriceLaunchedCoresThreadsTDPFrequencyTurbo
i3-8121U15 May 20182415 W
15,000 mW
0.0201 hp
0.015 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
M3-8114Y241.5 GHz
1,500 MHz
1,500,000 kHz
Count: 2

References[edit]

  • Some information was obtained directly from Intel.
  • Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cannon_lake&oldid=92852"
Facts about "Cannon Lake - Microarchitectures - Intel"
RDF feed
codenameCannon Lake +
core count2 +
designerIntel +
first launchedMay 15, 2018 +
full page nameintel/microarchitectures/cannon lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCannon Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +