Difference between revisions of "intel/process"

Latest revision as of 02:56, 4 March 2022

This article details Intel's semiconductor process technology history for research and posterity.

Overview[edit]

The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. SRAM bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used. Additionally, the metal layer count is for the client dies (example consumer mobile & desktop); server models utilize considerably more layers. Finally, from the 45 nm node, Intel has switched to utilizing a high-κ material, therefore the oxide thickness shown refers to the equivalent oxide thickness instead.

Nomenclature[edit]

Intel has been using the same naming scheme for decades. All process technologies (including packaging technologies) begin with a 'P' followed by the wafer size and the process ID. Generally, the process ID is an auto-increment value with odd values generally reserved for SoC and I/O (low power) devices while the even values have been used for Intel premier line of high-performance processors.

Timeline[edit]

1 µm vs 500 nm yield

historical roadmap

Ramps from 1 µm to 65 nm

Roadmap past 180 nm

SRAM test chips from 130 nm to 45 nm

Intel's fab roadmap from 2003. Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics.

65 nm to 32 nm SRAM scaling

90 nm to 32 nm

Intel scaling from 45 nm to 10 nm

Intel roadmap from 10 nm to 5 nm and an advance packaging roadmap.

Year	Process	Node	MLayers	µarchs	Attributes
1972	PMOS I	10 µm	1	4004	Gate Dielectric	SiO₂
1972	PMOS I	10 µm	1	4004	L_g	10.0 µm
1974	HMOS I	8 µm	1		Gate Dielectric	SiO₂
1974	HMOS I	8 µm	1		L_g	8.0 µm
1976	HMOS II/III	6 µm	1	8080	Gate Dielectric	SiO₂
1976	HMOS II/III	6 µm	1	8080	L_g	6.0 µm
1977	CHMOS I	3 µm	1	8085, 8086, 8088, 80186	T_ox	70 nm	Gate Dielectric	SiO₂
					V_dd	5 V	SRAM	1120 µm²
					L_g	3.0 µm
					CPP	7 µm	MMP	11 µm
1979	CHMOS II	2 µm	1		T_ox	40 nm	Gate Dielectric	SiO₂
					V_dd	5 V	SRAM	1740 µm²
					L_g	2.0 µm
					CPP	5.6 µm	MMP	8 µm
1982	P646 (CHMOS III)	1.5 µm	1	80286, 80386	T_ox	25 nm	Gate Dielectric	SiO₂
					V_dd	5 V	SRAM	951.7 µm²
					L_g	1.5 µm
					CPP	4.0 µm	MMP	6.4 µm
1987	P648	1.0 µm	2	80486	T_ox		Gate Dielectric	SiO₂
					V_dd	5 V	SRAM	220 µm²
					L_g	1.0 µm
					CPP		MMP
1989	P650	0.8 µm	3	80486	T_ox	15 nm	Gate Dielectric	SiO₂
					V_dd	4 V	SRAM	111 µm²
					L_g	800 nm
					CPP	1.7 µm	MMP	2 µm
1991	P652	0.6 µm	4	80486, P5	T_ox	8 nm	Gate Dielectric	SiO₂
					V_dd	3.3 V	SRAM
					L_g	600 nm
					CPP		MMP	1.4 µm
1993	P852	0.5 µm	4	P5	T_ox	8 nm	Gate Dielectric	SiO₂
					V_dd	3.3 V	SRAM	44 µm²
					L_g	500 nm
					CPP		MMP
1995	P854	0.35 µm	4	P6	T_ox	6 nm	Gate Dielectric	SiO₂
					V_dd	2.5 V	SRAM	20.5 µm²
					L_g	350 nm
					CPP	920 nm	MMP	880 nm
1997	P856	0.25 µm	5	P6	T_ox	4.08 nm	Gate Dielectric	SiO₂
					V_dd	1.8 V	SRAM	10.26 µm²
					L_g	200 nm
					CPP	500 nm	MMP	640 nm
1998	P856.5	0.25 µm	5	P6	T_ox	4.08 nm	Gate Dielectric	SiO₂
					V_dd	1.8 V	SRAM	9.26 µm²
					L_g	200 nm
					CPP	475 nm	MMP	608 nm
1999	P858	0.18 µm	6	NetBurst	T_ox	2.0 nm	Gate Dielectric	SiO₂
					V_dd	1.6 V	SRAM	5.59 µm²
					L_g	130 nm
					CPP	480 nm	MMP	500 nm
2001	P860	0.13 µm	6	Pentium M	T_ox	1.4 nm	Gate Dielectric	SiO₂
					V_dd	1.4 V	SRAM	2.45 µm²
					L_g	70 nm
					CPP	336 nm	MMP	345 nm
2003	P1262 (CPU) P1263 (SoC, I/O)	90 nm	7	Pentium M	T_ox	1.2 nm	Gate Dielectric	SiO₂
					V_dd	1.2 V	SRAM	1.00 µm²
					L_g	50 nm
					CPP	260 nm	MMP	220 nm
2005	P1264 (CPU) P1265 (SoC, I/O)	65 nm	8	Core, Modified Pentium M	T_ox	1.2 nm	Gate Dielectric	SiO₂
					V_dd		SRAM	0.570 µm²
					L_g	35 nm
					CPP	220 nm	MMP	210 nm
2007	P1266 (CPU) P1267 (SoC, I/O)	45 nm	9	Penryn, Nehalem	T_oxe	1 nm	Gate Dielectric	High-κ
					V_dd		SRAM	0.346 µm²
					L_g	25 nm
					CPP	160 nm	MMP	180 nm
2009	P1268 (CPU) P1269 (SoC, I/O)	32 nm	10	Westmere, Sandy Bridge	T_oxe	1 nm	Gate Dielectric	High-κ
					V_dd	0.75 V	SRAM	0.148 µm²
					L_g	30 nm
					CPP	112.5 nm	MMP	112.5 nm
2011	P1270 (CPU) P1271 (SoC, I/O)	22 nm	11	Ivy Bridge, Haswell	T_oxe	0.9 nm	Gate Dielectric	High-κ
					V_dd	0.75 V	SRAM	0.092 µm²
					L_g	26 nm
					CPP	90 nm	MMP	80 nm
					P_fin	60 nm
					W_fin	8 nm	H_fin	34 nm
2014	P1272 (CPU) P1273 (SoC, I/O)	14 nm	12	Broadwell, Skylake, Kaby Lake, Coffee Lake, Cascade Lake, Comet Lake	T_oxe		Gate Dielectric	High-κ
					V_dd	0.70 V	SRAM	0.0499 µm²
					L_g	20 nm
					CPP	70 nm	MMP	52 nm
					P_fin	42 nm
					W_fin	8 nm	H_fin	42-46 nm
2019	P1274 (CPU) P1275 (SoC, I/O)	10 nm	12-13	Cannon Lake, Ice Lake, Tiger Lake, Alder Lake, Sapphire Rapids, Raptor Lake	T_oxe		Gate Dielectric	High-κ
					V_dd	0.70 V	SRAM	0.0312 µm²
					L_g	18 nm
					CPP	54 nm	MMP	36 nm
					P_fin	34 nm
					W_fin	7 nm	H_fin	44-55 nm
2021	P1276 (CPU) P1277 (SoC, I/O)	7 nm			T_oxe		Gate Dielectric
					V_dd		SRAM
					L_g
					CPP		MMP
					P_fin
					W_fin		H_fin
2024	P1278 (CPU) P1279 (SoC, I/O)	5 nm			T_oxe		Gate Dielectric
					V_dd		SRAM
					L_g
					CPP		MMP
					P_fin
					W_fin		H_fin
2027	P1280 (CPU) P1281 (SoC, I/O)	3 nm			T_oxe		Gate Dielectric
					V_dd		SRAM
					L_g
					CPP		MMP
					P_fin
					W_fin		H_fin

SRAM Scaling[edit]

For Intel, from 2 µm to 10 nm, SRAM 6T bit cells have had an average shrink of 0.496x in an attempt to maintain Moore's Law double density observation/requirement. Note that SRAM shrunk more significantly prior to the 65 nm process node. It should also be noted that logic typically scales better than the typical 6T SRAM cells, so raw logic density scaled more over time. Nonetheless, the size of the SRAM can be as much as three to four times the density of the typical logic cell.

Other processes[edit]

Semiconductor Process history by company:

DEC
Intel

@@ Line 1: / Line 1: @@
-{{intel title|Process Technology}}
+{{intel title|Process Technology History}}
-This article details details '''[[Intel]]'s [[Semiconductor Process Technology]]''' history for research and posterity.
+This article details '''[[Intel]]'s [[semiconductor process technology]]''' history for research and posterity.
+== Overview ==
 The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. [[SRAM]] bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used. Additionally, the metal layer count is for the client dies (example consumer mobile & desktop); server models utilize considerably more layers. Finally, from the [[45 nm]] node, Intel has switched to utilizing a [[high-κ]] material, therefore the oxide thickness shown refers to the [[equivalent oxide thickness]] instead.
+== Nomenclature ==
+Intel has been using the same naming scheme for decades. All process technologies (including packaging technologies) begin with a 'P' followed by the [[wafer size]] and the process ID. Generally, the process ID is an auto-increment value with odd values generally reserved for SoC and I/O (low power) devices while the even values have been used for Intel premier line of high-performance processors.
+[[File:intel process naming scheme.svg|400px]]
 == Timeline ==
@@ Line 14: / Line 21: @@
 [[File:intel 90nm 32nm yield.png|250px|thumb|[[90 nm]] to [[32 nm]]]]
 [[File:intel scaling from 45nm to 10nm.png|250px|thumb|Intel scaling from [[45 nm]] to [[10 nm]]]]
+[[File:intel scaling roadmap to 5nm.png|250px|thumb|Intel roadmap from [[10 nm]] to [[5 nm]] and an advance packaging roadmap.]]
 <div style="overflow-x: scroll; white-space: nowrap; min-width: 300px" class="scrollable">
 <table class="wikitable" style="text-align: center;">
 <tr><th>Year</th><th>Process</th><th>[[technology node|Node]]</th><th>MLayers</th><th>µarchs</th><th>Gate</th><th>Interconnects</th><th colspan="4">Attributes</th></tr>
+{{intel proc tech |year=1972 |name=PMOS I |mlayers=1 |node=10 µm
+  |archs=4004
+  |a1=Gate Dielectric |d1=SiO<sub>2</sub>
+  |a2=L<sub>g</sub>  |d2=10.0 µm
+}}
+{{intel proc tech |year=1974 |name=HMOS I |mlayers=1 |node=8 µm
+  |archs=
+  |a1=Gate Dielectric |d1=SiO<sub>2</sub>
+  |a2=L<sub>g</sub>  |d2=8.0 µm
+}}
+{{intel proc tech |year=1976 |name=HMOS II/III |mlayers=1 |node=6 µm
+  |archs=8080
+  |a1=Gate Dielectric |d1=SiO<sub>2</sub>
+  |a2=L<sub>g</sub>  |d2=6.0 µm
+}}
 {{intel proc tech |year=1977 |name=CHMOS I |mlayers=1 |node=3 µm
    |archs=8085, 8086, 8088, 80186
@@ Line 49: / Line 72: @@
    |a1=T<sub>ox</sub> |d1=15 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
    |a2=V<sub>dd</sub> |d2=4 V       |a22=SRAM            |d22=111 µm²
-   |a3=L<sub>g</sub>  |d3=800 µm
+   |a3=L<sub>g</sub>  |d3=800 nm
    |a4=CPP            |d4=1.7 µm    |a42=MMP             |d42=2 µm
 }}
@@ Line 56: / Line 79: @@
    |a1=T<sub>ox</sub> |d1=8 nm      |a12=Gate Dielectric |d12=SiO<sub>2</sub>
    |a2=V<sub>dd</sub> |d2=3.3 V     |a22=SRAM            |d22=
-   |a3=L<sub>g</sub>  |d3=600 µm
+   |a3=L<sub>g</sub>  |d3=600 nm
    |a4=CPP            |d4=          |a42=MMP             |d42=1.4 µm
 }}
@@ Line 106: / Line 129: @@
    |a4=CPP            |d4=336 nm     |a42=MMP             |d42=345 nm
 }}
-{{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm
+{{intel proc tech |year=2003 |name=P1262 (CPU)<br>P1263 (SoC, I/O) |mlayers=7 |node=90 nm
    |xtor img=intel 90nm gate.png
    |interconnects img=intel_90nm_gate_interconnect.png
@@ Line 115: / Line 138: @@
    |a4=CPP            |d4=260 nm     |a42=MMP             |d42=220 nm
 }}
-{{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm
+{{intel proc tech |year=2005 |name=P1264 (CPU)<br>P1265 (SoC, I/O) |mlayers=8 |node=65 nm
    |xtor img=intel 65nm gate.png
    |interconnects img=intel_65nm_gate_interconnect.png
@@ Line 124: / Line 147: @@
    |a4=CPP            |d4=220 nm     |a42=MMP             |d42=210 nm
 }}
-{{intel proc tech |year=2007 |name=P1266 |mlayers=9 |node=45 nm
+{{intel proc tech |year=2007 |name=P1266 (CPU)<br>P1267 (SoC, I/O) |mlayers=9 |node=45 nm
    |xtor img=intel 45nm gate.png
    |interconnects img=intel_45nm_gate_interconnects.png
@@ Line 133: / Line 156: @@
    |a4=CPP            |d4=160 nm     |a42=MMP             |d42=180 nm
 }}
-{{intel proc tech |year=2009 |name=P1268 |mlayers=10 |node=32 nm
+{{intel proc tech |year=2009 |name=P1268 (CPU)<br>P1269 (SoC, I/O) |mlayers=10 |node=32 nm
    |xtor img=intel 32nm gate.png
    |interconnects img=intel 32nm gate interconnect.png
    |archs=Westmere, Sandy Bridge
-   |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
+   |a1=T<sub>oxe</sub>|d1=1 nm       |a12=Gate Dielectric |d12=High-κ
    |a2=V<sub>dd</sub> |d2=0.75 V     |a22=SRAM            |d22=0.148 µm²
    |a3=L<sub>g</sub>  |d3=30 nm
    |a4=CPP            |d4=112.5 nm   |a42=MMP             |d42=112.5 nm
 }}
-{{intel proc tech |year=2011 |name=P1270 |mlayers=11 |node=22 nm
+{{intel proc tech |year=2011 |name=P1270 (CPU)<br>P1271 (SoC, I/O) |mlayers=11 |node=22 nm
    |xtor img=intel 22nm gate.png
    |interconnects img=intel 22nm gate interconnect.png
    |archs=Ivy Bridge, Haswell
-   |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
+   |a1=T<sub>oxe</sub>|d1=0.9 nm     |a12=Gate Dielectric |d12=High-κ
    |a2=V<sub>dd</sub> |d2=0.75 V     |a22=SRAM            |d22=0.092 µm²
    |a3=L<sub>g</sub>  |d3=26 nm
@@ Line 153: / Line 176: @@
    |a6=W<sub>''fin''</sub>      |d6=8 nm       |a62=H<sub>''fin''</sub> |d62=34 nm
 }}
-{{intel proc tech |year=2014 |name=P1272 |mlayers=11 |node=14 nm
+{{intel proc tech |year=2014 |name=P1272 (CPU)<br>P1273 (SoC, I/O) |mlayers=12 |node=14 nm
    |xtor img=intel 14nm gate top.png
    |interconnects img=intel 14nm gate interconnect.png
-   |archs=Broadwell, Skylake, Kaby Lake, Coffee Lake
+   |archs=Broadwell, Skylake, Kaby Lake, Coffee Lake, Cascade Lake, Comet Lake, Cooper Lake, Rocket Lake
    |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
    |a2=V<sub>dd</sub> |d2=0.70 V     |a22=SRAM            |d22=0.0499 µm²
@@ Line 162: / Line 185: @@
    |a4=CPP            |d4=70 nm      |a42=MMP             |d42=52 nm
    |a5=P<sub>''fin''</sub>      |d5=42 nm
-   |a6=W<sub>''fin''</sub>      |d6=8 nm       |a62=H<sub>''fin''</sub> |d62=42 nm
+   |a6=W<sub>''fin''</sub>      |d6=8 nm       |a62=H<sub>''fin''</sub> |d62=42-46 nm
 }}
-{{intel proc tech |year=2017 |name=P1274 |mlayers= |node=10 nm
+{{intel proc tech |year=2019 |name=P1274 (CPU)<br>P1275 (SoC, I/O) |mlayers=12-13 |node=10 nm
-   |archs=Cannonlake, Icelake, Tigerlake
+   |archs=Cannon Lake, Ice Lake, Tiger Lake, Alder Lake, Sapphire Rapids, Raptor Lake, Emerald Rapids
    |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
    |a2=V<sub>dd</sub> |d2=0.70 V     |a22=SRAM            |d22=0.0312 µm²
-   |a3=L<sub>g</sub>  |d3=18 nm ?
+   |a3=L<sub>g</sub>  |d3=18 nm
    |a4=CPP            |d4=54 nm      |a42=MMP             |d42=36 nm
    |a5=P<sub>''fin''</sub>      |d5=34 nm
-   |a6=W<sub>''fin''</sub>      |d6=5 nm       |a62=H<sub>''fin''</sub> |d62=53 nm
+   |a6=W<sub>''fin''</sub>      |d6=7 nm       |a62=H<sub>''fin''</sub> |d62=44-55 nm
 }}
-{{intel proc tech |year=2019 |name=P1276 |mlayers= |node=7 nm
+{{intel proc tech |year=2021 |name=P1276 (CPU)<br>P1277 (SoC, I/O) |mlayers= |node=7 nm
+  |archs=Meteor Lake, Granite Rapids
+|archs=
+  |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=
+  |a2=V<sub>dd</sub> |d2=     |a22=SRAM            |d22=
+  |a3=L<sub>g</sub>  |d3=
+  |a4=CPP            |d4=     |a42=MMP          |d42=
+  |a5=P<sub>''fin''</sub>      |d5=
+  |a6=W<sub>''fin''</sub>      |d6=       |a62=H<sub>''fin''</sub> |d62=
 }}
-{{intel proc tech |year=2022 |name=P1278 |mlayers= |node=5 nm
+{{intel proc tech |year=2024 |name=P1278 (CPU)<br>P1279 (SoC, I/O) |mlayers= |node=5 nm
+|archs=
+  |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=
+  |a2=V<sub>dd</sub> |d2=     |a22=SRAM            |d22=
+  |a3=L<sub>g</sub>  |d3=
+  |a4=CPP            |d4=     |a42=MMP          |d42=
+  |a5=P<sub>''fin''</sub>      |d5=
+  |a6=W<sub>''fin''</sub>      |d6=       |a62=H<sub>''fin''</sub> |d62=
+}}
+{{intel proc tech |year=2027 |name=P1280 (CPU)<br>P1281 (SoC, I/O) |mlayers= |node=3 nm
+|archs=
+  |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=
+  |a2=V<sub>dd</sub> |d2=     |a22=SRAM            |d22=
+  |a3=L<sub>g</sub>  |d3=
+  |a4=CPP            |d4=     |a42=MMP          |d42=
+  |a5=P<sub>''fin''</sub>      |d5=
+  |a6=W<sub>''fin''</sub>      |d6=       |a62=H<sub>''fin''</sub> |d62=
 }}
 </table>
@@ Line 181: / Line 228: @@
 == SRAM Scaling ==
-For Intel, from [[2 µm]] to [[10 nm]], SRAM 6T [[bit cells]] have had an average shrink of 0.496x in an attempt to maintain [[Moore's Law]] double density observation/requirement. Note that SRAM shrunk more significantly prior to the [[65 nm process]] node.
+For Intel, from [[2 µm]] to [[10 nm]], SRAM 6T [[bit cells]] have had an average shrink of 0.496x in an attempt to maintain [[Moore's Law]] double density observation/requirement. Note that SRAM shrunk more significantly prior to the [[65 nm process]] node. It should also be noted that logic typically scales better than the typical 6T SRAM cells, so raw logic density scaled more over time. Nonetheless, the size of the SRAM can be as much as three to four times the density of the typical logic cell.
 [[File:intel sram bit cell scaling.png|900px]]
+== Other processes ==
+{{other processes list}}
+== See also ==
+* {{intel|Copy Exactly!}}
+[[Category:intel]]

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