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{{intel title|Silvermont|arch}}
 
{{intel title|Silvermont|arch}}
−
'''Silvermont''' is [[Intel]]'s [[22 nm]] [[microarchitecture]] for the {{intel|Atom|Atom family}} of [[system on chip]]s. Introduced in 2013, Silvermont was the successor to {{intel|Saltwell}}, targeting smartphones, tablets, embedded devices, and consumer electronics.
+
{{microarchitecture
 +
| atype            = CPU
 +
| name          = Silvermont
 +
| designer      = Intel
 +
| manufacturer  = Intel
 +
| introduction  = 2013
 +
| phase-out    = 2015
 +
| process      = 22 nm
 +
| cores        = 1
 +
| cores 2      = 2
 +
| cores 3      = 4
 +
| cores 4      = 8
 +
 
 +
| pipeline      = Yes
 +
| type          = Superscalar
 +
| OoOE          = Yes
 +
| speculative  = Yes
 +
| renaming      = Yes
 +
|isa=x86-64
 +
| stages min    = 12
 +
| stages max    = 14
 +
| issues        = 2
 +
 
 +
| inst          = Yes
 +
| feature      =
 +
| extension    = MOVBE
 +
| extension 2  = MMX
 +
| extension 3  = SSE
 +
| extension 4  = SSE2
 +
| extension 5  = SSE3
 +
| extension 6  = SSSE3
 +
| extension 7  = SSE4.1
 +
| extension 8  = SSE4.2
 +
| extension 9  = POPCNT
 +
| extension 10  = AES
 +
| extension 11  = PCLMUL
 +
| extension 12  = RDRND
 +
 
 +
| cache        = Yes
 +
| l1i          = 32 KiB
 +
| l1i per      = Core
 +
| l1i desc      = 8-way set associative
 +
| l1d          = 24 KiB
 +
| l1d per      = Core
 +
| l1d desc      = 6-way set associative
 +
| l2            = 1 MiB
 +
| l2 per        = 2 Cores
 +
| l2 desc      = 16-way set associative
 +
 
 +
| core names      = Yes
 +
| core name        = Tangier
 +
| core name 2      = Valleyview
 +
| core name 3      = Avoton
 +
| core name 4      = Rangeley
 +
 
 +
| succession      = Yes
 +
| predecessor      = Saltwell
 +
| predecessor link = intel/microarchitectures/saltwell
 +
| successor        = Airmont
 +
| successor link  = intel/microarchitectures/airmont
 +
}}
 +
'''Silvermont''' ('''SLM''') is [[Intel]]'s [[22 nm]] [[microarchitecture]] for the {{intel|Atom|Atom family}} of [[system on chip]]s. Introduced in 2013, Silvermont was the successor to {{intel|Saltwell}}, targeting smartphones, tablets, embedded devices, and consumer electronics.
  
 
== Codenames ==
 
== Codenames ==
Line 9: Line 70:
 
| {{intel|Merrifield}} || {{intel|Tangier}} || Smartphones
 
| {{intel|Merrifield}} || {{intel|Tangier}} || Smartphones
 
|-
 
|-
−
| {{intel|Bay Trail}} || {{intel|Valleyview}} || Tablets
+
| {{intel|Moorefield}} || {{intel|Anniedale}} || High-end Smartphones
 +
|-
 +
| {{intel|Slayton}}    ||  {{intel|SoFIA}} || Smartphones (3G only)
 +
|-
 +
| {{intel|Bay Trail}} || {{intel|Bay Trail}} || Tablets
 
|-
 
|-
 
| {{intel|Edisonville}} || {{intel|Avoton}} || Microservers
 
| {{intel|Edisonville}} || {{intel|Avoton}} || Microservers
Line 15: Line 80:
 
| {{intel|Edisonville}} || {{intel|Rangeley}} || Embedded Networking
 
| {{intel|Edisonville}} || {{intel|Rangeley}} || Embedded Networking
 
|}
 
|}
 +
 +
== Process Technology ==
 +
{{main|intel/microarchitectures/ivy bridge#Process_Technology|l1=Ivy Bridge § Process Technology}}
 +
Silvermont-based chips are manufactured on Intel's [[22 nm process]].
  
 
== Architecture==
 
== Architecture==
Line 25: Line 94:
 
* Support up to {{intel|Westmere}}
 
* Support up to {{intel|Westmere}}
 
* Multi-core modular system (up to 8 cores)
 
* Multi-core modular system (up to 8 cores)
 +
 +
==== New instructions ====
 +
Silvermont introduced a number of {{x86|extensions|new instructions}}:
 +
 +
* {{x86|SSE4.1|<code>SSE4.1</code>}} - Streaming SIMD Extensions, Version 4.1
 +
* {{x86|SSE4.2|<code>SSE4.2</code>}} - Streaming SIMD Extensions, Version 4.2
 +
* {{x86|MOVBE|<code>MOVBE</code>}} - Move Big-Endian instruction
 +
* {{x86|CRC32|<code>CRC32</code>}} - [[Hardware-accelerated]] [[CRC32]]
 +
* {{x86|POPCNT|<code>POPCNT</code>}} - Hardware-accelerated [[population count]]
 +
* {{x86|CLMUL|<code>CLMUL</code>}} - Hardware-accelerated Carry-less Multiplication
 +
* {{x86|AES|<code>AES</code>}} - Hardware-accelerated AES operations
 +
* {{x86|RDRAND|<code>RDRAND</code>}} - Secure Key Technology extension
 +
* {{x86|PREFETCHW|<code>PREFETCHW</code>}} - Prefetch data into caches, hinting a write is expected in the future
 +
 +
=== Block Diagram ===
 +
[[File:silvermont block.png]]
  
 
=== Core Modules ===
 
=== Core Modules ===
 
[[File:silvermont modules.svg|right|450px]]
 
[[File:silvermont modules.svg|right|450px]]
−
Silvermont employees a modular core design. Each module consists of 2 cores and 2 threads with exclusive hardware - resources are not shared. Within each module is a 1 MB L2 cache shared between the two cores. The L1 is still identical to {{intel|Saltwell|Saltwell's}}: 32K L1I$ and 24K L1D$. Each module as a dedicated point-to-point interface (IDI) to the system agent. Each module has a per-core frequency and power management support. This is a departure from previous microarchitectures as well as similar desktop (e.g. Core) where all cores are tied to the same frequency.
+
Silvermont employs a modular core design. Each module consists of 2 cores and 2 threads with exclusive hardware - resources are not shared. Within each module is a 1 MB L2 cache shared between the two cores. The L1 is still identical to {{intel|Saltwell|Saltwell's}}: 32K L1I$ and 24K L1D$. Each module as a dedicated point-to-point interface (IDI) to the system agent. Each module has a per-core frequency and power management support. This is a departure from previous microarchitectures as well as similar desktop (e.g. Core) where all cores are tied to the same frequency.
  
 
==== System Agent ====
 
==== System Agent ====
−
The system agent acts very much like a [[northbridge]] however it does a much better job than previous {{intel|Atom}} microarchitectures performance-wise because it's capable of reordering all requests from all consumers (e.g. Core, GPU).
+
The system agent (''Silvermont System Agent''') acts very much like a [[North Bridge]] however it does a much better job than previous {{intel|Atom}} microarchitectures performance-wise because it's capable of reordering all requests from all consumers (e.g. Core, GPU).
 +
 
 +
==== IDI ====
 +
While the previous {{intel|Atom}} architecture did away with the memory controller by integrating and other support chips on-die, it still used a Front Side Bus implementation to talk to North Bridge. In Silvermont, this was replaced with a lightweight in-die interconnect (IDI) - same one used in the {{\\|Core}} processors. The use of IDI should have noticeable performance impact per thread.
  
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
Line 37: Line 125:
 
** Hardware prefetchers
 
** Hardware prefetchers
 
** L1 Cache:
 
** L1 Cache:
−
*** 32 KB 8-way [[set associative]] instruction
+
*** 32 [[KiB]] 8-way [[set associative]] instruction, 64 B line size
−
**** 1 read and 1 write port
+
*** 24 KiB 6-way set associative data, 64 B line size
−
*** 24 KB 6-way set associative data
 
−
**** 1 read and 1 write port
 
−
*** 8 transistors (instead of 6) to reduce voltage
 
 
*** Per core
 
*** Per core
 
** L2 Cache:
 
** L2 Cache:
−
*** 512 KB 8-way set associative
+
*** 1 MiB 16-way set associative, 64 B line size
−
*** ECC
+
*** Per 2 cores
−
*** separate voltage rail, fixed @ 1.05V
+
*** 32B/cycle, 14 cycle latency
−
*** Per core
 
 
** L3 Cache:
 
** L3 Cache:
 
*** No level 3 cache
 
*** No level 3 cache
−
** Non-Cache Shared State Memory
 
−
*** 256KB low-power SRAM
 
−
*** separate voltage plane
 
−
*** always-on block that stores architectural states while in various power saving modes
 
 
** RAM
 
** RAM
−
*** Maximum of 1GB, 2 GB, and 4 GB
+
*** Maximum of 1 GiB, 2 GiB, and 4 GiB
 
*** dual 32-bit channels, 1 or 2 ranks per channel
 
*** dual 32-bit channels, 1 or 2 ranks per channel
 +
 +
=== Multithreading ===
 +
Silvermont dropped support for Intel Hyper-Threading Technology.
 +
 +
=== Pipeline ===
 +
While Silvermont share some similarities with {{\\|Saltwell}}, it introduces a number of significant changes that sets it apart from part {{intel|Atom}} microarchitectures. Like {{\\|Saltwell}}, the pipeline is still uses a dual-issue design; however it has a pipeline that is 2 stages shorter with a branch misprediction penalty of 3 cycles lower. Silvermont is the first microarchitecture to introduce [[out-of-order execution]] (OoOE)
 +
 +
[[File:silvermont pipeline.svg]]
 +
 +
Silvermont pipeline decodes and issues 2 instructions and dispatches 5 operations/cycle.
 +
 +
==== Instruction Fetch ====
 +
Instruction Fetch, just like in previous microarchs make up the first three stages of the pipeline. However, with the introduction of out-of-order execution, silvermont's more aggressive fetching and branch prediction mean stalled instructions do not clog the entire pipeline as it did in {{intel|Saltwell}}. 
 +
 +
====Instruction Decode====
 +
In previous generations of microarchitectures, common software code had roughly 5% of instructions split up into micro-ops. In Silvermont this is reduced down to just 1-2%. This reduction translates directly into performance because it eliminates the 3-4 additional cycles of overhead. Silvermont has a second branch predictor that can make more accurate predictions based on previously unknown information (e.g. target address from memory or register) and override the generic predictor. Nevertheless the expense of branch misprediction penalties was also reduced by 3 stages (down to 10 cycles from 13 in {{intel|Saltwell}}).
 +
 +
=== Branch Prediction ===
 +
Silvermont has two branch predictions: one that controls the instruction fetching and a second one that can override the first during the decode stage after gather additional information. The second predictor controls the speculative instruction issuing. For the first predictor, Silvermont uses a [[Branch Target Buffer]] to determine the next fetch address which also includes a 4-entry Return Stack Buffer for calls and returns handling.
 +
 +
== Die ==
 +
8-core {{intel|Avoton}} Die:
 +
 +
[[File:silvermont die (quad-core).png]]
 +
 +
== Cores ==
 +
* {{intel|Tangier}} - SoCs for Smartphones
 +
* {{intel|Valleyview}} - SoCs for Tablets
 +
* {{intel|Avoton}} - SoCs for Microservers
 +
* {{intel|Rangeley}} - SoCs for Embedded Networking
 +
 +
== All Silvermont Chips ==
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 +
          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
<table class="wikitable sortable">
 +
<tr><th colspan="12" style="background:#D6D6FF;">Silvermont Chips</th></tr>
 +
<tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr>
 +
<tr><th>Model</th><th>µarch</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>TDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr>
 +
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Silvermont]]
 +
|?full page name
 +
|?model number
 +
|?microarchitecture
 +
|?platform
 +
|?core name
 +
|?first launched
 +
|?sdp
 +
|?tdp
 +
|?base frequency
 +
|?max memory
 +
|?integrated gpu
 +
|?integrated gpu base frequency
 +
|?integrated gpu max frequency
 +
|format=template
 +
|template=proc table 2
 +
|userparam=13
 +
|mainlabel=-
 +
}}
 +
</table>

Latest revision as of 08:35, 25 September 2019

Edit Values
Silvermont µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2013
Phase-out2015
Process22 nm
Core Configs1, 2, 4, 8
Pipeline
TypeSuperscalar
SpeculativeYes
Reg RenamingYes
Stages12-14
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND
Cache
L1I Cache32 KiB/Core
8-way set associative
L1D Cache24 KiB/Core
6-way set associative
L2 Cache1 MiB/2 Cores
16-way set associative
Cores
Core NamesTangier,
Valleyview,
Avoton,
Rangeley
Succession

Silvermont (SLM) is Intel's 22 nm microarchitecture for the Atom family of system on chips. Introduced in 2013, Silvermont was the successor to Saltwell, targeting smartphones, tablets, embedded devices, and consumer electronics.

Codenames[edit]

Platform Core Target
Merrifield Tangier Smartphones
Moorefield Anniedale High-end Smartphones
Slayton SoFIA Smartphones (3G only)
Bay Trail Bay Trail Tablets
Edisonville Avoton Microservers
Edisonville Rangeley Embedded Networking

Process Technology[edit]

Main article: Ivy Bridge § Process Technology

Silvermont-based chips are manufactured on Intel's 22 nm process.

Architecture[edit]

Silvermont introduced a number of significant changes from the previous Atom microarchitecture in addition to the increase performance and lower power consumption.

Key changes from Saltwell[edit]

  • Pipeline is now OoOE
  • 14 stage (2 shorter)
  • 10 stage panelty for miss (3 shorter)
  • Support up to Westmere
  • Multi-core modular system (up to 8 cores)

New instructions[edit]

Silvermont introduced a number of new instructions:

Block Diagram[edit]

silvermont block.png

Core Modules[edit]

silvermont modules.svg

Silvermont employs a modular core design. Each module consists of 2 cores and 2 threads with exclusive hardware - resources are not shared. Within each module is a 1 MB L2 cache shared between the two cores. The L1 is still identical to Saltwell's: 32K L1I$ and 24K L1D$. Each module as a dedicated point-to-point interface (IDI) to the system agent. Each module has a per-core frequency and power management support. This is a departure from previous microarchitectures as well as similar desktop (e.g. Core) where all cores are tied to the same frequency.

System Agent[edit]

The system agent (Silvermont System Agent') acts very much like a North Bridge however it does a much better job than previous Atom microarchitectures performance-wise because it's capable of reordering all requests from all consumers (e.g. Core, GPU).

IDI[edit]

While the previous Atom architecture did away with the memory controller by integrating and other support chips on-die, it still used a Front Side Bus implementation to talk to North Bridge. In Silvermont, this was replaced with a lightweight in-die interconnect (IDI) - same one used in the Core processors. The use of IDI should have noticeable performance impact per thread.

Memory Hierarchy[edit]

  • Cache
    • Hardware prefetchers
    • L1 Cache:
      • 32 KiB 8-way set associative instruction, 64 B line size
      • 24 KiB 6-way set associative data, 64 B line size
      • Per core
    • L2 Cache:
      • 1 MiB 16-way set associative, 64 B line size
      • Per 2 cores
      • 32B/cycle, 14 cycle latency
    • L3 Cache:
      • No level 3 cache
    • RAM
      • Maximum of 1 GiB, 2 GiB, and 4 GiB
      • dual 32-bit channels, 1 or 2 ranks per channel

Multithreading[edit]

Silvermont dropped support for Intel Hyper-Threading Technology.

Pipeline[edit]

While Silvermont share some similarities with Saltwell, it introduces a number of significant changes that sets it apart from part Atom microarchitectures. Like Saltwell, the pipeline is still uses a dual-issue design; however it has a pipeline that is 2 stages shorter with a branch misprediction penalty of 3 cycles lower. Silvermont is the first microarchitecture to introduce out-of-order execution (OoOE)

silvermont pipeline.svg

Silvermont pipeline decodes and issues 2 instructions and dispatches 5 operations/cycle.

Instruction Fetch[edit]

Instruction Fetch, just like in previous microarchs make up the first three stages of the pipeline. However, with the introduction of out-of-order execution, silvermont's more aggressive fetching and branch prediction mean stalled instructions do not clog the entire pipeline as it did in Saltwell.

Instruction Decode[edit]

In previous generations of microarchitectures, common software code had roughly 5% of instructions split up into micro-ops. In Silvermont this is reduced down to just 1-2%. This reduction translates directly into performance because it eliminates the 3-4 additional cycles of overhead. Silvermont has a second branch predictor that can make more accurate predictions based on previously unknown information (e.g. target address from memory or register) and override the generic predictor. Nevertheless the expense of branch misprediction penalties was also reduced by 3 stages (down to 10 cycles from 13 in Saltwell).

Branch Prediction[edit]

Silvermont has two branch predictions: one that controls the instruction fetching and a second one that can override the first during the decode stage after gather additional information. The second predictor controls the speculative instruction issuing. For the first predictor, Silvermont uses a Branch Target Buffer to determine the next fetch address which also includes a 4-entry Return Stack Buffer for calls and returns handling.

Die[edit]

8-core Avoton Die:

silvermont die (quad-core).png

Cores[edit]

All Silvermont Chips[edit]

Silvermont Chips
Main processorIGP
ModelµarchPlatformCoreLaunchedSDPTDPFreqMax MemNameFreqMax Freq
x3-C3130SilvermontSoFIASoFIA4 March 20151,000 MHz
1 GHz
1,000,000 kHz
Mali-400 MP2480 MHz
0.48 GHz
480,000 KHz
x3-C3200RKSilvermontSoFIASoFIA4 March 20152 W
2,000 mW
0.00268 hp
0.002 kW
1,100 MHz
1.1 GHz
1,100,000 kHz
2,048 MiB
2,097,152 KiB
2,147,483,648 B
2 GiB
0.00195 TiB
Mali-450 MP4600 MHz
0.6 GHz
600,000 KHz
x3-C3230RKSilvermontSoFIASoFIA4 March 20152 W
2,000 mW
0.00268 hp
0.002 kW
1,100 MHz
1.1 GHz
1,100,000 kHz
2,048 MiB
2,097,152 KiB
2,147,483,648 B
2 GiB
0.00195 TiB
Mali-450 MP4600 MHz
0.6 GHz
600,000 KHz
x3-C3405SilvermontSoFIASoFIAApril 20152 W
2,000 mW
0.00268 hp
0.002 kW
1,200 MHz
1.2 GHz
1,200,000 kHz
2,048 MiB
2,097,152 KiB
2,147,483,648 B
2 GiB
0.00195 TiB
Mali T720 MP2456 MHz
0.456 GHz
456,000 KHz
x3-C3445SilvermontSoFIASoFIAApril 20152 W
2,000 mW
0.00268 hp
0.002 kW
1,200 MHz
1.2 GHz
1,200,000 kHz
2,048 MiB
2,097,152 KiB
2,147,483,648 B
2 GiB
0.00195 TiB
Mali T720 MP2456 MHz
0.456 GHz
456,000 KHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/silvermont&oldid=93674"
Facts about "Silvermont - Microarchitectures - Intel"
RDF feed
codenameSilvermont +
core count1 +, 2 +, 4 + and 8 +
designerIntel +
first launched2013 +
full page nameintel/microarchitectures/silvermont +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameSilvermont +
phase-out2015 +
pipeline stages (max)14 +
pipeline stages (min)12 +
process22 nm (0.022 μm, 2.2e-5 mm) +