From WikiChip
Difference between revisions of "arm holdings/microarchitectures/cortex-x2"
< arm holdings

(add tables)
 
Line 1: Line 1:
−
{{armh title|Cortex-X2|arch}}
+
{{armh title|Cortex-X2 (Matterhorn-ELP)|arch}}
 
{{microarchitecture
 
{{microarchitecture
−
|atype=CPU
+
| atype = CPU
−
|name=Cortex-X2
+
| name = Cortex-X2 (Matterhorn-ELP)
−
|designer=ARM Holdings
+
| codename = Cortex-X2
−
|manufacturer=TSMC
+
| core name = '''Cortex-X2'''
−
|predecessor=Cortex-X1
+
| designer = ARM Holdings
−
|predecessor link=arm holdings/microarchitectures/cortex-x1
+
| manufacturer = TSMC
−
|successor=Cortex-X3
+
| introduction = 2021
−
|successor link=arm holdings/microarchitectures/cortex-x3
+
| process = 10 nm
−
|contemporary=Cortex-A710
+
| process 2 = 7 nm
−
|contemporary link=arm holdings/microarchitectures/cortex-a710
+
| process 3 = 5 nm
 +
| cores = 1
 +
| cores 2 = 2
 +
| cores 3 = 4
 +
| cores 4 = 6
 +
| cores 5 = 8
 +
| cores 6 = 10
 +
| cores 7 = 12
 +
| type = Superscalar
 +
| type 2 = Pipelined
 +
| oooe = Yes
 +
| speculative = Yes
 +
| renaming = Yes
 +
| stages = 288
 +
| decode = 5-way
 +
| isa = ARMv9.0-A
 +
| feature = Hardware virtualization
 +
| extension = FPU
 +
| extension 2 = NEON
 +
| l1i = 64 KiB
 +
| l1i per = core
 +
| l1i desc = 4-way set associative
 +
| l1d = 64 KiB
 +
| l1d per = core
 +
| l1d desc = 4-way set associative
 +
| l2 = 1 MiB
 +
| l2 per = core
 +
| l2 desc = 8-way set associative
 +
| l3 = 16 MiB
 +
| l3 per = cluster
 +
| l3 desc = 16-way set associative
 +
| predecessor = '''Cortex-X1''' (Hera)
 +
| predecessor link = arm holdings/microarchitectures/cortex-x1
 +
| successor = '''Cortex-X3''' (Makalu-ELP)
 +
| successor link = arm holdings/microarchitectures/cortex-x3
 +
| contemporary = '''Cortex-A710''' (Matterhorn)
 +
| contemporary link = arm holdings/microarchitectures/cortex-a710
 +
| contemporary 2 = '''Cortex-A510''' (Klein)
 +
| contemporary 2 link = arm holdings/microarchitectures/cortex-a510
 
}}
 
}}
−
'''Cortex-X2''' is the successor to the {{\\|Cortex-X1}}, a performance-enhanced version of the {{\\|Cortex-A710}}, low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market.
+
 
 +
'''Cortex-X2''' ''(Matterhorn-ELP)'' is the successor to the '''{{\\|Cortex-X1}}''' ''(Hera)'', a performance-enhanced version of the '''{{\\|Cortex-A710}}''' ''({{armh|Matterhorn|l=arch}})'', low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market.
 +
 
 +
=== [[Cortex]]-X ===
 +
:;[[ARM]] • [[Cortex]]
 +
{| class="wikitable" style="text-align: center;
 +
|-
 +
! Year !! Cortex-X Core !! Cortex-A Core
 +
|-
 +
| [[2020]] || {{armh|Cortex-X1|l=arch}} (''{{armh|Hera|l=arch}}'') <br>{{armh|Cortex-X1C|l=arch}} (''{{armh|Hera-C|l=arch}}'') || {{armh|Cortex-A78|l=arch}} (''{{armh|Hercules|l=arch}}'') <!--<br>{{armh|Cortex-A78AE|l=arch}} (''{{armh|Hercules-AE|l=arch}}'')--> <br>{{armh|Cortex-A78C|l=arch}} (''{{armh|Hera Prime|l=arch}}'')
 +
|-
 +
| [[2021]] || {{armh|Cortex-X2|l=arch}} <br>(''{{armh|Matterhorn-ELP|l=arch}}'') || {{armh|Cortex-A710|l=arch}} (''{{armh|Matterhorn|l=arch}}'') <br>{{armh|Cortex-A510|l=arch}} (''{{armh|Klein|l=arch}}'')
 +
|-
 +
| [[2022]] || {{armh|Cortex-X3|l=arch}} (''{{armh|Makalu-ELP|l=arch}}'') || {{armh|Cortex-A715|l=arch}} (''{{armh|Makalu|l=arch}}'')
 +
|-
 +
| [[2023]] || {{armh|Cortex-X4|l=arch}} (''{{armh|Hunter-ELP|l=arch}}'') || {{armh|Cortex-A720|l=arch}} (''{{armh|Hunter|l=arch}}'') <br>{{armh|Cortex-A520|l=arch}} (''{{armh|Hayes|l=arch}}'')
 +
|-
 +
| [[2024]] || <s>{{armh|Cortex-X5|l=arch}} (''{{armh|Chaberton-ELP|l=arch}}'')</s> <br>{{armh|Cortex-X925|l=arch}} (''{{armh|Blackhawk|l=arch}}'') || {{armh|Cortex-A720AE|l=arch}} (''{{armh|Hunter-AE|l=arch}}'') <br>{{armh|Cortex-A725|l=arch}} (''{{armh|Chaberton|l=arch}}'')
 +
|-
 +
| [[2025]] || {{armh|Cortex-X930|l=arch}} (''{{armh|Travis|l=arch}}'') || {{armh|Cortex-A730|l=arch}} (''{{armh|Gelas|l=arch}}'') <br>{{armh|Cortex-A530|l=arch}} (''{{armh|Nevis|l=arch}}'')
 +
|-
 +
|}
 +
 
 +
== Architecture ==
 +
 
 +
=== Key changes from {{\\|Cortex-X1}} ===
 +
The processor implements the following changes: <ref>{{cite book |date=2021-05-25 |title=Arm Launches Its New Flagship Performance Armv9 Core: Cortex-X2 |url=https://fuse.wikichip.org/news/5269/arm-launches-its-new-flagship-performance-armv9-core-cortex-x2/ |website=WikiChip Fuse |last=WikiChip Fuse}}</ref>
 +
* Instruction set ARMv9.0
 +
* 10 cycle pipeline down from 11, created by reducing dispatch stage from 2 cycles to 1
 +
* Reorder buffer (ROB) increased by 30% from 224 entries to 288
 +
* dTLB increased by 20% from 40 entries to 48
 +
* Bfloat16 data type support
 +
* Support for Aarch32 removed
 +
* SVE2 SIMD support
 +
* DSU-110
 +
** Up to 12 cores (up from 8 cores)
 +
** Up to 16MB L3 cache (up from 8MB)
 +
* CoreLink CI-700/NI-700: up to 32MB SLC
 +
 
 +
Performance claims:
 +
*Comparing the {{\\|Cortex-X2}} <ref>{{cite book |title=Arm Announces Mobile Armv9 CPU Microarchitectures: Cortex-X2, Cortex-A710 & Cortex-A510 |url=https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510 |website=anandtech.com}}</ref> to the {{\\|Cortex-X1}} with the same process, <br>clock speed, and 4MB of L3 cache (also known as ISO-process):
 +
**16% greater integer performance / IPC
 +
**100% greater ML performance
 +
*30% peak performance improvement over the {{\\|Cortex-X1}} in smartphones
 +
:(3.3GHz, 1MB L2, 8MB L3)
 +
* 40% faster than an Intel Core i5-1135G7 at 15W (3.5GHz, 1MB L2, 16MB L3)
 +
 
 +
=== Comparison ===
 +
 
 +
:;"Prime" core
 +
{| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;
 +
|-
 +
![[Microarchitecture|Architecture]]
 +
!{{armh|Cortex-A78|l=arch}}
 +
!{{armh|Cortex-X1|l=arch}}
 +
!{{armh|Cortex-X2|l=arch}}
 +
!{{armh|Cortex-X3|l=arch}}
 +
!{{armh|Cortex-X4|l=arch}}
 +
!{{armh|Cortex-X925|l=arch}}
 +
!{{armh|Cortex-X930|l=arch}}
 +
|-
 +
!Code name
 +
|''{{armh|Hercules|l=arch}}''
 +
|''Hera''
 +
|''{{armh|Matterhorn|l=arch}}-ELP''
 +
|''{{armh|Makalu|l=arch}}-ELP''
 +
|''{{armh|Hunter-ELP|l=arch}}''
 +
|''Blackhawk''
 +
|''Travis''
 +
|-
 +
!ISA
 +
| colspan="2" |[[ARMv8]].2-A
 +
| colspan="2" |ARMv9.0-A
 +
| colspan="3" |ARMv9.2-A
 +
|-
 +
!Peak clock speed
 +
| colspan="3" |~3.0&nbsp;GHz
 +
|~3.3&nbsp;GHz
 +
|~3.4&nbsp;GHz
 +
|~3.8&nbsp;GHz
 +
|~4.2&nbsp;GHz
 +
|-
 +
!Max in-flight
 +
|2x 160
 +
|2x 224
 +
|2x 288
 +
|2x 320
 +
|2x 384
 +
|2x 768
 +
|
 +
|-
 +
!L0 (Mops entries)
 +
|1536 <ref>{{cite book |title=Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence |url=https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging }}</ref>
 +
| colspan="2" |3072
 +
|1536
 +
|0
 +
|
 +
|
 +
|-
 +
!L1-I + L1-D
 +
|32+32 KiB
 +
| colspan="2" |64+64 KiB
 +
| colspan="2" |64+64 KiB
 +
|64+64 KiB
 +
|
 +
|-
 +
!L2
 +
|128–512 KiB
 +
| colspan="3" |0.25–1 MiB
 +
|0.5–2 MiB
 +
|2–3 MiB
 +
|
 +
|-
 +
!L3
 +
| colspan="2" |0–8 MiB <ref>{{cite book |last=Schor |first=David |date=2020-05-26 |title=Arm Cortex-X1: The First From The Cortex-X Custom Program |url=https://fuse.wikichip.org/news/3543/arm-cortex-x1-the-first-from-the-cortex-x-custom-program/ |website=WikiChip Fuse }}</ref>
 +
| colspan="2" |0–16 MiB
 +
| colspan="2" |0–32 MiB
 +
|
 +
|-
 +
!Decode width
 +
|4
 +
| colspan="2" |5
 +
|6
 +
|10 <ref>{{cite book |date=2023-05-29 |title=Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive |url=https://www.androidauthority.com/arm-cortex-x4-explained-3328008/ |website=Android Authority}}</ref>
 +
|10
 +
|
 +
|-
 +
!Dispatch
 +
|6/cycle
 +
| colspan="3" |8/cycle
 +
| colspan="2" |10/cycle
 +
|
 +
|-
 +
|}
 +
 
 +
== References ==

Latest revision as of 19:22, 15 April 2025

Edit Values
Cortex-X2 (Matterhorn-ELP) µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
Introduction2021
Process10 nm, 7 nm, 5 nm
Core Configs1, 2, 4, 6, 8, 10, 12
Pipeline
TypeSuperscalar, Pipelined
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages288
Decode5-way
Instructions
ISAARMv9.0-A
ExtensionsFPU, NEON
Cache
L1I Cache64 KiB/core
4-way set associative
L1D Cache64 KiB/core
4-way set associative
L2 Cache1 MiB/core
8-way set associative
L3 Cache16 MiB/cluster
16-way set associative
Cores
Core NamesCortex-X2
Succession
Contemporary
Cortex-A710 (Matterhorn)
Cortex-A510 (Klein)

Cortex-X2 (Matterhorn-ELP) is the successor to the Cortex-X1 (Hera), a performance-enhanced version of the Cortex-A710 (Matterhorn), low-power high-performance ARM microarchitecture designed by Arm for the mobile market.

Cortex-X[edit]

ARM • Cortex
Year Cortex-X Core Cortex-A Core
2020 Cortex-X1 (Hera)
Cortex-X1C (Hera-C) 		Cortex-A78 (Hercules)
Cortex-A78C (Hera Prime)
2021 Cortex-X2
(Matterhorn-ELP) 		Cortex-A710 (Matterhorn)
Cortex-A510 (Klein)
2022 Cortex-X3 (Makalu-ELP) Cortex-A715 (Makalu)
2023 Cortex-X4 (Hunter-ELP) Cortex-A720 (Hunter)
Cortex-A520 (Hayes)
2024 Cortex-X5 (Chaberton-ELP)
Cortex-X925 (Blackhawk) 		Cortex-A720AE (Hunter-AE)
Cortex-A725 (Chaberton)
2025 Cortex-X930 (Travis) Cortex-A730 (Gelas)
Cortex-A530 (Nevis)

Architecture[edit]

Key changes from Cortex-X1[edit]

The processor implements the following changes: [1]

  • Instruction set ARMv9.0
  • 10 cycle pipeline down from 11, created by reducing dispatch stage from 2 cycles to 1
  • Reorder buffer (ROB) increased by 30% from 224 entries to 288
  • dTLB increased by 20% from 40 entries to 48
  • Bfloat16 data type support
  • Support for Aarch32 removed
  • SVE2 SIMD support
  • DSU-110
    • Up to 12 cores (up from 8 cores)
    • Up to 16MB L3 cache (up from 8MB)
  • CoreLink CI-700/NI-700: up to 32MB SLC

Performance claims:

  • Comparing the Cortex-X2 [2] to the Cortex-X1 with the same process,
    clock speed, and 4MB of L3 cache (also known as ISO-process):
    • 16% greater integer performance / IPC
    • 100% greater ML performance
  • 30% peak performance improvement over the Cortex-X1 in smartphones
(3.3GHz, 1MB L2, 8MB L3)
  • 40% faster than an Intel Core i5-1135G7 at 15W (3.5GHz, 1MB L2, 16MB L3)

Comparison[edit]

"Prime" core
Architecture Cortex-A78 Cortex-X1 Cortex-X2 Cortex-X3 Cortex-X4 Cortex-X925 Cortex-X930
Code name Hercules Hera Matterhorn-ELP Makalu-ELP Hunter-ELP Blackhawk Travis
ISA ARMv8.2-A ARMv9.0-A ARMv9.2-A
Peak clock speed ~3.0 GHz ~3.3 GHz ~3.4 GHz ~3.8 GHz ~4.2 GHz
Max in-flight 2x 160 2x 224 2x 288 2x 320 2x 384 2x 768
L0 (Mops entries) 1536 [3] 3072 1536 0
L1-I + L1-D 32+32 KiB 64+64 KiB 64+64 KiB 64+64 KiB
L2 128–512 KiB 0.25–1 MiB 0.5–2 MiB 2–3 MiB
L3 0–8 MiB [4] 0–16 MiB 0–32 MiB
Decode width 4 5 6 10 [5] 10
Dispatch 6/cycle 8/cycle 10/cycle

References[edit]

  1. ↑ WikiChip Fuse (2021-05-25). Arm Launches Its New Flagship Performance Armv9 Core: Cortex-X2.
  2. ↑ Arm Announces Mobile Armv9 CPU Microarchitectures: Cortex-X2, Cortex-A710 & Cortex-A510.
  3. ↑ Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence.
  4. ↑ Schor, David (2020-05-26). Arm Cortex-X1: The First From The Cortex-X Custom Program.
  5. ↑ (2023-05-29) Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-x2&oldid=103216"
Facts about "Cortex-X2 (Matterhorn-ELP) - Microarchitectures - ARM"
RDF feed
codenameCortex-X2 +
designerARM Holdings +
full page namearm holdings/microarchitectures/cortex-x2 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-X2 +