Difference between revisions of "amd/epyc/7h12"

	Edit Values
	EPYC 7H12
	General Info
Designer	AMD
Manufacturer	TSMC, GlobalFoundries
Model Number	7H12
Part Number	100-000000055,; 100-100000055WOF
Market	Server
Introduction	September 18, 2019 (announced); September 18, 2019 (launched)
Shop	Amazon
	General Specs
Family	EPYC
Series	7002
Locked	Yes
Frequency	2,600 MHz
Turbo Frequency	3,300 MHz
Clock multiplier	26
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen 2
Core Name	Rome
Core Family	23
Core Model	49
Core Stepping	B0
Process	7 nm, 14 nm
Technology	CMOS
MCP	Yes (9 dies)
Word Size	64 bit
Cores	64
Threads	128
Max Memory	4 TiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
	Electrical
TDP	280 W
	Packaging
Package	SP3, FCLGA-4094 (FC-OLGA)
Dimension	75.4 mm × 58.5 mm × 6.26 mm
Pitch	0.87 mm × 1 mm
Contacts	4094
Socket	SP3, LGA-4094

Latest revision as of 19:34, 8 January 2021

EPYC 7H12 is a 64-bit 64-core x86 server microprocessor designed and introduced by AMD in late 2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7H12 has a TDP of 280 W with a base frequency of 2.6 GHz and a boost frequency of up to 3.3 GHz. This processor supports up to two-way SMP and up to 4 TiB of eight channels DDR4-3200 memory per socket.

This is a specially-binned microprocessor intended for the HPC market. Due to the high TDP requirement, this SKU is intended to be liquid-cooled.

Cache[edit]

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

4 MiB

4,096 KiB
4,194,304 B

L1I$	2 MiB 2,048 KiB 2,097,152 B	64x32 KiB	8-way set associative
L1D$	2 MiB 2,048 KiB 2,097,152 B	64x32 KiB	8-way set associative	write-back

L2$

32 MiB

32,768 KiB
33,554,432 B
0.0313 GiB

		64x512 KiB	8-way set associative	write-back

L3$

256 MiB

262,144 KiB
268,435,456 B
0.25 GiB

		16x16 MiB

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-3200
Supports ECC	Yes
Max Mem	4 TiB
Controllers	8
Channels	8
Max Bandwidth	190.7 GiB/s 195,276.8 MiB/s 204.763 GB/s 204,762.566 MB/s 0.186 TiB/s 0.205 TB/s
Bandwidth	Single 23.84 GiB/s Double 47.68 GiB/s Quad 95.37 GiB/s Hexa 143.1 GiB/s Octa 190.7 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 4.0
	Max Lanes: 128
	Configuration: x16, x8

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
SSE4a	Streaming SIMD Extensions 4a
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
SHA	SHA Extensions
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
SMT	Simultaneous Multithreading
AMD-Vi	AMD-Vi (I/O MMU virtualization)
AMD-V	AMD Virtualization
SME	Secure Memory Encryption
TSME	Transparent SME
SEV	Secure Encrypted Virtualization
SenseMI	SenseMI Technology
Boost 2	Precision Boost 2

References[edit]

"AMD EPYC™ 7H12". AMD.com. Retrieved October 2020.
"AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter", AMD Publ. #LE-70002, Rev. 02, April 2020

@@ Line 7: / Line 7: @@
 |manufacturer 2=GlobalFoundries
 |model number=7H12
+|part number=100-000000055
+|part number 2=100-100000055WOF
 |market=Server
 |first announced=September 18, 2019
@@ Line 21: / Line 23: @@
 |core name=Rome
 |core family=23
+|core model=49
+|core stepping=B0
 |process=7 nm
 |process 2=14 nm
@@ Line 29: / Line 33: @@
 |core count=64
 |thread count=128
+|max memory=4 TiB
 |max cpus=2
-|max memory=4 TiB
 |tdp=280 W
 |package name 1=amd,socket_sp3
 }}
-'''EPYC 7H12''' is a {{arch|64}} [[64-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7H12 has a TDP of 280 W with a base frequency of 2.6 GHz and a {{amd|precision boost|boost}} frequency of up to 3.3 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
+'''EPYC 7H12''' is a {{arch|64}} [[64-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in late [[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7H12 has a TDP of 280 W with a base frequency of 2.6 GHz and a {{amd|precision boost|boost}} frequency of up to 3.3 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
 This is a specially-binned microprocessor intended for the HPC market. Due to the high TDP requirement, this SKU is intended to be liquid-cooled.
+{{#set: part of=HPC-optimized SKUs}}
 == Cache ==
@@ Line 48: / Line 53: @@
 |l1d break=64x32 KiB
 |l1d desc=8-way set associative
+|l1d policy=write-back
 |l2 cache=32 MiB
 |l2 break=64x512 KiB
@@ Line 83: / Line 89: @@
 }}
 == Features ==
 {{x86 features
 |real=Yes
@@ Line 192: / Line 198: @@
 |amdpbod=No
 }}
+== References ==
+* [https://www.amd.com/en/products/cpu/amd-epyc-7h12 "AMD EPYC™ 7H12"]. <i>AMD.com</i>. Retrieved October 2020.
+* [https://www.amd.com/system/files/documents/AMD-EPYC-7002-Series-Datasheet.pdf "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter"], AMD Publ. #LE-70002, Rev. 02, April 2020

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7H12 - AMD#pcie +
base frequency	2,600 MHz (2.6 GHz, 2,600,000 kHz) +
clock multiplier	26 +
core count	64 +
core family	23 +
core model	49 +
core name	Rome +
core stepping	B0 +
designer	AMD +
die count	9 +
family	EPYC +
first announced	September 18, 2019 +
first launched	September 18, 2019 +
full page name	amd/epyc/7h12 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd precision boost 2	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 +
has locked clock multiplier	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	4,096 KiB (4,194,304 B, 4 MiB) +
l1d$ description	8-way set associative +
l1d$ size	2,048 KiB (2,097,152 B, 2 MiB) +
l1i$ description	8-way set associative +
l1i$ size	2,048 KiB (2,097,152 B, 2 MiB) +
l2$ description	8-way set associative +
l2$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
l3$ size	256 MiB (262,144 KiB, 268,435,456 B, 0.25 GiB) +
ldate	September 18, 2019 +
manufacturer	TSMC + and GlobalFoundries +
market segment	Server +
max cpu count	2 +
max memory	4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth	190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels	8 +
microarchitecture	Zen 2 +
model number	7H12 +
name	EPYC 7H12 +
package	SP3 + and FCLGA-4094 +
part number	100-000000055 + and 100-100000055WOF +
part of	HPC-optimized SKUs +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
series	7002 +
smp max ways	2 +
socket	SP3 + and LGA-4094 +
supported memory type	DDR4-3200 +
tdp	280 W (280,000 mW, 0.375 hp, 0.28 kW) +
technology	CMOS +
thread count	128 +
turbo frequency	3,300 MHz (3.3 GHz, 3,300,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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