Difference between revisions of "amd/cores/rome"

	Edit Values
	Rome
	General Info
Designer	AMD
Manufacturer	TSMC, GlobalFoundries
Introduction	May 16, 2017 (announced); August 7, 2019 (launched)
	Microarchitecture
ISA	x86-64
Microarchitecture	Zen 2
Word Size	8 octets ; 16 nibbles ; 64 bit
Process	7 nm 0.007 μm ; 7.0e-6 mm ; , 14 nm 0.014 μm ; 1.4e-5 mm ;
Technology	CMOS
	Packaging
Package	SP3, FCLGA-4094 (FC-OLGA)
Dimension	75.4 mm 7.54 cm ; 2.969 in ; × 58.5 mm 5.85 cm ; 2.303 in ; × 6.26 mm 0.246 in ;
Pitch	0.87 mm 0.0343 in ; × 1 mm 0.0394 in ;
Contacts	4094
Socket	SP3, LGA-4094
	Succession
	Naples Milan

Revision as of 09:11, 7 August 2019

Rome codename for AMD's high-performance enterprise-level server multiprocessors based on the Zen 2 microarchitecture serving as a successor to Naples. Rome-based chips are fabricated on TSMC 7 nm process with some components made on GlobalFoundries 14 nm process.

AMD datacenter roadmap

Overview

AMD Rome system on chips are a series of high-performance multiprocessors designed by AMD based on their Zen 2 microarchitecture. Rome SoCs support both single and 2-way multiprocessing with up to a maximum of 64 cores (and 128 threads) per processor for a total of up to 128 cores (and 256 threads) for a 2-way MP system. Those SoCs support 128 PCIe lanes each. Rome is backward platform/socket (Socket SP3) compatible with Naples and forward-compatible with Milan.

Common Features

All Rome processors have the following:

128 PCIe lanes (in both single-way and dual-way multiprocessing)
- PCIe Gen 4
Octa-channel Memory
- Up to DDR4-3200 ECC
- Up to 4 TiB (8 TiB in 2MP)
Up to 64 cores / 128 threads
Everything up to AVX2 (i.e., SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2), and SHA

Rome Processors

	List of Rome Processors
Model	Family	Launched	Cores	Threads	TDP	L2$	L3$	Base	Turbo
7232P	EPYC	7 August 2019	8	16	120 W 120,000 mW 0.161 hp 0.12 kW	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	3.1 GHz 3,100 MHz 3,100,000 kHz	3.2 GHz 3,200 MHz 3,200,000 kHz
7252	EPYC	7 August 2019	8	16	120 W 120,000 mW 0.161 hp 0.12 kW	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB	3.1 GHz 3,100 MHz 3,100,000 kHz	3.2 GHz 3,200 MHz 3,200,000 kHz
7262	EPYC	7 August 2019	8	16	155 W 155,000 mW 0.208 hp 0.155 kW	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	3.2 GHz 3,200 MHz 3,200,000 kHz	3.4 GHz 3,400 MHz 3,400,000 kHz
7272	EPYC	7 August 2019	12	24	120 W 120,000 mW 0.161 hp 0.12 kW	6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB	64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB	2.9 GHz 2,900 MHz 2,900,000 kHz	3.2 GHz 3,200 MHz 3,200,000 kHz
7282	EPYC	7 August 2019	16	32	120 W 120,000 mW 0.161 hp 0.12 kW	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB	2.8 GHz 2,800 MHz 2,800,000 kHz	3.2 GHz 3,200 MHz 3,200,000 kHz
7302	EPYC	7 August 2019	16	32	155 W 155,000 mW 0.208 hp 0.155 kW	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	3 GHz 3,000 MHz 3,000,000 kHz	3.3 GHz 3,300 MHz 3,300,000 kHz
7302P	EPYC	7 August 2019	16	32	155 W 155,000 mW 0.208 hp 0.155 kW	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	3 GHz 3,000 MHz 3,000,000 kHz	3.3 GHz 3,300 MHz 3,300,000 kHz
7352	EPYC	7 August 2019	24	48	155 W 155,000 mW 0.208 hp 0.155 kW	12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	2.3 GHz 2,300 MHz 2,300,000 kHz	3.2 GHz 3,200 MHz 3,200,000 kHz
7402	EPYC	7 August 2019	24	48	180 W 180,000 mW 0.241 hp 0.18 kW	12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	2.8 GHz 2,800 MHz 2,800,000 kHz	3.35 GHz 3,350 MHz 3,350,000 kHz
7402P	EPYC	7 August 2019	24	48	180 W 180,000 mW 0.241 hp 0.18 kW	12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	2.8 GHz 2,800 MHz 2,800,000 kHz	3.35 GHz 3,350 MHz 3,350,000 kHz
7452	EPYC	7 August 2019	32	64	155 W 155,000 mW 0.208 hp 0.155 kW	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	2.35 GHz 2,350 MHz 2,350,000 kHz	3.35 GHz 3,350 MHz 3,350,000 kHz
7502	EPYC	7 August 2019	32	64	180 W 180,000 mW 0.241 hp 0.18 kW	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	2.5 GHz 2,500 MHz 2,500,000 kHz	3.35 GHz 3,350 MHz 3,350,000 kHz
7502P	EPYC	7 August 2019	32	64	180 W 180,000 mW 0.241 hp 0.18 kW	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	2.5 GHz 2,500 MHz 2,500,000 kHz	3.35 GHz 3,350 MHz 3,350,000 kHz
7532	EPYC	19 February 2020	32	64	200 W 200,000 mW 0.268 hp 0.2 kW	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	256 MiB 262,144 KiB 268,435,456 B 0.25 GiB	2.4 GHz 2,400 MHz 2,400,000 kHz	3.3 GHz 3,300 MHz 3,300,000 kHz
7542	EPYC	7 August 2019	32	64	225 W 225,000 mW 0.302 hp 0.225 kW	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	2.9 GHz 2,900 MHz 2,900,000 kHz	3.4 GHz 3,400 MHz 3,400,000 kHz
7552	EPYC	7 August 2019	48	96	200 W 200,000 mW 0.268 hp 0.2 kW	24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB	192 MiB 196,608 KiB 201,326,592 B 0.188 GiB	2.2 GHz 2,200 MHz 2,200,000 kHz	3.35 GHz 3,350 MHz 3,350,000 kHz
7642	EPYC	7 August 2019	48	96	225 W 225,000 mW 0.302 hp 0.225 kW	24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB	256 MiB 262,144 KiB 268,435,456 B 0.25 GiB	2.3 GHz 2,300 MHz 2,300,000 kHz	3.3 GHz 3,300 MHz 3,300,000 kHz
7662	EPYC	19 February 2020	64	128	225 W 225,000 mW 0.302 hp 0.225 kW	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	256 MiB 262,144 KiB 268,435,456 B 0.25 GiB	2 GHz 2,000 MHz 2,000,000 kHz	3.3 GHz 3,300 MHz 3,300,000 kHz
7702	EPYC	7 August 2019	64	128	200 W 200,000 mW 0.268 hp 0.2 kW	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	256 MiB 262,144 KiB 268,435,456 B 0.25 GiB	2 GHz 2,000 MHz 2,000,000 kHz	3.35 GHz 3,350 MHz 3,350,000 kHz
7702P	EPYC	7 August 2019	64	128	200 W 200,000 mW 0.268 hp 0.2 kW	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	256 MiB 262,144 KiB 268,435,456 B 0.25 GiB	2 GHz 2,000 MHz 2,000,000 kHz	3.35 GHz 3,350 MHz 3,350,000 kHz
7742	EPYC	7 August 2019	64	128	225 W 225,000 mW 0.302 hp 0.225 kW	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	256 MiB 262,144 KiB 268,435,456 B 0.25 GiB	2.25 GHz 2,250 MHz 2,250,000 kHz	3.4 GHz 3,400 MHz 3,400,000 kHz
7F32	EPYC	14 April 2020	8	16	180 W 180,000 mW 0.241 hp 0.18 kW	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	3.7 GHz 3,700 MHz 3,700,000 kHz	3.9 GHz 3,900 MHz 3,900,000 kHz
7F52	EPYC	14 April 2020	16	32	240 W 240,000 mW 0.322 hp 0.24 kW	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	256 MiB 262,144 KiB 268,435,456 B 0.25 GiB	3.5 GHz 3,500 MHz 3,500,000 kHz	3.9 GHz 3,900 MHz 3,900,000 kHz
7F72	EPYC	14 April 2020	24	48	240 W 240,000 mW 0.322 hp 0.24 kW	12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB	192 MiB 196,608 KiB 201,326,592 B 0.188 GiB	3.2 GHz 3,200 MHz 3,200,000 kHz	3.7 GHz 3,700 MHz 3,700,000 kHz
7H12	EPYC	18 September 2019	64	128	280 W 280,000 mW 0.375 hp 0.28 kW	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	256 MiB 262,144 KiB 268,435,456 B 0.25 GiB	2.6 GHz 2,600 MHz 2,600,000 kHz	3.3 GHz 3,300 MHz 3,300,000 kHz
Count: 25

SKU Comparison

Below are a number of SKU comparison graphs based on their specifications.

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@@ Line 25: / Line 25: @@
 == Overview ==
-AMD Rome [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture. Rome SoCs support both single and 2-way multiprocessing with up to a maximum of 64 cores (and 128 threads) per processor for a total of up to 128 cores (and 256 threads) for a 2-way MP system. Those SoCs support 128 PCIe lanes each. Rome is backwards platform/socket compatible with Naples and forward-compatible with Milan.
+AMD Rome [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture. Rome SoCs support both single and 2-way multiprocessing with up to a maximum of 64 cores (and 128 threads) per processor for a total of up to 128 cores (and 256 threads) for a 2-way MP system. Those SoCs support 128 PCIe lanes each. Rome is backward platform/socket (Socket SP3) compatible with {{\\|Naples}} and forward-compatible with {{\\|Milan}}.
 === Common Features ===

designer	AMD +
first announced	May 16, 2017 +
first launched	August 7, 2019 +
instance of	core +
isa	x86-64 +
manufacturer	TSMC + and GlobalFoundries +
microarchitecture	Zen 2 +
name	Rome +
package	SP3 + and FCLGA-4094 +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
socket	SP3 + and LGA-4094 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +

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