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− | {{intel title| | + | {{intel title|Cannon Lake|arch}} |
{{microarchitecture | {{microarchitecture | ||
− | | atype | + | |atype=CPU |
− | | name | + | |name=Cannon Lake |
− | | designer | + | |designer=Intel |
− | | manufacturer | + | |manufacturer=Intel |
− | | introduction | + | |introduction=May 15, 2018 |
− | | | + | |process=10 nm |
− | | | + | |cores=2 |
+ | |type=Superscalar | ||
+ | |oooe=Yes | ||
+ | |speculative=Yes | ||
+ | |renaming=Yes | ||
+ | |stages min=14 | ||
+ | |stages max=19 | ||
+ | |decode=5-way? | ||
+ | |isa=x86-64 | ||
+ | |extension=MOVBE | ||
+ | |extension 2=MMX | ||
+ | |extension 3=SSE | ||
+ | |extension 4=SSE2 | ||
+ | |extension 5=SSE3 | ||
+ | |extension 6=SSSE3 | ||
+ | |extension 7=SSE4.1 | ||
+ | |extension 8=SSE4.2 | ||
+ | |extension 9=POPCNT | ||
+ | |extension 10=AVX | ||
+ | |extension 11=AVX2 | ||
+ | |extension 12=AES | ||
+ | |extension 13=PCLMUL | ||
+ | |extension 14=FSGSBASE | ||
+ | |extension 15=RDRND | ||
+ | |extension 16=FMA3 | ||
+ | |extension 17=F16C | ||
+ | |extension 18=BMI | ||
+ | |extension 19=BMI2 | ||
+ | |extension 20=VT-x | ||
+ | |extension 21=VT-d | ||
+ | |extension 22=TXT | ||
+ | |extension 23=TSX | ||
+ | |extension 24=RDSEED | ||
+ | |extension 25=ADCX | ||
+ | |extension 26=PREFETCHW | ||
+ | |extension 27=CLFLUSHOPT | ||
+ | |extension 28=XSAVE | ||
+ | |extension 29=SGX | ||
+ | |extension 30=MPX | ||
+ | |extension 31=AVX-512 | ||
+ | |extension 32=AVX-512F | ||
+ | |extension 33=AVX-512CD | ||
+ | |extension 34=AVX-512BW | ||
+ | |extension 35=AVX-512DQ | ||
+ | |extension 36=AVX-512VL | ||
+ | |extension 37=AVX-512IFMA | ||
+ | |extension 38=AVX-512VBMI | ||
+ | |extension 39=SHA | ||
+ | |extension 40=UMIP | ||
+ | |l1i=32 KiB | ||
+ | |l1i per=core | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d=32 KiB | ||
+ | |l1d per=core | ||
+ | |l1d desc=8-way set associative | ||
+ | |l2=256 KiB | ||
+ | |l2 per=core | ||
+ | |l2 desc=4-way set associative | ||
+ | |l3=2 MiB | ||
+ | |l3 per=core | ||
+ | |l3 desc=Up to 16-way set associative | ||
+ | |core name 2=Cannon Lake Y | ||
+ | |predecessor=Kaby Lake | ||
+ | |predecessor link=intel/microarchitectures/kaby lake | ||
+ | |successor=Ice Lake | ||
+ | |successor link=intel/microarchitectures/ice lake (client) | ||
+ | |contemporary=Coffee Lake | ||
+ | |contemporary link=intel/microarchitectures/coffee lake | ||
+ | |core names=Yes | ||
+ | |succession=Yes | ||
+ | }} | ||
+ | '''Cannon Lake''' ('''CNL''') (formerly '''Skymont''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannon Lake is expected to be fabricated using a [[10 nm process]] and is set to be introduced in the second half of [[2018]]. Cannon Lake is the "Process" microarchitecture as part of Intel's {{intel|PAO}} model. | ||
− | | | + | For mobile, Cannon Lake is expected to be branded as 8th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. |
− | | | ||
− | | | ||
− | |||
− | |||
− | |||
− | |||
− | + | == Codenames == | |
− | | | + | {| class="wikitable" |
− | | | + | |- |
− | | | + | ! Core !! Abbrev !! Description !! Graphics !! Target |
− | | | + | |- |
− | }} | + | | {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
− | + | |} | |
− | + | == Release Dates == | |
+ | Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year. | ||
== Process Technology == | == Process Technology == | ||
− | + | Cannon Lake is manufactured on Intel's [[10 nm process]] (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ [[Self-Aligned Quad Patterning]] (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² [[SRAM]] bit cell. | |
[[Scaling]]: | [[Scaling]]: | ||
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{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! !! Broadwell !! | + | ! !! Broadwell !! Cannon<br>Lake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]] |
|- | |- | ||
| || [[14 nm]] || [[10 nm]] || | | || [[14 nm]] || [[10 nm]] || | ||
|- | |- | ||
− | | Fin Pitch || 42 nm || 34 || 0.81x | + | | Fin Pitch || 42 nm || 34 nm || 0.81x |
|- | |- | ||
− | | Fin Width || 8 nm || | + | | Fin Width || 8 nm || 7 nm || 0.88x |
|- | |- | ||
− | | Fin Height || 42 nm || 53 nm || 1.24x | + | | Fin Height || 42 nm || 53 nm || 1.24x |
|- | |- | ||
− | | Gate Pitch || 70 nm || 54 nm || 0.77x | + | | Gate Pitch || 70 nm || 54 nm || 0.77x |
|- | |- | ||
− | | Interconnect Pitch || 52 nm || 36 nm || 0.69x | + | | Interconnect Pitch || 52 nm || 36 nm || 0.69x |
|- | |- | ||
| Cell Height || 399 nm || 272 nm || 0.68x | | Cell Height || 399 nm || 272 nm || 0.68x | ||
|} | |} | ||
− | == | + | == Compiler support == |
+ | Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0. | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Core !! | + | ! Compiler !! Arch-Specific || Arch-Favorable |
+ | |- | ||
+ | | [[ICC]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code> | ||
+ | |- | ||
+ | | [[GCC]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code> | ||
+ | |- | ||
+ | | [[LLVM]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code> | ||
+ | |- | ||
+ | | [[Visual Studio]] || <code>?</code> || <code>?</code> | ||
+ | |} | ||
+ | |||
+ | === CPUID === | ||
+ | {| class="wikitable tc1 tc2 tc3 tc4" | ||
+ | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ||
|- | |- | ||
− | | | + | | rowspan="2" | {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6 |
|- | |- | ||
− | | | + | | colspan="4" | Family 6 Model 102 |
|} | |} | ||
== Architecture == | == Architecture == | ||
− | + | === Key changes from {{\\|Skylake (client)|Skylake}} === | |
− | === Key changes from {{\\| | ||
* [[10 nm process]] (from [[14 nm]]) | * [[10 nm process]] (from [[14 nm]]) | ||
+ | |||
+ | * {{\\|Palm Cove|Palm Cove core}} (from {{\\|Skylake (client)|Skylake}}) | ||
+ | ** ''See {{\\|Palm Cove}} for microarchitectural details and changes'' | ||
+ | |||
+ | * Mainstream chipset | ||
+ | ** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}} | ||
+ | |||
+ | * Mobile Processors | ||
+ | ** LPDDR4/LPDDR4X memory support (from LPDDR3) | ||
+ | *** Rates up to 2400 MT/s | ||
+ | |||
* {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics | * {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics | ||
− | + | * {{intel|Gen10|l=arch}} GPUs | |
− | + | ** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}}) | |
− | ** | + | ** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}}) |
− | *** | + | |
− | ** | + | * New Integration |
+ | ** New Gaussian Neural Accelerator 1.0 (Unclear to what extent) | ||
+ | |||
+ | ====New instructions ==== | ||
+ | Cannon Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|palm cove#New instructions|Palm Cove § New Instructions|l=arch}} for details. | ||
+ | |||
+ | === Block Diagram === | ||
+ | |||
+ | ==== Entire SoC Overview ==== | ||
+ | [[File:cannon lake soc block diagram.svg|800px]] | ||
+ | |||
+ | ==== Individual Core ==== | ||
+ | See {{intel|Palm Cove#Block Diagram|Palm Cove § Block Diagram|l=arch}}. | ||
+ | |||
+ | ==== Gen11 Graphics ==== | ||
+ | See {{intel|Gen10#Block Diagram|Gen10 Graphics § Block Diagram|l=arch}}. | ||
+ | |||
+ | == Die == | ||
+ | === Dual-core === | ||
+ | * [[10 nm process]] | ||
+ | * [[13 metal layers]] | ||
+ | * ~8.2 mm x ~8.6 mm | ||
+ | * ~70.52 mm² die size | ||
+ | * 2 CPU cores + 40 GPU EUs | ||
− | == All | + | == All Cannon Lake Chips == |
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{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc4 tc5 tc6"> |
− | + | {{comp table header|main|7:List of Cannon Lake-based Processors}} | |
− | + | {{comp table header|cols|Price|Launched|Cores|Threads|TDP|%Frequency|%Turbo}} | |
− | + | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]] | |
− | |||
− | {{#ask: [[Category:microprocessor models by intel | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
+ | |?release price | ||
|?first launched | |?first launched | ||
− | |||
− | |||
− | |||
− | |||
|?core count | |?core count | ||
|?thread count | |?thread count | ||
− | |||
− | |||
|?tdp | |?tdp | ||
|?base frequency#GHz | |?base frequency#GHz | ||
|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
− | |||
− | |||
− | |||
− | |||
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|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | + | |userparam=9 | |
− | |||
− | |||
− | |userparam= | ||
|mainlabel=- | |mainlabel=- | ||
− | |||
}} | }} | ||
− | + | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]}} | |
− | {{comp table count|ask=[[Category:microprocessor models by intel | ||
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
+ | |||
+ | == References == | ||
+ | * Some information was obtained directly from Intel. | ||
+ | * Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | ||
== See also == | == See also == | ||
* AMD's {{amd|Zen|l=arch}} | * AMD's {{amd|Zen|l=arch}} |
Latest revision as of 12:53, 5 August 2019
Edit Values | |
Cannon Lake µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | May 15, 2018 |
Process | 10 nm |
Core Configs | 2 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14-19 |
Decode | 5-way? |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512, AVX-512F, AVX-512CD, AVX-512BW, AVX-512DQ, AVX-512VL, AVX-512IFMA, AVX-512VBMI, SHA, UMIP |
Cache | |
L1I Cache | 32 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L2 Cache | 256 KiB/core 4-way set associative |
L3 Cache | 2 MiB/core Up to 16-way set associative |
Succession | |
Contemporary | |
Coffee Lake |
Cannon Lake (CNL) (formerly Skymont) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannon Lake is expected to be fabricated using a 10 nm process and is set to be introduced in the second half of 2018. Cannon Lake is the "Process" microarchitecture as part of Intel's PAO model.
For mobile, Cannon Lake is expected to be branded as 8th Generation Intel Core i3, Core i5. and Core i7 processors.
Contents
Codenames[edit]
Core | Abbrev | Description | Graphics | Target |
---|---|---|---|---|
Cannon Lake U | CNL-U | Ultra-low Power | GT2/GT3 | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
Release Dates[edit]
Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year.
Process Technology[edit]
Cannon Lake is manufactured on Intel's 10 nm process (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ Self-Aligned Quad Patterning (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² SRAM bit cell.
Broadwell | Cannon Lake |
Δ | ![]() | |
---|---|---|---|---|
14 nm | 10 nm | |||
Fin Pitch | 42 nm | 34 nm | 0.81x | |
Fin Width | 8 nm | 7 nm | 0.88x | |
Fin Height | 42 nm | 53 nm | 1.24x | |
Gate Pitch | 70 nm | 54 nm | 0.77x | |
Interconnect Pitch | 52 nm | 36 nm | 0.69x | |
Cell Height | 399 nm | 272 nm | 0.68x |
Compiler support[edit]
Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0.
Compiler | Arch-Specific | Arch-Favorable |
---|---|---|
ICC | -march=cannonlake |
-mtune=cannonlake
|
GCC | -march=cannonlake |
-mtune=cannonlake
|
LLVM | -march=cannonlake |
-mtune=cannonlake
|
Visual Studio | ? |
?
|
CPUID[edit]
Core | Extended Family |
Family | Extended Model |
Model |
---|---|---|---|---|
U | 0 | 0x6 | 0x6 | 0x6 |
Family 6 Model 102 |
Architecture[edit]
Key changes from Skylake[edit]
- 10 nm process (from 14 nm)
- Palm Cove core (from Skylake)
- See Palm Cove for microarchitectural details and changes
- Mainstream chipset
- Mobile Processors
- LPDDR4/LPDDR4X memory support (from LPDDR3)
- Rates up to 2400 MT/s
- LPDDR4/LPDDR4X memory support (from LPDDR3)
- New Integration
- New Gaussian Neural Accelerator 1.0 (Unclear to what extent)
New instructions[edit]
Cannon Lake introduced a number of new instructions. See Palm Cove § New Instructions for details.
Block Diagram[edit]
Entire SoC Overview[edit]
Individual Core[edit]
See Palm Cove § Block Diagram.
Gen11 Graphics[edit]
See Gen10 Graphics § Block Diagram.
Die[edit]
Dual-core[edit]
- 10 nm process
- 13 metal layers
- ~8.2 mm x ~8.6 mm
- ~70.52 mm² die size
- 2 CPU cores + 40 GPU EUs
All Cannon Lake Chips[edit]
References[edit]
- Some information was obtained directly from Intel.
- Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
See also[edit]
- AMD's Zen
codename | Cannon Lake + |
core count | 2 + |
designer | Intel + |
first launched | May 15, 2018 + |
full page name | intel/microarchitectures/cannon lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cannon Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |