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|manufacturer=TSMC
 
|manufacturer=TSMC
 
|introduction=October 19, 2011
 
|introduction=October 19, 2011
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|process=40 nm
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|process 2=28 nm
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|isa=ARMv7
 
|predecessor=Cortex-A9
 
|predecessor=Cortex-A9
 
|predecessor link=arm_holdings/microarchitectures/cortex-a9
 
|predecessor link=arm_holdings/microarchitectures/cortex-a9
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|successor link=arm_holdings/microarchitectures/cortex-a53
 
|successor link=arm_holdings/microarchitectures/cortex-a53
 
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'''Cortex-A7''' is the successor to the {{armh|Cortex-A9|l=arch}}, a high efficiency [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A7 was introduced along with the {{armh|big.LITTLE}} technology so that it could be integrated along with the a higher-performance core such as the {{\\|Cortex-A15}} for better energy and power efficiency.
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'''Cortex-A7''' (codename '''Kingfisher''') is the successor to the {{armh|Cortex-A9|l=arch}}, a high efficiency [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A7 was introduced along with the {{armh|big.LITTLE}} technology so that it could be integrated along with the a higher-performance core such as the {{\\|Cortex-A15}} or the {{\\|Cortex-A17}} for better energy and power efficiency.
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== Architecture ==
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=== Key changes from {{\\|Cortex-A9}} ===
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* [[28 nm process]] (from [[40 nm]])
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* New [[in-order]] pipeline (form [[out-of-order]])
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** Shorter [[pipeline]] (8, down from 9-12)
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*** 0.5x frequency (1 GHz, down from 2 GHz)
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* Integer
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** Hardware [[division]] support
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** Hardware [[Fused Multiply-Accumulate]]
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* [[VFPv4]] (from [[VFPv3]])
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* [[NEONv2]] (from [[NEON]])
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* Memory subsystem
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** Level 1 [[instruction cache]] reduced to 2-way set associative (down from 4-way)
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** Added {{arm|LPAE}} support
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{{expand list}}
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 +
=== Block Diagram ===
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{{empty section}}
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=== Memory Hierarchy ===
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{{empty section}}
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== Licensees ==
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Arm named the following companies as licensees.
 +
 
 +
{{collist
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|count = 3
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|
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* [[Broadcom]]
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* [[Freescale]]
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* [[Fujitsu]]
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* [[HiSilicon]]
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* [[LGE]]
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* [[Samsung]]
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* [[STEricsson]]
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* [[Texas Instruments]]
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}}
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== Die ==
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=== MediaTek [[MT6595]] ===
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* TSMC [[28 nm process]]
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* 89 mm² die size
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* Quad-core Cortex-A7
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** ~0.48 mm² per core
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* Quad-core {{\\|Cortex-A17}} + 2 MiB L2
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** ~1.93 mm² per core
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** ~3.93 mm² for 2 MiB L2
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(small quad-core is unlabeled below the big core cluster)
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:[[File:mt6595 die shot.png|600px]]
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== Bibliography ==
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* Mair, Hugh, et al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015.

Latest revision as of 13:24, 31 December 2018

Edit Values
Cortex-A7 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionOctober 19, 2011
Process40 nm, 28 nm
Instructions
ISAARMv7
Succession

Cortex-A7 (codename Kingfisher) is the successor to the Cortex-A9, a high efficiency ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A7 was introduced along with the big.LITTLE technology so that it could be integrated along with the a higher-performance core such as the Cortex-A15 or the Cortex-A17 for better energy and power efficiency.

Architecture[edit]

Key changes from Cortex-A9[edit]

This list is incomplete; you can help by expanding it.

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Licensees[edit]

Arm named the following companies as licensees.

Die[edit]

MediaTek MT6595[edit]

  • TSMC 28 nm process
  • 89 mm² die size
  • Quad-core Cortex-A7
    • ~0.48 mm² per core
  • Quad-core Cortex-A17 + 2 MiB L2
    • ~1.93 mm² per core
    • ~3.93 mm² for 2 MiB L2

(small quad-core is unlabeled below the big core cluster)

mt6595 die shot.png

Bibliography[edit]

  • Mair, Hugh, et al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015.
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Facts about "Cortex-A7 - Microarchitectures - ARM"
RDF feed
codenameCortex-A7 +
designerARM Holdings +
first launchedOctober 19, 2011 +
full page namearm holdings/microarchitectures/cortex-a7 +
instance ofmicroarchitecture +
instruction set architectureARMv7 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A7 +
process40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) +