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MT6595
General Info
Designer	MediaTek, ARM Holdings
Manufacturer	TSMC
Model Number	MT6595
Part Number	MT6595
Market	Mobile
Introduction	Februray 11, 2014 (announced) Februray 11, 2014 (launched)
General Specs
Family	MT65xx
Frequency	2,500 MHz, 1,700 MHz
Microarchitecture
ISA	ARMv7 (ARM)
Microarchitecture	Cortex-A17, Cortex-A7
Core Name	Cortex-A17, Cortex-A7
Process	28 nm
Technology	CMOS
Die	89 mm²
Word Size	64 bit
Cores	8
Threads	8
Multiprocessing
Max SMP	1-Way (Uniprocessor)

MT6595 is a mid-range octa-core ARM LTE SoC designed by MediaTek and introduced in early 2014. This chip, which is fabricated on TSMC's 28 nm process, features four big Cortex-A17 cores operating at up to 2.5 GHz and four little Cortex-A7 cores operating at up to 1.7 GHz. The MT6595 incorporates an PowerVR G6200 GPU operating at up to 600 MHz and supports up to dual-channel LPDDR3-1866 memory.

Cache

Main article: Cortex-A7 § Cache

Cortex-A7 Cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1x512 KiB

Cortex-A17 Cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR3-1866 Supports ECC No Controllers 1 Channels 2

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR G6200 Designer Imagination Technologies Frequency 600 MHz 0.6 GHz 600,000 KHz Output DSI Max Resolution DSI 2560x1600 Standards Direct3D 10.0 OpenGL 3.2 OpenCL 1.2 OpenGL ES 3.1 Vulkan 1.0

• Encoding H.265
• Playback H.264, H.265 / HEVC, VP-9

Camera

• Image signal processor
  • 20 Mpixel

Connectivity

• UE Cat-4
• EDGE, FDD / TDD LTE, HSPA +, TD-SCDMA
• Bluetooth
• Wi-Fi
  • a/b/g/n/ac

Location

• GNSS
  • GPS, Glonass, Beidou, Galileo

Utilizing devices

• Gionee P7 Max
• InFocus M530
• Zopo ZP999
• Meizu MX4

This list is incomplete; you can help by expanding it.

Die

• TSMC 28 nm process
• 89 mm² die size
• Quad-core Cortex-A7
  • ~0.48 mm² per core
• Quad-core Cortex-A17 + 2 MiB L2
  • ~1.93 mm² per core
  • ~3.93 mm² for 2 MiB L2

(small quad-core is unlabeled below the big core cluster)

Bibliography

• Mair, Hugh, et al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015.