Difference between revisions of "intel/process"

Revision as of 11:03, 11 May 2017

This article details details Intel's Semiconductor Process Technology history. The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. SRAM bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used.

Timeline

1 µm vs 500 nm yield

Ramps from 1 µm to 65 nm

SRAM test chips from 130 nm to 45 nm

Intel's fab roadmap from 2003. Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics.

65 nm to 32 nm SRAM scaling

Year	Process	Node	MLayers	µarchs
	CHMOS I	3 µm	1	8085, 8086, 8088, 80186	T_ox	70 nm	Gate Dielectric
					V_dd	5 V	SRAM	1120 µm²
					L_g	3.0 µm
					CPP	7 µm	MMP	11 µm
	CHMOS II	2 µm	1		T_ox	40 nm	Gate Dielectric
					V_dd	5 V	SRAM	1740 µm²
					L_g	2.0 µm
					CPP	5.6 µm	MMP	8 µm
1982	P646 (CHMOS III)	1.5 µm	1	80286, 80386	T_ox	25 nm	Gate Dielectric	Si₂N₂O
					V_dd	5 V	SRAM	951.7 µm²
					L_g	1.5 µm
					CPP	4.0 µm	MMP	6.4 µm
1987	P648	1.0 µm	2	80486	T_ox		Gate Dielectric
					V_dd	5 V	SRAM
					L_g	1,000 µm
					CPP		MMP
1989	P650	0.8 µm	3	80486	T_ox	15 nm	Gate Dielectric
					V_dd	5 V	SRAM	111 µm²
					L_g	800 µm
					CPP	1.7 µm	MMP	2 µm
1991		0.6 µm	4	80486, P5	T_ox	8 nm	Gate Dielectric
					V_dd	3.3 V	SRAM
					L_g	600 µm
					CPP		MMP	1.4 µm
1993	P852	0.5 µm	4	P5	L_g	500 nm
					T_ox	8.0 nm	Gate Dielectric
					V_dd	3.3 V
1995	P854	0.35 µm	4	P6	T_ox	6 nm	Gate Dielectric	SiO₂
					V_dd	2.5 V	SRAM	20.5 µm²
					L_g	350 nm
					CPP	920 nm	MMP	880 nm
1997	P856	0.25 µm	5	P6	T_ox	4.08 nm	Gate Dielectric	SiO₂
					V_dd	1.8 V	SRAM	10.26 µm²
					L_g	200 nm
					CPP	500 nm	MMP	640 nm
1998	P856.5	0.25 µm	5	P6	T_ox	4.08 nm	Gate Dielectric	SiO₂
					V_dd	1.8 V	SRAM	9.26 µm²
					L_g	200 nm
					CPP	475 nm	MMP	608 nm
1999	P858	0.18 µm	6	NetBurst	T_ox	2.0 nm	Gate Dielectric	SiO₂
					V_dd	1.6 V	SRAM	5.59 µm²
					L_g	130 nm
					CPP	480 nm	MMP	500 nm
2001	P860	0.13 µm	6	Pentium M	T_ox	1.4 nm	Gate Dielectric	SiO₂
					V_dd	1.4 V	SRAM	2.45 µm²
					L_g	70 nm
					CPP	336 nm	MMP	345 nm
2003	P1262	90 nm	7	Pentium M	T_ox	1.2 nm	Gate Dielectric	SiO₂
					V_dd	1.2 V	SRAM	1.00 µm²
					L_g	50 nm
					CPP	260 nm	MMP	220 nm
2005	P1264	65 nm	8	Core, Modified Pentium M	T_ox		Gate Dielectric	SiO₂
					V_dd		SRAM	0.570 µm²
					L_g	35 nm
					CPP	220 nm	MMP	210 nm
2007	P1266	45 nm	9	Penryn, Nehalem	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.346 µm²
					L_g	25 nm
					CPP	160 nm	MMP	180 nm
2009	P1268	32 nm	10	Westmere, Sandy Bridge	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.148 µm²
					L_g	30 nm
					CPP	112.5 nm	MMP	112.5 nm
2011	P1270	22 nm	11	Ivy Bridge, Haswell	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.092 µm²
					L_g	26 nm
					CPP	90 nm	MMP	80 nm
2014	P1272	14 nm	11	Broadwell, Skylake, Kaby Lake, Coffee Lake	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.0499 µm²
					L_g	20 nm
					CPP	70 nm	MMP	52 nm
2017	P1274	10 nm		Cannonlake, Icelake, Tigerlake	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.0312 µm²
					L_g	18 nm ?
					CPP	54 nm	MMP	36 nm
2019	P1276	7 nm
2022	P1278	5 nm

@@ Line 12: / Line 12: @@
 <tr><th>Year</th><th>Process</th><th>Node</th><th>MLayers</th><th>µarchs</th><th>Transistor</th><th colspan="4">Attributes</th></tr>
 {{intel proc tech |year= |name=CHMOS I |mlayers=1 |node=3 µm
-   |archs=
+   |archs=8085, 8086, 8088, 80186
    |a1=T<sub>ox</sub> |d1=70 nm     |a12=Gate Dielectric |d12=
    |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22= 1120 µm²
@@ Line 34: / Line 34: @@
 {{intel proc tech |year=1987 |name=P648 |mlayers=2 |node=1.0 µm
    |archs=80486
-   |a1=L<sub>g</sub>  |d1=1,000 nm
+   |a1=T<sub>ox</sub> |d1=     |a12=Gate Dielectric |d12=
-   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=
+   |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22=
-   |a3=V<sub>dd</sub> |d3=? V
+   |a3=L<sub>g</sub>  |d3=1,000 µm
+  |a4=CPP            |d4=    |a42=MMP             |d42=
 }}
 {{intel proc tech |year=1989 |name=P650 |mlayers=3 |node=0.8 µm
    |archs=80486
-   |a1=L<sub>g</sub>  |d1=800 nm
+   |a1=T<sub>ox</sub> |d1=15 nm     |a12=Gate Dielectric |d12=
-   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=
+  |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22=111 µm²
-   |a3=V<sub>dd</sub> |d3=? V
+  |a3=L<sub>g</sub>  |d3=800 µm
+  |a4=CPP            |d4=1.7 µm    |a42=MMP             |d42=2 µm
+}}
+{{intel proc tech |year=1991 |name= |mlayers=4 |node=0.6 µm
+  |archs=80486, P5
+   |a1=T<sub>ox</sub> |d1=8 nm      |a12=Gate Dielectric |d12=
+  |a2=V<sub>dd</sub> |d2=3.3 V     |a22=SRAM            |d22=
+   |a3=L<sub>g</sub>  |d3=600 µm
+  |a4=CPP            |d4=          |a42=MMP             |d42=1.4 µm
 }}
 {{intel proc tech |year=1993 |name=P852 |mlayers=4 |node=0.5 µm
@@ Line 52: / Line 61: @@
 {{intel proc tech |year=1995 |name=P854 |mlayers=4 |node=0.35 µm
    |archs=P6
-   |a1=L<sub>g</sub>  |d1=350 nm
+   |a1=T<sub>ox</sub> |d1=6 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
-   |a2=T<sub>ox</sub> |d2=5.2 nm |a22=Gate Dielectric |d22=
+  |a2=V<sub>dd</sub> |d2=2.5 V      |a22=SRAM            |d22=20.5 µm²
-   |a3=V<sub>dd</sub> |d3=2.5 V
+  |a3=L<sub>g</sub>  |d3=350 nm
+   |a4=CPP            |d4=920 nm     |a42=MMP             |d42=880 nm
+}}
+{{intel proc tech |year=1997 |name=P856 |mlayers=5 |node=0.25 µm
+  |archs=P6
+  |a1=T<sub>ox</sub> |d1=4.08 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
+   |a2=V<sub>dd</sub> |d2=1.8 V      |a22=SRAM            |d22=10.26 µm²
+  |a3=L<sub>g</sub>  |d3=200 nm
+  |a4=CPP            |d4=500 nm     |a42=MMP             |d42=640 nm
 }}
-{{intel proc tech |year=1997 |name=P856<br>P856.5 |mlayers=5 |node=0.25 µm
+{{intel proc tech |year=1998 |name=P856.5 |mlayers=5 |node=0.25 µm
    |archs=P6
-   |a1=L<sub>g</sub>  |d1=200 nm
+   |a1=T<sub>ox</sub> |d1=4.08 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
-   |a2=T<sub>ox</sub> |d2=3.1 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
+   |a2=V<sub>dd</sub> |d2=1.8 V      |a22=SRAM            |d22=9.26 µm²
-   |a3=V<sub>dd</sub> |d3=1.8 V
+   |a3=L<sub>g</sub>  |d3=200 nm
+  |a4=CPP            |d4=475 nm     |a42=MMP             |d42=608 nm
 }}
 {{intel proc tech |year=1999 |name=P858 |mlayers=6 |node=0.18 µm
    |archs=NetBurst

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Revision as of 11:03, 11 May 2017

Timeline