From WikiChip
Difference between revisions of "arm holdings/microarchitectures/hayes"
< arm holdings

(fixed)
(add tables)
 
Line 2: Line 2:
 
{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
−
|name=Cortex-A520
+
|name=Cortex-A520 (Hayes)
 
|designer=ARM Holdings
 
|designer=ARM Holdings
 
|manufacturer=TSMC
 
|manufacturer=TSMC
−
|manufacturer 2=
 
 
|introduction=Q4 2023
 
|introduction=Q4 2023
 
|process=4 nm
 
|process=4 nm
−
|process 2=
 
−
|process 3=
 
 
|cores=4
 
|cores=4
 
|cores 2=
 
|cores 2=
Line 35: Line 32:
 
|l3=256 KiB-32 MiB
 
|l3=256 KiB-32 MiB
 
|l3 desc=(optional)
 
|l3 desc=(optional)
−
|predecessor=Cortex-A510
+
|predecessor=Cortex-A510 (Klein)
 
|predecessor link=arm_holdings/microarchitectures/cortex-a510
 
|predecessor link=arm_holdings/microarchitectures/cortex-a510
−
|successor=Cortex-A530
+
|successor=Cortex-A530 (Nevis)
 
|successor link=arm_holdings/microarchitectures/cortex-a530
 
|successor link=arm_holdings/microarchitectures/cortex-a530
−
|successor 2=Cortex-A520AE
 
−
|successor 2 link=arm_holdings/microarchitectures/cortex-a520ae
 
 
}}
 
}}
−
'''Cortex-A520''' (codename '''Hayes''') is a planned ultra-high efficiency {{armh|Cortex}} [[microarchitecture]] being designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A510|l=arch}}. Cortex-A520 is scheduled for introduction around the 2023 timeframe.
+
'''Cortex-A520''' ''({{armh|Hayes|l=arch}})'' is a planned ultra-high efficiency {{armh|Cortex}} [[microarchitecture]] being designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A510|l=arch}} ''(Klein)''. Cortex-A520 is scheduled for introduction around the [[2023]] timeframe.
  
 
=== Process Technology ===
 
=== Process Technology ===
Line 48: Line 43:
 
<!--[[N7|7 nm]], [[N6|6 nm]], [[N5|5 nm]] as well as Samsung's [[7LPP|7 nm]] and [[5LPP|5 nm]]-->
 
<!--[[N7|7 nm]], [[N6|6 nm]], [[N5|5 nm]] as well as Samsung's [[7LPP|7 nm]] and [[5LPP|5 nm]]-->
  
 +
== Architecture ==
 
=== Key changes from {{\\|Cortex-A510}} ===
 
=== Key changes from {{\\|Cortex-A510}} ===
−
* Update to ARMv9.2-A <ref>{{cite web |title=Cortex-A520 |url=https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a520 |access-date=2023-06-05 |website=Arm {{!}} The Architecture for the Digital World }}</ref>
+
* Update to ARMv9.2-A <ref>{{cite book |title=Cortex-A520 |url=https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a520 |website=ARM }}</ref>
 
* Support only 64-bit applications
 
* Support only 64-bit applications
 
* Up to 512 KiB of private L2 cache (from 256 KiB)
 
* Up to 512 KiB of private L2 cache (from 256 KiB)
−
* 8% peak performance improvement over the Cortex-A510 <ref>{{cite web |title=Arm Unveils 2023 Mobile CPU Core Designs: Cortex-X4, A720, and A520 - the ARMv9.2 Family |url=https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive |access-date=2023-06-05 |website=www.anandtech.com }}</ref>
+
* 8% peak performance improvement over the Cortex-A510 <ref>{{cite book |title=Arm Unveils 2023 Mobile CPU Core Designs: Cortex-X4, A720, and A520 - ARMv9.2 Family |url=https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive |website=anandtech.com }}</ref>
 
* Add QARMA3 Pointer Authentication (PAC) algorithm support
 
* Add QARMA3 Pointer Authentication (PAC) algorithm support
  
−
== Architecture comparison ==
+
== Comparison ==
 
{| class="wikitable" style="text-align: center;
 
{| class="wikitable" style="text-align: center;
 
|-
 
|-
Line 120: Line 116:
 
|
 
|
 
|
 
|
 +
|-
 +
|}
 +
 +
=== [[Cortex]]-X/-A Core ===
 +
:;[[ARM]] • [[Cortex]] • [[arm/microarchitectures|Microarchitectures]]
 +
{| class="wikitable" style="text-align: center;
 +
|-
 +
! Year !! Cortex-X Core !! Cortex-A Core
 +
|-
 +
| [[2020]] || {{armh|Cortex-X1|l=arch}} (''{{armh|Hera|l=arch}}'') <br>{{armh|Cortex-X1C|l=arch}} (''{{armh|Hera-C|l=arch}}'') || {{armh|Cortex-A78|l=arch}} (''{{armh|Hercules|l=arch}}'') <!--<br>{{armh|Cortex-A78AE|l=arch}} (''{{armh|Hercules-AE|l=arch}}'')--> <br>{{armh|Cortex-A78C|l=arch}} (''{{armh|Hera Prime|l=arch}}'')
 +
|-
 +
| [[2021]] || {{armh|Cortex-X2|l=arch}} <br>(''{{armh|Matterhorn-ELP|l=arch}}'') || {{armh|Cortex-A710|l=arch}} (''{{armh|Matterhorn|l=arch}}'') <br>{{armh|Cortex-A510|l=arch}} (''{{armh|Klein|l=arch}}'')
 +
|-
 +
| [[2022]] || {{armh|Cortex-X3|l=arch}} (''{{armh|Makalu-ELP|l=arch}}'') || {{armh|Cortex-A715|l=arch}} (''{{armh|Makalu|l=arch}}'')
 +
|-
 +
| [[2023]] || {{armh|Cortex-X4|l=arch}} (''{{armh|Hunter-ELP|l=arch}}'') || {{armh|Cortex-A720|l=arch}} (''{{armh|Hunter|l=arch}}'') <br>{{armh|Cortex-A520|l=arch}} (''{{armh|Hayes|l=arch}}'')
 +
|-
 +
| [[2024]] || <s>{{armh|Cortex-X5|l=arch}} (''{{armh|Chaberton-ELP|l=arch}}'')</s> <br>{{armh|Cortex-X925|l=arch}} (''{{armh|Blackhawk|l=arch}}'') || {{armh|Cortex-A720AE|l=arch}} (''{{armh|Hunter-AE|l=arch}}'') <br>{{armh|Cortex-A725|l=arch}} (''{{armh|Chaberton|l=arch}}'')
 +
|-
 +
| [[2025]] || {{armh|Cortex-X930|l=arch}} (''{{armh|Travis|l=arch}}'') || {{armh|Cortex-A730|l=arch}} (''{{armh|Gelas|l=arch}}'') <br>{{armh|Cortex-A530|l=arch}} (''{{armh|Nevis|l=arch}}'')
 
|-
 
|-
 
|}
 
|}

Latest revision as of 08:51, 13 May 2025

Edit Values
Cortex-A520 (Hayes) µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionQ4 2023
Process4 nm
Core Configs4
Pipeline
TypeIn-order
OoOENo
SpeculativeYes
Reg RenamingNo
Decode3-way
Instructions
ISAARMv9.2-A
ExtensionsFPU, NEON, SVE, SVE2, TrustZone
Cache
L1I Cache32-64 KiB/core
4-way set associative
L1D Cache32-64 KiB/core
4-way set associative
L2 Cache0-512 KiB/cluster
4-way set associative
L3 Cache256 KiB-32 MiB
(optional)
Succession

Cortex-A520 (Hayes) is a planned ultra-high efficiency Cortex microarchitecture being designed by ARM Holdings as a successor to the Cortex-A510 (Klein). Cortex-A520 is scheduled for introduction around the 2023 timeframe.

Process Technology[edit]

The Cortex-A520 was primarily designed to take advantage of TSMC's 4 nm (TSMC N4P).

Architecture[edit]

Key changes from Cortex-A510[edit]

  • Update to ARMv9.2-A [1]
  • Support only 64-bit applications
  • Up to 512 KiB of private L2 cache (from 256 KiB)
  • 8% peak performance improvement over the Cortex-A510 [2]
  • Add QARMA3 Pointer Authentication (PAC) algorithm support

Comparison[edit]

uArch Cortex-A53 Cortex-A55 Cortex-A510 Cortex-A520 Cortex-A530
Codename Apollo Ananke Klein Hayes Nevis
Peak clock speed 2.3 GHz 2.1 GHz 2.0 GHz 2.0 GHz
Architecture ARMv8.0-A ARMv8.2-A ARMv9.0-A ARMv9.2-A
AArch 32-bit and 64-bit 64-bit
L1-I + L1-D 8/64 + 8/64 KiB 16/64 + 16/64 KiB 32/64 + 32/64 KiB
L2 0–256 KiB 0–512 KiB
L3 ? 0–4 MiB 0–16 MiB 0–32 MiB
Decode Width 2 3 3 (2 ALU)
Dispatch 8

Cortex-X/-A Core[edit]

ARM • Cortex • Microarchitectures
Year Cortex-X Core Cortex-A Core
2020 Cortex-X1 (Hera)
Cortex-X1C (Hera-C) 		Cortex-A78 (Hercules)
Cortex-A78C (Hera Prime)
2021 Cortex-X2
(Matterhorn-ELP) 		Cortex-A710 (Matterhorn)
Cortex-A510 (Klein)
2022 Cortex-X3 (Makalu-ELP) Cortex-A715 (Makalu)
2023 Cortex-X4 (Hunter-ELP) Cortex-A720 (Hunter)
Cortex-A520 (Hayes)
2024 Cortex-X5 (Chaberton-ELP)
Cortex-X925 (Blackhawk) 		Cortex-A720AE (Hunter-AE)
Cortex-A725 (Chaberton)
2025 Cortex-X930 (Travis) Cortex-A730 (Gelas)
Cortex-A530 (Nevis)

Processors[edit]

1× @2.3GHz Kryo Prime (Cortex-A720) +
3× @2.2GHz Kryo Gold (Cortex-A720) +
4× @1.8GHz Kryo Silver (Cortex-A520)
1× 2.8 GHz Kryo Prime (Cortex-X4) +
4× 2.6 GHz Kryo Gold (Cortex-A720) +
3× 1.9 GHz Kryo Silver (Cortex-A520)
1× @2.5GHz Kryo Prime (Cortex-A720) +
3× @2.4GHz Kryo Gold (Cortex-A720) +
4× @1.8GHz Kryo Silver (Cortex-A520)
1× @3.3GHz Kryo Prime (Cortex-X4) +
3× @3.15GHz Kryo Gold (Cortex-A720) +
2× @2.96GHz Kryo Gold (Cortex-A720) +
2× @2.27GHz Kryo Silver (Cortex-A520)
1× @3.05GHz Kryo Prime (Cortex-X4) +
5× @2.96GHz Kryo Gold (Cortex-A720) +
2× @2.04GHz Kryo Silver (Cortex-A520) Q4 2024
1× @3.4GHz Kryo Prime (Cortex-X4) +
3× @3.15GHz Kryo Gold (Cortex-A720) +
2× @2.96GHz Kryo Gold (Cortex-A720) +
2× @2.27GHz Kryo Silver (Cortex-A520)
1× @3.0GHz Kryo Prime (Cortex-X4) +
4× @2.8GHz Kryo Gold (Cortex-A720) +
3× @2.0GHz Kryo Silver (Cortex-A520)

See also[edit]

Reference[edit]

  1. ↑ Cortex-A520.
  2. ↑ Arm Unveils 2023 Mobile CPU Core Designs: Cortex-X4, A720, and A520 - ARMv9.2 Family.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/hayes&oldid=103423"
Facts about "Cortex-A520 - Microarchitectures - ARM"
RDF feed
codenameCortex-A520 (Hayes) +
core count4 +
designerARM Holdings +
first launchedApril 2023 +
full page namearm holdings/microarchitectures/hayes +
instance ofmicroarchitecture +
instruction set architectureARMv9.2-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A520 (Hayes) +
process4 nm (0.004 μm, 4.0e-6 mm) +