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{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
−
|name=Poseidon
+
|name=Neoverse V3
 +
|codename=Poseidon
 +
|features={{\\|Poseidon}}
 +
|core name=[[Neoverse]] (Voyager)
 
|designer=ARM Holdings
 
|designer=ARM Holdings
 
|manufacturer=TSMC
 
|manufacturer=TSMC
−
|introduction=2021
+
|introduction=2023
 
|process=5 nm
 
|process=5 nm
 +
|process 2=4 nm
 
|oooe=Yes
 
|oooe=Yes
 
|speculative=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|renaming=Yes
−
|predecessor=Zeus
+
|isa=ARMv9.0-A
−
|predecessor link=arm_holdings/microarchitectures/zeus
+
|decode=6
 +
|predecessor=Neoverse N1
 +
|predecessor link=arm_holdings/microarchitectures/neoverse n1
 +
|predecessor 2=Neoverse N2
 +
|predecessor 2 link=arm_holdings/microarchitectures/neoverse n2
 +
|predecessor 3=Neoverse V1
 +
|predecessor 3 link=arm_holdings/microarchitectures/neoverse v1
 +
|predecessor 4=Neoverse V2
 +
|predecessor 4 link=arm_holdings/microarchitectures/neoverse v2
 +
|successor=Neoverse N3
 +
|successor link=arm_holdings/microarchitectures/neoverse n3
 +
|successor 2=Neoverse N4
 +
|successor 2 link=arm_holdings/microarchitectures/neoverse n4
 +
|successor 3=Neoverse E4
 +
|successor 3 link=arm_holdings/microarchitectures/neoverse e4
 +
|successor 4=Neoverse V4
 +
|successor 4 link=arm_holdings/microarchitectures/neoverse v4
 
}}
 
}}
−
'''Poseidon''' is the successor to {{\\|Zeus}}, a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
+
 
 +
'''Neoverse V3''' (''{{\\|Poseidon}}'') is the successor to [[Neoverse V1]] (''{{\\|Zeus}}''), a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market.  
 +
 
 +
This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  
 
== History ==
 
== History ==
−
[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]]
+
[[File:arm server roadmap techcon 2018.jpg|thumb|left|Arm's server roadmap.]]
−
Poseidon was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
+
 
 +
{{\\|Poseidon}} was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon [[2018]] keynote.
  
 
== Release Dates ==
 
== Release Dates ==
−
Ares is expected to show up in products around 2021.
+
{{\\|Poseidon}} is expected to show up in products around [[2023]].
 +
{{see also|Neoverse}}
  
 
== Process Technology ==
 
== Process Technology ==
−
Zeus specifically designed takes advantage of the power and area advantages of the [[5nm process]].
+
{{\\|Poseidon}} specifically designed takes advantage of the power and area advantages of the [[5 nm process]].
 +
 
 +
== All Neoverse V1/V2/V3 Processors ==
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 
 +
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc4 tc6 tc9">
 +
{{comp table header|main|9:List of Neoverse V1/V2/V3-based Processors}}
 +
{{comp table header|main|7:Main processor|2:ISA}}
 +
{{comp table header|cols|Part number|Family|Arch|Cores|%Frequency|Process|Launched|ISA|Bits}}
 +
{{#ask: [[Category:all microprocessor models]] [[microarchitecture::~*Neoverse V*]]
 +
|?full page name
 +
|?name
 +
|?model_number
 +
|?family
 +
|?microarchitecture
 +
|?core count
 +
|?base frequency#GHz
 +
|?process
 +
|?first launched
 +
|?isa
 +
|?word_size
 +
|format=template
 +
|template=proc table 3
 +
|userparam=11
 +
|mainlabel=-
 +
|valuesep=,
 +
}}
 +
{{comp table count|ask=[[Category:all microprocessor models]] [[microarchitecture::~*Neoverse V*]]}}
 +
</table>
 +
{{comp table end}}
  
 
== Architecture ==
 
== Architecture ==
−
{{future information}}
+
The codename ''Poseidon'' was first used for the generation succeeding {{\\|Zeus}}, now V1, and targeted for [[2021]] on a [[5 nm]] node.
−
=== Key changes from {{\\|Zeus}} ===
+
 
−
* [[5 nm process]] (from [[7nm]])
+
With codename Poseidon a successor for [[Neoverse V1]] (Zeus) was first publicly mentioned on TechCon [[2018]].
 +
:Actual introduction (used by third party chip designers in their products) was given in form
 +
:of a rough target date of [[2021]]. Its initial realization process is said to be [[5 nm]] by [[TSMC]].
 +
 
 +
=== Neoverse V3 ===
 +
'''Neoverse V3''' (codename ''"Poseidon"'') was teased by [[Arm]] alongside the V2 and E2 announcements.
 +
:It is targeted for systems including DDR5, PCIe Gen 6, and CXL 3.0
 +
 
 +
==== Key changes from [[Neoverse V1]] (''{{\\|Zeus}}'') ====
 
{{expand list}}
 
{{expand list}}
 +
 +
=== Neoverse V2 ===
 +
'''Neoverse V2''' (codename ''"Demeter"'') is derived from the ARM {{armh|Cortex-X3|l=arch}} and implements the ARMv9.0-A instruction set.
 +
:It was officially announced by [[Arm]] on September 14, [[2022]].
 +
 +
==== Key changes from [[Neoverse V1]] ====
 +
*ARMv9.0-A instruction set (from ARMv8.4-A)
 +
*[[4 nm]] process (from [[5 nm]])
 +
*BTB capacity: 12K entries
 +
*TAGE predictor: 8-table
 +
*Micro-op cache: 1536 entries (reduced for efficiency)
 +
*Decode width: 6
 +
*Rename / Dispatch width: 8
 +
*ROB: 320 entry
 +
*Execution ports: 15
 +
*L2 cache: 1024-2048 KB per core
 +
*CMN-700 mesh interconnect
 +
:Up to 256 cores per die
 +
:Up to 512 MB SLC
 +
:Up to 4 TB/s bandwidth
 +
 +
=== Automobile solution ===
 +
*Neoverse V3AE (Poseidon-AE), Neoverse VN (Poseidon-VN) [Auto]
 +
*Neoverse CSS N3 (Pioneer), Neoverse CSS V3 (Voyager)
 +
 +
=== Models ===
 +
:;[[Amazon]] (AWS) • [[Google]] • [[NVIDIA]]
 +
*[[AWS Graviton3]] • 64× [[Neoverse V1]] (2021)
 +
*[[AWS Graviton4]] • 96× [[Neoverse]] V2 (2023)
 +
*[[Google]] Axion • 72× [[Neoverse]] V2 (2023)
 +
*[[NVIDIA]] Tegra Grace (T241) • 72× [[Neoverse]] V2 (2023)
 +
*[[NVIDIA]] Tegra Thor (T264) • [[Neoverse]] V3AE (2024)
  
 
== Bibliography ==
 
== Bibliography ==
 
* Drew Henry keynote, TechCon 2018 keynote.
 
* Drew Henry keynote, TechCon 2018 keynote.
 +
 +
[[Category:arm holdings]]

Latest revision as of 21:00, 23 March 2025

Edit Values
Neoverse V3 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
Introduction2023
Process5 nm, 4 nm
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Decode6
Instructions
ISAARMv9.0-A
FeaturesPoseidon
Cores
Core NamesNeoverse (Voyager)
Succession

Neoverse V3 (Poseidon) is the successor to Neoverse V1 (Zeus), a high-performance ARM microarchitecture designed by ARM Holdings for the server market.

This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

History[edit]

Arm's server roadmap.

Poseidon was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.

Release Dates[edit]

Poseidon is expected to show up in products around 2023.

See also: Neoverse


Process Technology[edit]

Poseidon specifically designed takes advantage of the power and area advantages of the 5 nm process.

All Neoverse V1/V2/V3 Processors[edit]

 List of Neoverse V1/V2/V3-based Processors
 Main processorISA
ModelPart numberFamilyArchCoresFrequencyProcessLaunchedISABits
AWS Graviton3ALC13B00GravitonNeoverse V1642.6 GHz
2,600 MHz
2,600,000 kHz
5 nm
0.005 μm
5.0e-6 mm
30 November 2021ARMv8.4-A64 bit
8 octets
16 nibbles
AWS Graviton4ALC14C00GravitonNeoverse V2962.8 GHz
2,800 MHz
2,800,000 kHz
4 nm
0.004 μm
4.0e-6 mm
28 November 2023ARMv9.0-A64 bit
8 octets
16 nibbles
Count: 2

Architecture[edit]

The codename Poseidon was first used for the generation succeeding Zeus, now V1, and targeted for 2021 on a 5 nm node.

With codename Poseidon a successor for Neoverse V1 (Zeus) was first publicly mentioned on TechCon 2018.

Actual introduction (used by third party chip designers in their products) was given in form
of a rough target date of 2021. Its initial realization process is said to be 5 nm by TSMC.

Neoverse V3[edit]

Neoverse V3 (codename "Poseidon") was teased by Arm alongside the V2 and E2 announcements.

It is targeted for systems including DDR5, PCIe Gen 6, and CXL 3.0

Key changes from Neoverse V1 (Zeus)[edit]

This list is incomplete; you can help by expanding it.

Neoverse V2[edit]

Neoverse V2 (codename "Demeter") is derived from the ARM Cortex-X3 and implements the ARMv9.0-A instruction set.

It was officially announced by Arm on September 14, 2022.

Key changes from Neoverse V1[edit]

  • ARMv9.0-A instruction set (from ARMv8.4-A)
  • 4 nm process (from 5 nm)
  • BTB capacity: 12K entries
  • TAGE predictor: 8-table
  • Micro-op cache: 1536 entries (reduced for efficiency)
  • Decode width: 6
  • Rename / Dispatch width: 8
  • ROB: 320 entry
  • Execution ports: 15
  • L2 cache: 1024-2048 KB per core
  • CMN-700 mesh interconnect
Up to 256 cores per die
Up to 512 MB SLC
Up to 4 TB/s bandwidth

Automobile solution[edit]

  • Neoverse V3AE (Poseidon-AE), Neoverse VN (Poseidon-VN) [Auto]
  • Neoverse CSS N3 (Pioneer), Neoverse CSS V3 (Voyager)

Models[edit]

Amazon (AWS) • Google • NVIDIA

Bibliography[edit]

  • Drew Henry keynote, TechCon 2018 keynote.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/poseidon&oldid=103051"
Facts about "Poseidon - Microarchitectures - ARM"
RDF feed
codenameNeoverse V3 +
designerARM Holdings +
first launched2023 +
full page namearm holdings/microarchitectures/poseidon +
instance ofmicroarchitecture +
instruction set architectureARMv9.0-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse V3 +
process5 nm (0.005 μm, 5.0e-6 mm) + and 4 nm (0.004 μm, 4.0e-6 mm) +