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Difference between revisions of "amd/microarchitectures/zen 4"
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(→‎Key changes from {{\\|Zen 3}}: improved grammar)
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Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on November 6, 2018, AMD stated that Zen 4 was at the design completion phase.
 
Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on November 6, 2018, AMD stated that Zen 4 was at the design completion phase.
  
−
== Process Technology ==
+
== Products ==
−
AMD claims that Zen4 is going to be produced on a [[5nm]] node by [[TSMC]].
 
−
 
 
−
== Codenames ==
 
 
{{future information}}
 
{{future information}}
  
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
−
! Core !! C/T !! Target
+
! Processor Series !! Cores/Threads !! Market
 
|-
 
|-
−
| {{amd|Genoa|l=core}} || Up to 96/192 || High-end server [[multiprocessors]]
+
| EPYC 7004 "{{amd|Genoa|l=core}}" || Up to 96/192 || High-end server [[multiprocessors]]
 
|-
 
|-
 
| {{amd|Warhol|l=core}} || Up to 20/40 || Mainstream to high-end desktops & enthusiasts market processors
 
| {{amd|Warhol|l=core}} || Up to 20/40 || Mainstream to high-end desktops & enthusiasts market processors
Line 39: Line 36:
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
−
! Core !! C/T !! Target
+
! Processor Series !! Cores/Threads !! Market
 
|-
 
|-
 
| {{amd|Bergamo|l=core}} || Up to 128/128?  || Cloud multiprocessing (smaller, almost half-size Zen 4c [referred to as “Zen 4D” in leaks] core likely sacrificing AVX-512, L3 and possibly SMT)
 
| {{amd|Bergamo|l=core}} || Up to 128/128?  || Cloud multiprocessing (smaller, almost half-size Zen 4c [referred to as “Zen 4D” in leaks] core likely sacrificing AVX-512, L3 and possibly SMT)
 
|}
 
|}
 +
 +
== Process Technology ==
 +
AMD claims that Zen4 is going to be produced on a [[5nm]] node by [[TSMC]].
 +
 
== Architecture ==
 
== Architecture ==
−
Little is currently known about the architectural improvements that are being done to Zen 4.
+
{{future information}}
  
 
=== Key changes from {{\\|Zen 3}} ===
 
=== Key changes from {{\\|Zen 3}} ===
−
{{empty section}}
+
* Core
−
*Raised maximum core/thread count from 64/128 to at least 96/192
+
** AVX-512 instructions support
−
(Bergamo supports 128 cores but preliminary data shows a slightly altered architecture featuring cores that take up less space)
+
** L1 and L2 DTLB size increased from 64 to 72 and 2,048 to 3,072 entries
−
*Improved cache load, write and prefetch from/to register (less latency).
+
** L2 cache doubled from 512 KiB to 1 MiB per core
−
*Utilizes new AM5 socket and is confirmed to support DDR5 and PCI-E 5.
+
** Max. physical and linear address size raised from 48 to 52 and 57 bits respectively
−
*Higher Transistor Density, due to 5nm process
+
** Improved cache load, write and prefetch from/to register (less latency).
−
*Double the L2 cache when compared to Zen 3
+
** Higher Transistor Density, due to 5nm process
−
*Capable of higher all-core clockspeeds (shown by AMD to reach 5GHz+ on all cores)
+
** Capable of higher all-core clockspeeds (shown by AMD to reach 5GHz+ on all cores)
 +
* Package
 +
** Raised maximum core/thread count from 64/128 to at least 96/192 (EPYC 7004) (Bergamo supports 128 cores but preliminary data shows a slightly altered architecture featuring cores that take up less space)
 +
** Support for DDR5 memory and PCIe Gen 5
 +
** New sockets {{amd|AM5|l=pack}} (client), {{amd|SP5|l=pack}} (server), {{amd|FP7|FP7/FP7r2|l=pack}} (mobile)
  
−
== Bibliography ==
+
=== New Instructions ===
−
{{reflist}}
+
Zen 4 introduced the following ISA enhancements:
 +
 
 +
<!--Update AVX-512 article when confirmed.-->
 +
* {{x86|AVX-512}} - 512-bit Vector Instructions
 +
** {{x86|AVX512F}} - Foundation (first introduced with [[Intel]] {{intel|skylake (server)|Skylake|l=arch}})
 +
** {{x86|AVX512CD}} - Conflict Detection Instructions ({{intel|Skylake X|l=core}})
 +
** {{x86|AVX512VL}} - Vector Length Extensions (Skylake X)
 +
** {{x86|AVX512DQ}} - Doubleword and Quadword Instructions (Skylake X)
 +
** {{x86|AVX512BW}} - Byte and Word Instructions (Skylake X)
 +
** {{x86|AVX512 IFMA}} - Integer Fused Multiply-Add ({{intel|Cannon Lake|l=arch}})
 +
** {{x86|AVX512 VBMI}} - Vector Bit Manipulation Instructions (Cannon Lake)
 +
** {{x86|AVX512 VPOPCNTDQ}} - Vector Population Count Instruction ({{intel|ice lake (server)|Ice Lake|l=arch}})
 +
** {{x86|AVX512 BITALG}} - Bit Algorithms (Ice Lake)
 +
** {{x86|AVX512 VBMI2}} - Vector Bit Manipulation Instructions 2 (Ice Lake)
 +
** {{x86|AVX512 VNNI}} - Vector Neural Network Instructions (Ice Lake)
 +
** {{x86|AVX512 BF16}} - [[bfloat16|BFloat16]] Instructions ({{intel|Cooper Lake|l=arch}})
 +
** ''Not supported'': AVX512ER, AVX512PF ({{intel|Knights Landing|l=arch}}); AVX512 4VNNIW, 4FMAPS ({{intel|Knights Mill|l=arch}}); VP2INTERSECT ({{intel|Tiger Lake|l=arch}})
 +
* GFNI - Galois Field New Instructions (first introduced with [[Intel]] {{intel|ice lake (server)|Ice Lake|l=arch}})
 +
** <code>VGF2P8AFFINEQB</code> - Galois field affine transformation
 +
** <code>VGF2P8AFFINEINVQB</code> - Galois field affine transformation inverse
 +
** <code>VGF2P8MULB</code> - Galois field multiply bytes
 +
 
 +
=== Memory Hierarchy ===
 +
==== Data and Instruction Caches ====
 +
* L0 Op Cache:
 +
** 4,096(?) Ops per core, 8-way(?) set associative
 +
** 8 Op line size(?)
 +
** Parity protected
 +
* L1I Cache:
 +
** 32 KiB per core, 8-way set associative
 +
** 64 B line size
 +
** Parity protected
 +
* L1D Cache:
 +
** 32 KiB per core, 8-way set associative
 +
** 64 B line size
 +
** Write-back policy
 +
** ? cycles latency for Int
 +
** ? cycles latency for FP
 +
** ECC
 +
* L2 Cache:
 +
** 1 MiB per core, 8-way set associative
 +
** 64 B line size
 +
** Write-back policy
 +
** Inclusive of L1(?)
 +
** ? cycles latency
 +
** {{abbr|DEC-TED}} ECC, tag & state arrays {{abbr|SEC-DED}}<!--7 check bits for 42 tag bits; AMD-55901-0.97 Sec 3.5-->
 +
* L3 Cache:
 +
<!--** "{{amd|Genoa|l=core}}": ? MiB/CCX, up to ? MiB total-->
 +
** Shared by all cores in the CCX, configurable
 +
** 16-way set associative
 +
** 64 B line size
 +
** L2 [[victim cache]](?)
 +
** Write-back policy
 +
** ? cycles average load-to-use latency
 +
** DEC-TED ECC, tag array & shadow tags SEC-DED<!--AMD-55901-0.97 Sec 3.5-->
 +
** QoS Monitoring and Enforcement
 +
 
 +
==== Translation Lookaside Buffers ====
 +
* ITLB
 +
** 64 entry L1 TLB, fully associative, all page sizes
 +
** 512 entry L2 TLB, ?-way set associative
 +
*** 4-Kbyte, 2-Mbyte, and 4-Mbyte pages
 +
** Parity protected
 +
* DTLB
 +
** 72 entry L1 TLB, fully associative, all page sizes
 +
** 3,072 entry L2 TLB, 12-way set associative
 +
*** 4-Kbyte, 2-Mbyte, and 4-Mbyte pages, PDEs to speed up table walks(?)
 +
** Parity protected
 +
 
 +
4-Mbyte pages require two 2-Mbyte entries in all TLBs. <!--TBD: All caches and TLBs are competitively shared in multi-threaded mode.-->
 +
 
 +
==== System DRAM ====
 +
* EPYC 7004 "{{amd|Genoa|l=core}}":
 +
** 12 channels per socket, two 40-bit DDR5 subchannels per channel
 +
** Up to 24 DIMMs, max. ?&nbsp;TiB
 +
** Up to PC5-41600 (DDR5-5200)
 +
** {{abbr|SR}}/{{abbr|DR}} {{abbr|RDIMM}}, {{abbr|4R}}/{{abbr|8R}} {{abbr|LRDIMM}}, {{abbr|3DS DIMM}}
 +
** ECC supported (x4, x8, x16, chipkill)<!--AMD-55901-0.97 Sec 3.7-->
 +
** DRAM bus parity and write data CRC options<!--ibid-->
 +
 
 +
Sources: <ref name="amd-55901-ppr-1910"/>
 +
 
 +
== All Zen 4 Processors ==
 +
<!-- NOTE:
 +
This table is generated automatically from the data in the actual articles.
 +
If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
created and tagged accordingly.
 +
Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
{{comp table start}}
 +
<table class="comptable sortable">
 +
{{comp table header|main|14:List of all Zen 4-based Processors}}
 +
{{comp table header|cols|Family|Codename|{{abbr|C|Cores}}|{{abbr|T|Threads}}|L2|L3|Base|Turbo|Memory|{{abbr|TDP}}|Launched|Price|{{abbr|OPN}}}}
 +
{{comp table header|lsep|14:[[Uniprocessors]]}}
 +
{{#ask: [[Category:microprocessor models by amd]] [[microarchitecture::Zen 4]] [[max cpu count::1]]
 +
|?full page name
 +
|?model number
 +
|?microprocessor family
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?l2$ size
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency#GHz
 +
|?supported memory type
 +
|?tdp
 +
|?first launched
 +
|?release price
 +
|?part number
 +
|sort=model number
 +
|format=template
 +
|template=proc table 3
 +
|userparam=15
 +
|mainlabel=-
 +
|valuesep=,<br/>
 +
}}
 +
{{comp table header|lsep|14:[[Multiprocessors]] (dual-socket)}}
 +
{{#ask: [[Category:microprocessor models by amd]] [[microarchitecture::Zen 4]] [[max cpu count::>>1]]
 +
|?full page name
 +
|?model number
 +
|?microprocessor family
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?l2$ size
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency#GHz
 +
|?supported memory type
 +
|?tdp
 +
|?first launched
 +
|?release price
 +
|?part number
 +
|sort=model number
 +
|format=template
 +
|template=proc table 3
 +
|userparam=15
 +
|mainlabel=-
 +
|valuesep=,<br/>
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by amd]] [[microarchitecture::Zen 4]]}}
 +
</table>
 +
{{comp table end}}
  
 
== Designers ==
 
== Designers ==
Line 63: Line 211:
  
 
== Bibliography ==
 
== Bibliography ==
−
{{reflist}}
+
 
 +
== References ==
 +
<references>
 +
<ref name="amd-55901-ppr-1910">{{cite techdoc|title=Processor Programming Reference (PPR) for AMD Family 19h Models 10h, Revision A0 Processors|publ=AMD|pid=55901|rev=0.97|date=2021-05-30}}</ref>
 +
</references>
  
 
== See Also ==
 
== See Also ==
−
* AMD {{\\|Zen}}
+
* AMD {{\\|Zen}}, {{\\|Zen 2}}, {{\\|Zen 3}}
 
* Intel {{intel|Meteor Lake|l=arch}}
 
* Intel {{intel|Meteor Lake|l=arch}}

Revision as of 15:06, 23 April 2022

Edit Values
Zen 4 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC
Process5 nm
Succession

Zen 4 is a planned microarchitecture being developed by AMD as a successor to Zen 3.

History

Zen 4 on the roadmap.

Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on November 6, 2018, AMD stated that Zen 4 was at the design completion phase.

Products

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Processor Series Cores/Threads Market
EPYC 7004 "Genoa" Up to 96/192 High-end server multiprocessors
Warhol Up to 20/40 Mainstream to high-end desktops & enthusiasts market processors
Rembrandt Up to 8/16 Mainstream desktop & mobile processors with GPU

Cores using variant Zen 4 uarch:

Processor Series Cores/Threads Market
Bergamo Up to 128/128? Cloud multiprocessing (smaller, almost half-size Zen 4c [referred to as “Zen 4D” in leaks] core likely sacrificing AVX-512, L3 and possibly SMT)

Process Technology

AMD claims that Zen4 is going to be produced on a 5nm node by TSMC.

Architecture

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Zen 3

  • Core
    • AVX-512 instructions support
    • L1 and L2 DTLB size increased from 64 to 72 and 2,048 to 3,072 entries
    • L2 cache doubled from 512 KiB to 1 MiB per core
    • Max. physical and linear address size raised from 48 to 52 and 57 bits respectively
    • Improved cache load, write and prefetch from/to register (less latency).
    • Higher Transistor Density, due to 5nm process
    • Capable of higher all-core clockspeeds (shown by AMD to reach 5GHz+ on all cores)
  • Package
    • Raised maximum core/thread count from 64/128 to at least 96/192 (EPYC 7004) (Bergamo supports 128 cores but preliminary data shows a slightly altered architecture featuring cores that take up less space)
    • Support for DDR5 memory and PCIe Gen 5
    • New sockets AM5 (client), SP5 (server), FP7/FP7r2 (mobile)

New Instructions

Zen 4 introduced the following ISA enhancements:

Memory Hierarchy

Data and Instruction Caches

  • L0 Op Cache:
    • 4,096(?) Ops per core, 8-way(?) set associative
    • 8 Op line size(?)
    • Parity protected
  • L1I Cache:
    • 32 KiB per core, 8-way set associative
    • 64 B line size
    • Parity protected
  • L1D Cache:
    • 32 KiB per core, 8-way set associative
    • 64 B line size
    • Write-back policy
    •  ? cycles latency for Int
    •  ? cycles latency for FP
    • ECC
  • L2 Cache:
    • 1 MiB per core, 8-way set associative
    • 64 B line size
    • Write-back policy
    • Inclusive of L1(?)
    •  ? cycles latency
    • DEC-TED ECC, tag & state arrays SEC-DED
  • L3 Cache:
    • Shared by all cores in the CCX, configurable
    • 16-way set associative
    • 64 B line size
    • L2 victim cache(?)
    • Write-back policy
    •  ? cycles average load-to-use latency
    • DEC-TED ECC, tag array & shadow tags SEC-DED
    • QoS Monitoring and Enforcement

Translation Lookaside Buffers

  • ITLB
    • 64 entry L1 TLB, fully associative, all page sizes
    • 512 entry L2 TLB, ?-way set associative
      • 4-Kbyte, 2-Mbyte, and 4-Mbyte pages
    • Parity protected
  • DTLB
    • 72 entry L1 TLB, fully associative, all page sizes
    • 3,072 entry L2 TLB, 12-way set associative
      • 4-Kbyte, 2-Mbyte, and 4-Mbyte pages, PDEs to speed up table walks(?)
    • Parity protected

4-Mbyte pages require two 2-Mbyte entries in all TLBs.

System DRAM

  • EPYC 7004 "Genoa":
    • 12 channels per socket, two 40-bit DDR5 subchannels per channel
    • Up to 24 DIMMs, max. ? TiB
    • Up to PC5-41600 (DDR5-5200)
    • SR/DR RDIMM, 4R/8R LRDIMM, 3DS DIMM
    • ECC supported (x4, x8, x16, chipkill)
    • DRAM bus parity and write data CRC options

Sources: [1]

All Zen 4 Processors

 List of all Zen 4-based Processors
ModelFamilyCodenameCTL2L3BaseTurboMemoryTDPLaunchedPriceOPN
 Uniprocessors
7600XRyzen 5Raphael6126 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
4.7 GHz
4,700 MHz
4,700,000 kHz
5.3 GHz
5,300 MHz
5,300,000 kHz
105 W
105,000 mW
0.141 hp
0.105 kW
7700Ryzen 7Raphael8168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.8 GHz
3,800 MHz
3,800,000 kHz
5.3 GHz
5,300 MHz
5,300,000 kHz
65 W
65,000 mW
0.0872 hp
0.065 kW
10 January 2023$ 339.00
€ 305.10
£ 274.59
¥ 35,028.87
100-000000592,
100-100000592BOX
7700XRyzen 7Raphael8168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
4.5 GHz
4,500 MHz
4,500,000 kHz
5.4 GHz
5,400 MHz
5,400,000 kHz
105 W
105,000 mW
0.141 hp
0.105 kW
27 September 2022$ 399.00
€ 359.10
£ 323.19
¥ 41,228.67
100-000000591,
100-100000591WOF
7800X3DRyzen 7Raphael8168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
96 MiB
98,304 KiB
100,663,296 B
0.0938 GiB
4.2 GHz
4,200 MHz
4,200,000 kHz
5 GHz
5,000 MHz
5,000,000 kHz
120 W
120,000 mW
0.161 hp
0.12 kW
7900X3DRyzen 9Raphael122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
4.4 GHz
4,400 MHz
4,400,000 kHz
5.6 GHz
5,600 MHz
5,600,000 kHz
120 W
120,000 mW
0.161 hp
0.12 kW
7950X3DRyzen 9Raphael163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
4.2 GHz
4,200 MHz
4,200,000 kHz
5.7 GHz
5,700 MHz
5,700,000 kHz
120 W
120,000 mW
0.161 hp
0.12 kW
28 February 2023$ 699.00
€ 629.10
£ 566.19
¥ 72,227.67
100-000000908,
100-000000908WOF
9354PEPYCGenoa326432 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.25 GHz
3,250 MHz
3,250,000 kHz
3.75 GHz
3,750 MHz
3,750,000 kHz
DDR5-4800280 W
280,000 mW
0.375 hp
0.28 kW
10 November 2022$ 2,730.00
€ 2,457.00
£ 2,211.30
¥ 282,090.90
100-100000805,
100-100000805WOF
9454PEPYCGenoa489648 MiB
49,152 KiB
50,331,648 B
0.0469 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.75 GHz
2,750 MHz
2,750,000 kHz
3.65 GHz
3,650 MHz
3,650,000 kHz
DDR5-4800290 W
290,000 mW
0.389 hp
0.29 kW
10 November 2022$ 4,598.00
€ 4,138.20
£ 3,724.38
¥ 475,111.34
100-100000873,
100-100000873WOF
9554PEPYCGenoa6412864 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.1 GHz
3,100 MHz
3,100,000 kHz
3.75 GHz
3,750 MHz
3,750,000 kHz
DDR5-4800360 W
360,000 mW
0.483 hp
0.36 kW
10 November 2022$ 7,104.00
€ 6,393.60
£ 5,754.24
¥ 734,056.32
100-100000804,
100-100000804WOF
9654PEPYCGenoa9619296 MiB
98,304 KiB
100,663,296 B
0.0938 GiB
384 MiB
393,216 KiB
402,653,184 B
0.375 GiB
2.4 GHz
2,400 MHz
2,400,000 kHz
3.55 GHz
3,550 MHz
3,550,000 kHz
DDR5-4800360 W
360,000 mW
0.483 hp
0.36 kW
10 November 2022$ 10,625.00
€ 9,562.50
£ 8,606.25
¥ 1,097,881.25
100-100000803,
100-100000803WOF
 Multiprocessors (dual-socket)
9124EPYCGenoa163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3 GHz
3,000 MHz
3,000,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
DDR5-4800200 W
200,000 mW
0.268 hp
0.2 kW
10 November 2022$ 1,083.00
€ 974.70
£ 877.23
¥ 111,906.39
100-100000802,
100-100000802WOF
9174FEPYCGenoa163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
4.1 GHz
4,100 MHz
4,100,000 kHz
4.15 GHz
4,150 MHz
4,150,000 kHz
DDR5-4800320 W
320,000 mW
0.429 hp
0.32 kW
10 November 2022$ 3,850.00
€ 3,465.00
£ 3,118.50
¥ 397,820.50
100-100000796,
100-100000796WOF
9224EPYCGenoa244824 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
2.5 GHz
2,500 MHz
2,500,000 kHz
3.65 GHz
3,650 MHz
3,650,000 kHz
DDR5-4800200 W
200,000 mW
0.268 hp
0.2 kW
10 November 2022$ 1,825.00
€ 1,642.50
£ 1,478.25
¥ 188,577.25
100-100000939,
100-100000939WOF
9254EPYCGenoa244824 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.9 GHz
2,900 MHz
2,900,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
DDR5-4800200 W
200,000 mW
0.268 hp
0.2 kW
10 November 2022$ 2,299.00
€ 2,069.10
£ 1,862.19
¥ 237,555.67
100-100000480,
100-100000480WOF
9274FEPYCGenoa244824 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
4.05 GHz
4,050 MHz
4,050,000 kHz
4.1 GHz
4,100 MHz
4,100,000 kHz
DDR5-4800320 W
320,000 mW
0.429 hp
0.32 kW
10 November 2022$ 3,060.00
€ 2,754.00
£ 2,478.60
¥ 316,189.80
100-100000794,
100-100000794WOF
9334EPYCGenoa326432 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.7 GHz
2,700 MHz
2,700,000 kHz
3.85 GHz
3,850 MHz
3,850,000 kHz
DDR5-4800210 W
210,000 mW
0.282 hp
0.21 kW
10 November 2022$ 2,990.00
€ 2,691.00
£ 2,421.90
¥ 308,956.70
100-100000800,
100-100000800WOF
9354EPYCGenoa326432 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.25 GHz
3,250 MHz
3,250,000 kHz
3.75 GHz
3,750 MHz
3,750,000 kHz
DDR5-4800280 W
280,000 mW
0.375 hp
0.28 kW
10 November 2022$ 3,420.00
€ 3,078.00
£ 2,770.20
¥ 353,388.60
100-100000798,
100-100000798WOF
9374FEPYCGenoa326432 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.85 GHz
3,850 MHz
3,850,000 kHz
4.1 GHz
4,100 MHz
4,100,000 kHz
DDR5-4800320 W
320,000 mW
0.429 hp
0.32 kW
10 November 2022$ 4,850.00
€ 4,365.00
£ 3,928.50
¥ 501,150.50
100-100000792,
100-100000792WOF
9454EPYCGenoa489648 MiB
49,152 KiB
50,331,648 B
0.0469 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.75 GHz
2,750 MHz
2,750,000 kHz
3.65 GHz
3,650 MHz
3,650,000 kHz
DDR5-4800290 W
290,000 mW
0.389 hp
0.29 kW
10 November 2022$ 5,225.00
€ 4,702.50
£ 4,232.25
¥ 539,899.25
100-100000478,
100-100000478WOF
9474FEPYCGenoa489648 MiB
49,152 KiB
50,331,648 B
0.0469 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.6 GHz
3,600 MHz
3,600,000 kHz
3.95 GHz
3,950 MHz
3,950,000 kHz
DDR5-4800360 W
360,000 mW
0.483 hp
0.36 kW
10 November 2022$ 6,780.00
€ 6,102.00
£ 5,491.80
¥ 700,577.40
100-100000788,
100-100000788WOF
9534EPYCGenoa6412864 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.45 GHz
2,450 MHz
2,450,000 kHz
3.55 GHz
3,550 MHz
3,550,000 kHz
DDR5-4800280 W
280,000 mW
0.375 hp
0.28 kW
10 November 2022$ 8,803.00
€ 7,922.70
£ 7,130.43
¥ 909,613.99
100-100000799,
100-100000799WOF
9554EPYCGenoa6412864 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.1 GHz
3,100 MHz
3,100,000 kHz
3.75 GHz
3,750 MHz
3,750,000 kHz
DDR5-4800360 W
360,000 mW
0.483 hp
0.36 kW
10 November 2022$ 9,087.00
€ 8,178.30
£ 7,360.47
¥ 938,959.71
100-100000790,
100-100000790WOF
9634EPYCGenoa8416884 MiB
86,016 KiB
88,080,384 B
0.082 GiB
384 MiB
393,216 KiB
402,653,184 B
0.375 GiB
2.25 GHz
2,250 MHz
2,250,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
DDR5-4800290 W
290,000 mW
0.389 hp
0.29 kW
10 November 2022$ 10,304.00
€ 9,273.60
£ 8,346.24
¥ 1,064,712.32
100-100000797,
100-100000797WOF
9654EPYCGenoa9619296 MiB
98,304 KiB
100,663,296 B
0.0938 GiB
384 MiB
393,216 KiB
402,653,184 B
0.375 GiB
2.4 GHz
2,400 MHz
2,400,000 kHz
3.55 GHz
3,550 MHz
3,550,000 kHz
DDR5-4800360 W
360,000 mW
0.483 hp
0.36 kW
10 November 2022$ 11,805.00
€ 10,624.50
£ 9,562.05
¥ 1,219,810.65
100-100000789,
100-100000789WOF
Count: 24

Designers

  • Mike Clark(?), chief architect

Bibliography

References

  1. ↑ "Processor Programming Reference (PPR) for AMD Family 19h Models 10h, Revision A0 Processors", AMD Publ. #55901, Rev. 0.97, May 30, 2021

See Also

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/microarchitectures/zen_4&oldid=100078"
Facts about "Zen 4 - Microarchitectures - AMD"
RDF feed
codenameZen 4 +
designerAMD +
full page nameamd/microarchitectures/zen 4 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameZen 4 +
process5 nm (0.005 μm, 5.0e-6 mm) +