• c/complex.h
  ...complex arithmetic implementation conforms to Annex G of the C standard ([[IEEE 754|IEC 60559 standard]]).
  13 KB (1,987 words) - 20:46, 7 January 2015
• microprocessor
  ...neers]]|doi=10.1109/MSPEC.2016.7551353|s2cid=32003640|url=https://spectrum.ieee.org/tech-history/silicon-revolution/the-surprising-story-of-the-first-micro ...in ROM and its data stored in shift register read-write memory.<ref name="ieee"/> Shima's initial design included [[Arithmetic logic unit|arithmetic units
  24 KB (3,399 words) - 11:39, 12 March 2025
• arduino
  ...]].<ref>[http://spectrum.ieee.org/geek-life/hands-on/the-making-of-arduino IEEE Spectrum], accessed on December 24, 2013</ref> Unfortunately their dwindlin
  3 KB (520 words) - 16:56, 19 December 2015
• 3 µm lithography process
  ** Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798. ...l. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.
  3 KB (314 words) - 23:04, 20 May 2018
• 2 µm lithography process
  * Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798. ...l. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.
  8 KB (969 words) - 12:31, 22 February 2019
• 8 µm lithography process
  ...V. Leo. "One-device cells for dynamic random-access memories: A tutorial." IEEE Transactions on Electron Devices 26.6 (1979): 839-852.</ref>.
  5 KB (632 words) - 23:04, 20 May 2018
• mosfet
  ...tion of insulated-gate field-effect transistor switching circuits |journal=IEEE Journal of Solid-State Circuits |volume=SC-3 |issue=3 |pages=285–89 |year ...rever," continued transistor scaling one new material at a time |journal=[[IEEE Transactions on Semiconductor Manufacturing]] |date=2005 |volume=18 |issue=
  193 KB (26,852 words) - 19:51, 11 March 2025
• inverter
  library ieee; use ieee.std_logic_1164.all;
  6 KB (983 words) - 04:50, 8 November 2015
• cmos
  ...f the MOS transistor-from conception to VLSI |journal=[[Proceedings of the IEEE]] |date=October 1988 |volume=76 |issue=10 |pages=1280–1326 (1290) |doi=10 ...t logic using field-effect metal-oxide semiconductor triodes |journal=1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |
  39 KB (5,297 words) - 20:00, 11 March 2025
• logic gate
  * [[ANSI/IEEE Std 91-1984]] (MIL/ANSI)
  5 KB (838 words) - 11:19, 10 February 2020
• microcontroller
  ...omputer processor]] could be contained on a single MOS LSI chip.<ref name="ieee"/> |url=https://spectrum.ieee.org/tech-history/silicon-revolution/chip-hall-of-fame-microchip-technology-
  11 KB (1,575 words) - 20:44, 6 September 2024
• 28 nm lithography process
  ...using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009. ...ow power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
  6 KB (711 words) - 17:01, 26 March 2019
• 32 nm lithography process
  ...ack end with eleven levels of copper." VLSI Technology, 2009 Symposium on. IEEE, 2009. ...t applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
  10 KB (1,107 words) - 21:10, 19 March 2025
• 14 nm lithography process
  ...SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014. ...metallization." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
  18 KB (2,283 words) - 20:34, 19 March 2025
• 45 nm lithography process
  ...packaging." Electron Devices Meeting, 2007. IEDM 2007. IEEE International. IEEE, 2007.
  5 KB (610 words) - 21:39, 19 March 2025
• intel/microarchitectures/bonnell
  ...IA processor for mobile internet devices in 45 nm high-k metal gate CMOS." IEEE Journal of Solid-State Circuits 44.1 (2009): 73-82. ...ference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International. IEEE, 2008.
  38 KB (5,468 words) - 08:27, 18 May 2025
• intel/microarchitectures/haswell (client)
  ...arlund, Per, et al. "Haswell: The fourth-generation intel core processor." IEEE Micro 34.2 (2014): 6-20.
  28 KB (3,890 words) - 14:10, 7 April 2025
• 16 nm lithography process
  ...it [[SRAM]] wafer from their [[16 nm]] HKMG FinFET process at the [[2014]] IEEE ISSCC. TSMC followed their 16FF process by the 16FF+ which provided roughly ...FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 170-177.
  4 KB (582 words) - 15:50, 17 April 2025
• 20 nm lithography process
  ...their 112 Mebibit [[SRAM]] wafer from their 20 nm HKMG process at the 2013 IEEE ISSCC. ...ts Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. IEEE, 2013.
  4 KB (483 words) - 23:04, 20 May 2018
• intel/microarchitectures/sandy bridge (client)
  ...State Circuits Conference]]. A copy of the paper can be [http://ieeexplore.ieee.org/abstract/document/5746311/ found here]. ...ily: Intel® Core i7, i5 and i3." Hot Chips 23 Symposium (HCS), 2011 IEEE. IEEE, 2011.
  84 KB (13,075 words) - 00:54, 29 December 2020

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)