Page title matches

• Advanced Micro Devices
  17 bytes (2 words) - 18:35, 23 December 2015
• Micro Computer Set-8
  25 bytes (3 words) - 18:00, 19 May 2016
• applied micro circuits corporation
  17 bytes (2 words) - 05:23, 12 December 2016
• Applied Micro Circuits Corporation
  17 bytes (2 words) - 05:23, 12 December 2016
• micro-operation
  {{title|Micro-Operation (µOP)}} ...associated with [[CISC]] [[ISA]]s such as [[x86]] and [[z/Architecture]], micro-ops are also used in various [[RISC]] designs such as [[ARM]] and [[POWER]]
  2 KB (208 words) - 13:58, 3 May 2017
• Micro-Operations
  #REDIRECT [[micro-operation]]
  29 bytes (2 words) - 14:58, 23 April 2017
• Micro-Ops
  #REDIRECT [[micro-operation]]
  29 bytes (2 words) - 14:58, 23 April 2017
• micro-ops
  #REDIRECT [[micro-operation]]
  29 bytes (2 words) - 14:58, 23 April 2017
• micro-operations
  #REDIRECT [[micro-operation]]
  29 bytes (2 words) - 18:30, 23 April 2017
• raza micro
  18 bytes (2 words) - 12:16, 28 May 2018
• Raza Micro
  18 bytes (2 words) - 12:16, 28 May 2018
• micro-op
  #REDIRECT [[micro-operation]]
  29 bytes (2 words) - 22:20, 31 May 2018
• micro-instruction
  #REDIRECT [[micro-operation]]
  29 bytes (2 words) - 02:19, 1 October 2018

Page text matches

• Flip Chip Ball Grid Array
  '''μFCBGA''' or '''micro-FCBGA''' is a line of fcBGA packages that ships with Intel's line of proces
  2 KB (239 words) - 07:17, 17 December 2013
• fairchild/pps-25
  The system supported up to 26 ROMs, each consisting of 256 micro-instructions.
  2 KB (291 words) - 23:48, 10 July 2017
• amd/am2900
  ...-bit]] [[bit-slice microprocessor|bit-slice]] chips designed by [[Advanced Micro Devices]] and introduced to the market in August [[1975]]. Each component r
  9 KB (1,061 words) - 22:55, 18 June 2019
• monolithic memories
  ...ctor company]] founded in 1969. On August 1987, MMI merged into [[advanced micro devices|AMD]]. MMI is also known for having invented the [[Programmable Arr
  290 bytes (37 words) - 20:46, 5 November 2015
• fairchild/100k
  ...e standard discrete logic chips, the {{fairchild|F220}} (10022x) series of micro-programmed {{arch|8}} [[bit-slice]] chips. The sub-family was composed of 5
  4 KB (521 words) - 14:38, 11 June 2017
• manufacturer prefix
  | AM || [[Advanced Micro Devices]] ||
  2 KB (253 words) - 06:58, 14 February 2024
• amd
  {{title|Advanced Micro Devices (AMD)}} | name = Advanced Micro Devices
  3 KB (437 words) - 03:14, 20 March 2022
• intel/mcs-4
  The '''MCS-4''' ('''Micro-Computer Set-4''') or '''4000 Series''' or '''Busicom Chip Set''' was a [[m
  4 KB (433 words) - 22:40, 27 June 2019
• general instrument/pic
  ...Instrument]]. This family is the direct ancestor of the modern Microchip {{micro|PIC|PIC family}}. ...Series}}, and , {{micro|PIC/PIC16C84|PIC16C84 Series}}, all part of the {{micro|PIC|PIC extended family}}.
  3 KB (423 words) - 00:33, 19 May 2016
• intel/mcs-40
  The '''MCS-40''' ('''Micro-Computer Set-40''') was a [[microprocessor family|family]] of [[4-bit archi
  2 KB (177 words) - 15:36, 12 May 2016
• amd/am9080
  | image = KL Advanced Micro Devices AM9080.jpg
  5 KB (683 words) - 23:46, 7 March 2018
• intel/mcs-8
  The '''MCS-8''' ('''Micro Computer Set-8''') was a family of {{arch|8}} microprocessor chipsets devel
  3 KB (382 words) - 17:58, 19 May 2016
• intel/mcs-80
  The '''MCS-80''' ('''Micro Computer Set-80''') was a family of {{arch|8}} microprocessor chipsets deve
  4 KB (406 words) - 16:10, 26 January 2019
• intel/microarchitectures/bonnell
  **** 16-entry micro-TLB ...oo complex to handle directly. Those selected few get diverted into the '''micro-code sequencer ROM''' ('''MSROM''') for decoding producing much more sane R
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/silvermont
  ...ectures, common software code had roughly 5% of instructions split up into micro-ops. In Silvermont this is reduced down to just 1-2%. This reduction transl
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/microarchitectures/haswell (client)
  ...ingle fused µOps and an additional 1-4 fused µOps. The unit handles both micro and macro fusions. [[Macro-fusion]] as a result of compatible adjacent µOp ...d, Per, et al. "Haswell: The fourth-generation intel core processor." IEEE Micro 34.2 (2014): 6-20.
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  ...design and entirely different functionality (only used to track in-flight micro-ops) ...or perhaps more appropriately called the Decoded Stream Buffer (DSB). The micro-op cache is unique in that it not only does substantially improve performan
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/core (client)
  * [[:File:01-2 Intel C2 AE Processor Architecture-Core.ppt|Intel® Processor Micro-architecture – Core®]]; Intel® Software College, 2006
  2 KB (251 words) - 21:08, 9 March 2018
• intel/microarchitectures/skylake (client)
  In the back-end, the micro-operations visit the [[reorder buffer]]. It's there where register allocati ...tch windows. In Skylake, the window size has been doubled to 64 bytes. The micro-operation cache is competitively shared between the two threads and can als
  79 KB (11,922 words) - 06:46, 11 November 2022
• 1.3 µm lithography process
  ** {{motorola|68030}}, "Micro 32"
  1 KB (138 words) - 12:57, 23 October 2022

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