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K10 - Microarchitectures - AMD
Edit Values | |
K10 µarch | |
General Info | |
Arch Type | CPU |
Designer | AMD |
Manufacturer | AMD |
Introduction | November 11, 2007 |
Phase-out | 2012 |
Process | 65 nm, 45 nm |
Core Configs | 1, 2, 3, 4, 6 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Reg Renaming | Yes |
Decode | 3 |
Instructions | |
ISA | x86-64 |
Extensions | MMX, SSE, SSE2, SSE3, SSE4A, 3DNow! |
Cache | |
L1I Cache | 64 KiB/core |
L1D Cache | 64 KiB/core |
Succession | |
K10 (sometimes 10h) was the microarchitecture developed by AMD as a successor to K8. K10 was superseded by Bulldozer in 2011.
Architecture[edit]
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Die Shot[edit]
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All K10 Chips[edit]
K10 Chips | ||||||
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Model | Family | Core | Launched | Power Dissipation | Freq | Max Mem |
Count: 0 |
See also[edit]
Facts about "K10 - Microarchitectures - AMD"
codename | K10 + |
core count | 1 +, 2 +, 3 +, 4 + and 6 + |
designer | AMD + |
first launched | November 11, 2007 + |
full page name | amd/microarchitectures/k10 + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | AMD + |
microarchitecture type | CPU + |
name | K10 + |
phase-out | 2012 + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + and 45 nm (0.045 μm, 4.5e-5 mm) + |