Revision as of 14:21, 31 December 2018

Cortex-A15 (codename Eagle) is the successor to the Cortex-A9, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The A15 is the first microarchitecture specifically designed for high-performance, whereas the Cortex-A12 (and the A17), also the successor to the Cortex-A9, target high-efficiency.

Architecture

Key changes from Cortex-A9

• 28 nm process (from 40 nm)
• Longer pipeline (15+, up from 9-12)
  • 1.25x frequency (2.5 GHz, up from 2 GHz)
• 6x larger return stack size (48 entries, up from 8)
• Integer
  • Hardware division support
  • Hardware Fused Multiply-Accumulate
• VFPv4 (from VFPv3)
• NEONv2 (from NEON)
• Memory subsystem
  • Level 1 instruction cache switched to PIPT (from VIPT)
  • Level 1 instruction cache reduced to 2-way set associative (down from 4-way)
  • Level 1 data cache reduced to 2-way set associative (down from 4-way)
  • Added LPAE support

This list is incomplete; you can help by expanding it.

Block Diagram

This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy

This section is empty; you can help add the missing info by editing this page.

Licensees

Arm named the following companies as licensees.