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Zen 4 µarch
General Info
Arch Type	CPU
Designer	AMD
Manufacturer	TSMC
Process	5nm, 6nm
Succession
Zen 3 Zen 5

Zen 4 is a microarchitecture developed by AMD as a successor to Zen 3. See press release for details: AMD Launches Ryzen 7000 Series Desktop Processors

History

Zen 4 on the roadmap.

Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on November 6, 2018, AMD stated that Zen 4 was at the design completion phase.

Codenames

Product Codenames:

Core	C/T	Target
Bergamo	Up to 128/256	High-performance CSP server multiprocessors
Genoa	Up to 96/192	High-end server multiprocessors
Storm Peak	Up to 64/128	Workstation & enthusiasts market processors
Raphael	Up to 16/32	Mainstream to high-end desktops & enthusiasts market processors
Dragon Range	Up to 16/32	High-end mobile processors with GPU
Phoenix Point	Up to 8/16	Mainstream desktop & mobile processors with GPU

Architectural Codenames:

Arch	Codename
Core	Persephone
CCD	Durango

Products

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Processor Series	Cores/Threads	Market
EPYC 9004 "Genoa"	Up to 96/192	High-end server multiprocessors
Ryzen Threadripper 7000 "Storm Peak"	Up to 96/192	Workstation & enthusiasts market processors
Ryzen 7000 "Raphael"	Up to 16/32	Mainstream to high-end desktops & enthusiasts market processors
Ryzen 7000 APU "Dragon Range"	Up to 16/32	High-end mobile processors with GPU
Ryzen 7000 APU "Phoenix Point"	Up to 8/16	Mainstream desktop & mobile processors with GPU

Cores using variant Zen 4 uarch:

Processor Series	Cores/Threads	Market
EPYC 9004 Bergamo	Up to 128/256	Cloud multiprocessors (smaller, almost half-size Zen 4c [referred to as “Zen 4D” in leaks] core sacrificing half of the L3 cache.)

Process Technology

Zen 4 is fabricated using both the 5nm node for the Core Compute Die (CCD) and the 6nm node for the Input/Output Die (IOD) by TSMC.

Architecture

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Zen 3

• Core
  • AVX-512 instructions support (256-bit datapaths)
  • L1 and L2 DTLB size increased from 64 to 72 and 2,048 to 3,072 entries
  • L2 cache doubled from 512 KiB to 1 MiB per core
  • Max. physical and linear address size raised from 48 to 52 and 57 bits respectively
  • Improved cache load, write and prefetch from/to register (less latency)
  • Higher Transistor Density, due to 5nm process
  • Capable of higher all-core clockspeeds (shown by AMD to reach 5GHz+ on all cores)
  • Larger integer register file (from 192 to 224), floating-point register file (from 160 to 192) and reorder buffer (from 256 to 320 entries)
• Package
  • Raised maximum core/thread count from 64/128 to at least 96/192 (EPYC 9004) (Bergamo supports 128 cores but preliminary data shows a slightly altered architecture featuring cores that take up less space)
  • Support for DDR5 memory and PCIe Gen 5
  • New sockets AM5 (client), SP5 (server), SP6 (server), FP7/FP7r2 (mobile)
  • RDNA2-based iGPU with 2 compute units (128 stream processors)

New Instructions

Zen 4 introduced the following ISA enhancements:

• AVX-512 - 512-bit Vector Instructions
  • AVX512F - Foundation (first introduced with Intel Skylake)
  • AVX512CD - Conflict Detection Instructions (Skylake X)
  • AVX512VL - Vector Length Extensions (Skylake X)
  • AVX512DQ - Doubleword and Quadword Instructions (Skylake X)
  • AVX512BW - Byte and Word Instructions (Skylake X)
  • AVX512 IFMA - Integer Fused Multiply-Add (Cannon Lake)
  • AVX512 VBMI - Vector Bit Manipulation Instructions (Cannon Lake)
  • AVX512 VPOPCNTDQ - Vector Population Count Instruction (Ice Lake)
  • AVX512 BITALG - Bit Algorithms (Ice Lake)
  • AVX512 VBMI2 - Vector Bit Manipulation Instructions 2 (Ice Lake)
  • AVX512 VNNI - Vector Neural Network Instructions (Ice Lake)
  • AVX512 BF16 - BFloat16 Instructions (Cooper Lake)
  • Not supported: AVX512ER, AVX512PF (Knights Landing); AVX512 4VNNIW, 4FMAPS (Knights Mill); VP2INTERSECT (Tiger Lake)
• GFNI - Galois Field New Instructions (first introduced with Intel Ice Lake)
  • VGF2P8AFFINEQB - Galois field affine transformation
  • VGF2P8AFFINEINVQB - Galois field affine transformation inverse
  • VGF2P8MULB - Galois field multiply bytes

Memory Hierarchy

Data and Instruction Caches

• L0 Op Cache:
  • 6.75K Ops per core, 8-way(?) set associative
  • 9 Op line size(?)
  • Parity protected
• L1I Cache:
  • 32 KiB per core, 8-way set associative
  • 64 B line size
  • Parity protected
• L1D Cache:
  • 32 KiB per core, 8-way set associative
  • 64 B line size
  • Write-back policy
  •  ? cycles latency for Int
  •  ? cycles latency for FP
  • ECC
• L2 Cache:
  • 1 MiB per core, 8-way set associative
  • 64 B line size
  • Write-back policy
  • Inclusive of L1(?)
  • 14 cycles latency
  • DEC-TED ECC, tag & state arrays SEC-DED
• L3 Cache:
  • Shared by all cores in the CCX, configurable
  • 16-way set associative
  • 64 B line size
  • L2 victim cache(?)
  • Write-back policy
  • 50 cycles average load-to-use latency
  • DEC-TED ECC, tag array & shadow tags SEC-DED
  • QoS Monitoring and Enforcement

Translation Lookaside Buffers

• ITLB
  • 64 entry L1 TLB, fully associative, all page sizes
  • 512 entry L2 TLB, ?-way set associative
    • 4-Kbyte, 2-Mbyte, and 4-Mbyte pages
  • Parity protected
• DTLB
  • 72 entry L1 TLB, fully associative, all page sizes
  • 3,072 entry L2 TLB, 12-way set associative
    • 4-Kbyte, 2-Mbyte, and 4-Mbyte pages, PDEs to speed up table walks(?)
  • Parity protected

4-Mbyte pages require two 2-Mbyte entries in all TLBs.

System DRAM

• Ryzen 7000 "Raphael":
  • Up to PC5-41600 (DDR5-5200) without overclocking
• EPYC 9004 "Genoa":
  • 12 channels per socket, two 40-bit DDR5 subchannels per channel
  • Up to 24 DIMMs, max. ? TiB
  • Up to PC5-44800 (DDR5-5600)
  • SR/DR RDIMM, 4R/8R LRDIMM, 3DS DIMM
  • ECC supported (x4, x8, x16, chipkill)
  • DRAM bus parity and write data CRC options

Sources:

All Zen 4 Processors

	List of all Zen 4-based Processors
Model	Family	Codename	C	T	L2	L3	Base	Turbo	Memory	TDP	Launched	Price	OPN
	Uniprocessors
7600X	Ryzen 5	Raphael	6	12	6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	4.7 GHz 4,700 MHz 4,700,000 kHz	5.3 GHz 5,300 MHz 5,300,000 kHz		105 W 105,000 mW 0.141 hp 0.105 kW
7700X	Ryzen 7	Raphael	8	16	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB	4.5 GHz 4,500 MHz 4,500,000 kHz	5.4 GHz 5,400 MHz 5,400,000 kHz		105 W 105,000 mW 0.141 hp 0.105 kW
	Multiprocessors (dual-socket)
Count: 2

Designers

• Mike Clark(?), chief architect

See Also

• AMD Zen, Zen 2, Zen 3
• Intel Meteor Lake